| Martin Roth | d75800c | 2014-05-12 21:56:27 -0600 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2007-2009 coresystems GmbH |
| 5 | * Copyright (C) 2011 Google Inc. |
| 6 | * Copyright (C) 2014 Sage Electronic Engineering, LLC. |
| 7 | * |
| 8 | * This program is free software; you can redistribute it and/or modify |
| 9 | * it under the terms of the GNU General Public License as published by |
| 10 | * the Free Software Foundation; version 2 of the License. |
| 11 | * |
| 12 | * This program is distributed in the hope that it will be useful, |
| 13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 15 | * GNU General Public License for more details. |
| Martin Roth | d75800c | 2014-05-12 21:56:27 -0600 | [diff] [blame] | 16 | */ |
| 17 | |
| 18 | #define INCLUDE_LPE 1 |
| 19 | #define INCLUDE_SCC 1 |
| 20 | #define INCLUDE_EHCI 1 |
| 21 | #define INCLUDE_XHCI 1 |
| 22 | #define INCLUDE_LPSS 1 |
| 23 | |
| 24 | |
| 25 | DefinitionBlock( |
| 26 | "dsdt.aml", |
| 27 | "DSDT", |
| 28 | 0x02, // DSDT revision: ACPI v2.0 |
| 29 | "COREv4", // OEM id |
| 30 | "COREBOOT", // OEM table id |
| 31 | 0x20110725 // OEM revision |
| 32 | ) |
| 33 | { |
| 34 | // Some generic macros |
| 35 | #include <soc/intel/fsp_baytrail/acpi/platform.asl> |
| 36 | |
| 37 | // global NVS and variables |
| 38 | #include <soc/intel/fsp_baytrail/acpi/globalnvs.asl> |
| 39 | |
| 40 | #include <soc/intel/fsp_baytrail/acpi/cpu.asl> |
| 41 | |
| 42 | Scope (\_SB) { |
| 43 | Device (PCI0) |
| 44 | { |
| 45 | #include <soc/intel/fsp_baytrail/acpi/southcluster.asl> |
| 46 | } |
| 47 | } |
| 48 | |
| 49 | /* Chipset specific sleep states */ |
| 50 | #include <soc/intel/fsp_baytrail/acpi/sleepstates.asl> |
| 51 | |
| 52 | #include "acpi/mainboard.asl" |
| 53 | } |