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Ricardo Martins0ca02552012-07-04 03:09:49 +01001/*
2 * This file is part of the coreboot project.
3 *
4 * Copyright (C) 2012 Ricardo Martins <rasmartins@gmail.com>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
Ricardo Martins0ca02552012-07-04 03:09:49 +010015 */
16
17#include <device/pci_ids.h>
18#include <arch/pirq_routing.h>
19
20/* Platform IRQs */
21#define PIRQA 10
22#define PIRQB 11
23#define PIRQC 11
24#define PIRQD 11
25
26/* Links */
27#define L_PIRQA 1
28#define L_PIRQB 2
29#define L_PIRQC 3
30#define L_PIRQD 4
31
32/* Bitmaps */
33#define B_LINK0 (1 << PIRQA)
34#define B_LINK1 (1 << PIRQB)
35#define B_LINK2 (1 << PIRQC)
36#define B_LINK3 (1 << PIRQD)
37
Stefan Reinauera47bd912012-11-15 15:15:15 -080038static const struct irq_routing_table intel_irq_routing_table = {
Ricardo Martins0ca02552012-07-04 03:09:49 +010039 PIRQ_SIGNATURE, /* u32 signature */
40 PIRQ_VERSION, /* u16 version */
41 32 + 16 * CONFIG_IRQ_SLOT_COUNT, /* Max. number of devices on the bus */
42 0x00, /* Interrupt router bus */
43 0x0f << 3, /* Interrupt router dev */
44 B_LINK0 | B_LINK1 | B_LINK2 | B_LINK3, /* IRQs devoted exclusively to PCI usage */
45 PCI_VENDOR_ID_AMD, /* Vendor */
46 PCI_DEVICE_ID_AMD_CS5536_ISA, /* Device */
47 0, /* Miniport */
48 {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, /* Reserved */
49 0xa6, /* Checksum */
50 {
51 [0] = { /* Host bridge */
52 .slot = 0x00,
53 .bus = 0x00,
54 .devfn = (0x01 << 3) | 0x0,
55 .irq = {
56 [0] = {
57 .link = L_PIRQA,
58 .bitmap = B_LINK0
59 },
60 [1] = {
61 .link = L_PIRQB,
62 .bitmap = B_LINK1
63 },
64 [2] = {
65 .link = L_PIRQC,
66 .bitmap = B_LINK2
67 },
68 [3] = {
69 .link = L_PIRQD,
70 .bitmap = B_LINK3
71 }
72 }
73 },
74
75 [1] = { /* ISA bridge */
76 .slot = 0x00,
77 .bus = 0x00,
78 .devfn = (0x0f << 3) | 0x0,
79 .irq = {
80 [0] = {
81 .link = L_PIRQA,
82 .bitmap = B_LINK0
83 },
84 [1] = {
85 .link = L_PIRQB,
86 .bitmap = B_LINK1
87 },
88 [2] = {
89 .link = L_PIRQC,
90 .bitmap = B_LINK2
91 },
92 [3] = {
93 .link = L_PIRQD,
94 .bitmap = B_LINK3
95 }
96 }
97 },
98
99 [2] = { /* Ethernet */
100 .slot = 0x00,
101 .bus = 0x00,
102 .devfn = (0x0e << 3) | 0x0,
103 .irq = {
104 [0] = {
105 .link = L_PIRQD,
106 .bitmap = B_LINK3
107 },
108 [1] = {
109 .link = L_PIRQA,
110 .bitmap = B_LINK0
111 },
112 [2] = {
113 .link = L_PIRQB,
114 .bitmap = B_LINK1
115 },
116 [3] = {
117 .link = L_PIRQC,
118 .bitmap = B_LINK2
119 }
120 }
121 },
122
123 [3] = { /* PCI Connector - Slot 0 */
124 .slot = 0x01,
125 .bus = 0x00,
126 .devfn = (0x09 << 3) | 0x0,
127 .irq = {
128 [0] = {
129 .link = L_PIRQA,
130 .bitmap = B_LINK0
131 },
132 [1] = {
133 .link = L_PIRQB,
134 .bitmap = B_LINK1
135 },
136 [2] = {
137 .link = L_PIRQC,
138 .bitmap = B_LINK2
139 },
140 [3] = {
141 .link = L_PIRQD,
142 .bitmap = B_LINK3
143 }
144 }
145 },
146
147 [4] = { /* PCI Connector - Slot 1 */
148 .slot = 0x02,
149 .bus = 0x00,
150 .devfn = (0x0c << 3) | 0x0,
151 .irq = {
152 [0] = {
153 .link = L_PIRQB,
154 .bitmap = B_LINK1
155 },
156 [1] = {
157 .link = L_PIRQC,
158 .bitmap = B_LINK2
159 },
160 [2] = {
161 .link = L_PIRQD,
162 .bitmap = B_LINK3
163 },
164 [3] = {
165 .link = L_PIRQA,
166 .bitmap = B_LINK0
167 }
168 }
169 },
170
171 [5] = { /* PCI Connector - Slot 2 */
172 .slot = 0x03,
173 .bus = 0x00,
174 .devfn = (0x0b << 3) | 0x0,
175 .irq = {
176 [0] = {
177 .link = L_PIRQC,
178 .bitmap = B_LINK2
179 },
180 [1] = {
181 .link = L_PIRQD,
182 .bitmap = B_LINK3
183 },
184 [2] = {
185 .link = L_PIRQA,
186 .bitmap = B_LINK0
187 },
188 [3] = {
189 .link = L_PIRQB,
190 .bitmap = B_LINK1
191 }
192 }
193 },
194
195 [6] = { /* PCI Connector - Slot 3 */
196 .slot = 0x04,
197 .bus = 0x00,
198 .devfn = (0x0a << 3) | 0x0,
199 .irq = {
200 [0] = {
201 .link = L_PIRQD,
202 .bitmap = B_LINK3
203 },
204 [1] = {
205 .link = L_PIRQA,
206 .bitmap = B_LINK0
207 },
208 [2] = {
209 .link = L_PIRQB,
210 .bitmap = B_LINK1
211 },
212 [3] = {
213 .link = L_PIRQC,
214 .bitmap = B_LINK2
215 }
216 }
217 }
218 }
219};
220
221unsigned long write_pirq_routing_table(unsigned long addr)
222{
Stefan Reinauera47bd912012-11-15 15:15:15 -0800223 return copy_pirq_routing_table(addr, &intel_irq_routing_table);
Ricardo Martins0ca02552012-07-04 03:09:49 +0100224}