| Marc Jones | 738347e | 2010-09-13 19:24:38 +0000 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2010 Advanced Micro Devices, Inc. |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or modify |
| 7 | * it under the terms of the GNU General Public License as published by |
| 8 | * the Free Software Foundation; version 2 of the License. |
| 9 | * |
| 10 | * This program is distributed in the hope that it will be useful, |
| 11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 13 | * GNU General Public License for more details. |
| Marc Jones | 738347e | 2010-09-13 19:24:38 +0000 | [diff] [blame] | 14 | */ |
| 15 | |
| 16 | /* This file defines the processor and performance state capability |
| 17 | * for each core in the system. It is included into the DSDT for each |
| 18 | * core. It assumes that each core of the system has the same performance |
| 19 | * characteristics. |
| 20 | */ |
| 21 | /* |
| 22 | DefinitionBlock ("DSDT.AML","DSDT",0x01,"XXXXXX","XXXXXXXX",0x00010001) |
| 23 | { |
| 24 | Scope (\_PR) { |
| 25 | Processor(CPU0,0,0x808,0x06) { |
| 26 | #include "cpstate.asl" |
| 27 | } |
| 28 | Processor(CPU1,1,0x0,0x0) { |
| 29 | #include "cpstate.asl" |
| 30 | } |
| 31 | Processor(CPU2,2,0x0,0x0) { |
| 32 | #include "cpstate.asl" |
| 33 | } |
| 34 | Processor(CPU3,3,0x0,0x0) { |
| 35 | #include "cpstate.asl" |
| 36 | } |
| 37 | } |
| 38 | */ |
| 39 | /* P-state support: The maximum number of P-states supported by the */ |
| 40 | /* CPUs we'll use is 6. */ |
| 41 | /* Get from AMI BIOS. */ |
| 42 | Name(_PSS, Package(){ |
| 43 | Package () |
| 44 | { |
| 45 | 0x00000AF0, |
| 46 | 0x0000BF81, |
| 47 | 0x00000002, |
| 48 | 0x00000002, |
| 49 | 0x00000000, |
| 50 | 0x00000000 |
| 51 | }, |
| 52 | |
| 53 | Package () |
| 54 | { |
| 55 | 0x00000578, |
| 56 | 0x000076F2, |
| 57 | 0x00000002, |
| 58 | 0x00000002, |
| 59 | 0x00000001, |
| 60 | 0x00000001 |
| 61 | } |
| 62 | }) |
| 63 | |
| 64 | Name(_PCT, Package(){ |
| 65 | ResourceTemplate(){Register(FFixedHW, 0, 0, 0)}, |
| 66 | ResourceTemplate(){Register(FFixedHW, 0, 0, 0)} |
| 67 | }) |
| 68 | |
| 69 | Method(_PPC, 0){ |
| 70 | Return(0) |
| 71 | } |