blob: bf16858b6c9d5d092a8e72c424718fc67b627116 [file] [log] [blame]
Matt DeVillierc12e5ae2016-11-27 02:19:02 -06001/*
2 * This file is part of the coreboot project.
3 *
4 * Copyright (C) 2012 Google Inc.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; version 2 of the License.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 */
15
16#include <types.h>
17#include <string.h>
18#include <cbmem.h>
19#include <console/console.h>
20#include <arch/acpi.h>
21#include <arch/ioapic.h>
22#include <arch/acpigen.h>
23#include <arch/smp/mpspec.h>
24#include <device/device.h>
25#include <device/pci.h>
26#include <device/pci_ids.h>
Matt DeVillierc12e5ae2016-11-27 02:19:02 -060027#include <vendorcode/google/chromeos/gnvs.h>
28#include <ec/google/chromeec/ec.h>
29
30#include <southbridge/intel/lynxpoint/pch.h>
31#include <southbridge/intel/lynxpoint/nvs.h>
32#include "thermal.h"
33
34static void acpi_update_thermal_table(global_nvs_t *gnvs)
35{
36 gnvs->tmps = TEMPERATURE_SENSOR_ID;
37 gnvs->tcrt = CRITICAL_TEMPERATURE;
38 gnvs->tpsv = PASSIVE_TEMPERATURE;
39 gnvs->tmax = MAX_TEMPERATURE;
40 gnvs->f0pw = EC_THROTTLE_POWER_LIMIT;
41 gnvs->flvl = 1;
42}
43
44void acpi_create_gnvs(global_nvs_t *gnvs)
45{
46 /* Enable USB ports in S3 */
47 gnvs->s3u0 = 1;
48 gnvs->s3u1 = 1;
49
50 /* Disable USB ports in S5 */
51 gnvs->s5u0 = 0;
52 gnvs->s5u1 = 0;
53
54 /* TPM Present */
55 gnvs->tpmp = 1;
56
57
58#if CONFIG_CHROMEOS
59 gnvs->chromeos.vbt2 = google_ec_running_ro() ?
60 ACTIVE_ECFW_RO : ACTIVE_ECFW_RW;
61#endif
62
63 acpi_update_thermal_table(gnvs);
64}
65
66unsigned long acpi_fill_madt(unsigned long current)
67{
68 /* Local APICs */
69 current = acpi_create_madt_lapics(current);
70
71 /* IOAPIC */
72 current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current,
73 2, IO_APIC_ADDR, 0);
74
75 /* INT_SRC_OVR */
76 current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *)
77 current, 0, 0, 2, 0);
78 current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *)
79 current, 0, 9, 9, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_HIGH);
80
81 return current;
82}