| Andrew Wu | 8522f99 | 2013-07-05 17:29:41 +0800 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2013 DMP Electronics Inc. |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or modify |
| 7 | * it under the terms of the GNU General Public License as published by |
| 8 | * the Free Software Foundation; version 2 of the License. |
| 9 | * |
| 10 | * This program is distributed in the hope that it will be useful, |
| 11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 13 | * GNU General Public License for more details. |
| Andrew Wu | 8522f99 | 2013-07-05 17:29:41 +0800 | [diff] [blame] | 14 | */ |
| 15 | |
| 16 | #include <arch/pirq_routing.h> |
| 17 | |
| 18 | static const struct irq_routing_table intel_irq_routing_table = { |
| 19 | PIRQ_SIGNATURE, /* u32 signature */ |
| 20 | PIRQ_VERSION, /* u16 version */ |
| 21 | 32 + 16 * 12, /* Max. number of devices on the bus */ |
| 22 | 0x00, /* Interrupt router bus */ |
| 23 | (0x07 << 3) | 0x0, /* Interrupt router dev */ |
| 24 | 0, /* IRQs devoted exclusively to PCI usage */ |
| 25 | 0x17f3, /* Vendor */ |
| 26 | 0x6031, /* Device */ |
| 27 | 0, /* Miniport */ |
| 28 | { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* u8 rfu[11] */ |
| 29 | 0xa, /* Checksum (has to be set to some value that |
| 30 | * would give 0 after the sum of all bytes |
| 31 | * for this structure (including checksum). |
| 32 | */ |
| 33 | { |
| 34 | /* bus, dev | fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */ |
| 35 | {0x00, (0x01 << 3) | 0x0, {{0x01, 0xdef8}, {0x02, 0xdef8}, {0x03, 0xdef8}, {0x04, 0xdef8}}, 0x1, 0x0}, |
| 36 | {0x00, (0x02 << 3) | 0x0, {{0x02, 0xdef8}, {0x03, 0xdef8}, {0x04, 0xdef8}, {0x01, 0xdef8}}, 0x2, 0x0}, |
| 37 | {0x00, (0x03 << 3) | 0x0, {{0x03, 0xdef8}, {0x04, 0xdef8}, {0x01, 0xdef8}, {0x02, 0xdef8}}, 0x0, 0x0}, |
| 38 | {0x00, (0x04 << 3) | 0x0, {{0x04, 0xdef8}, {0x01, 0xdef8}, {0x02, 0xdef8}, {0x03, 0xdef8}}, 0x4, 0x0}, |
| 39 | {0x00, (0x05 << 3) | 0x0, {{0x01, 0xdef8}, {0x02, 0xdef8}, {0x03, 0xdef8}, {0x04, 0xdef8}}, 0x5, 0x0}, |
| 40 | {0x00, (0x06 << 3) | 0x0, {{0x02, 0xdef8}, {0x03, 0xdef8}, {0x04, 0xdef8}, {0x01, 0xdef8}}, 0x6, 0x0}, |
| 41 | {0x00, (0x08 << 3) | 0x0, {{0x05, 0xdef8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x0000}}, 0x0, 0x0}, |
| 42 | {0x00, (0x0a << 3) | 0x0, {{0x07, 0xdef8}, {0x08, 0xdef8}, {0x00, 0x0000}, {0x00, 0x0000}}, 0x0, 0x0}, |
| 43 | {0x00, (0x0b << 3) | 0x0, {{0x09, 0xdef8}, {0x0a, 0xdef8}, {0x00, 0x0000}, {0x00, 0x0000}}, 0x0, 0x0}, |
| 44 | {0x00, (0x0c << 3) | 0x0, {{0x0b, 0xdef8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x0000}}, 0x0, 0x0}, |
| 45 | {0x00, (0x0f << 3) | 0x0, {{0x0d, 0xdef8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x0000}}, 0x0, 0x0}, |
| 46 | {0x00, (0x0e << 3) | 0x0, {{0x0e, 0xdef8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x0000}}, 0x0, 0x0}, |
| 47 | } |
| 48 | }; |
| 49 | |
| 50 | unsigned long write_pirq_routing_table(unsigned long addr) |
| 51 | { |
| 52 | return copy_pirq_routing_table(addr, &intel_irq_routing_table); |
| 53 | } |