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Uwe Hermann6d90afe2007-10-31 00:25:06 +00001/*
Stefan Reinauer7e61e452008-01-18 10:35:56 +00002 * This file is part of the coreboot project.
Uwe Hermann6d90afe2007-10-31 00:25:06 +00003 *
4 * Copyright (C) 2007 Uwe Hermann <uwe@hermann-uwe.de>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
Uwe Hermann6d90afe2007-10-31 00:25:06 +000015 */
16
17#include <arch/pirq_routing.h>
18
Stefan Reinauera47bd912012-11-15 15:15:15 -080019static const struct irq_routing_table intel_irq_routing_table = {
Uwe Hermann6d90afe2007-10-31 00:25:06 +000020 PIRQ_SIGNATURE,
21 PIRQ_VERSION,
Stefan Reinauer08670622009-06-30 15:17:49 +000022 32 + 16 * CONFIG_IRQ_SLOT_COUNT,/* Max. number of devices on the bus */
Uwe Hermann6d90afe2007-10-31 00:25:06 +000023 0x00, /* Interrupt router bus */
24 (0x07 << 3) | 0x0, /* Interrupt router device */
25 0xc00, /* IRQs devoted exclusively to PCI usage */
26 0x8086, /* Vendor */
27 0x7000, /* Device */
Uwe Hermann8fa90ec2010-09-21 21:16:27 +000028 0, /* Miniport data */
Uwe Hermann6d90afe2007-10-31 00:25:06 +000029 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* u8 rfu[11] */
30 0xc7, /* Checksum */
31 {
Elyes HAOUAS6350a2e2016-09-16 20:49:38 +020032 /* bus, dev|fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */
33 {0x00,(0x08 << 3)|0x0, {{0x60, 0xdeb8}, {0x61, 0xdeb8}, {0x62, 0xdeb8}, {0x63, 0x0deb8}}, 0x1, 0x0},
34 {0x00,(0x09 << 3)|0x0, {{0x61, 0xdeb8}, {0x62, 0xdeb8}, {0x63, 0xdeb8}, {0x60, 0x0deb8}}, 0x2, 0x0},
35 {0x00,(0x0a << 3)|0x0, {{0x62, 0xdeb8}, {0x63, 0xdeb8}, {0x60, 0xdeb8}, {0x61, 0x0deb8}}, 0x3, 0x0},
36 {0x00,(0x0b << 3)|0x0, {{0x63, 0xdeb8}, {0x60, 0xdeb8}, {0x61, 0xdeb8}, {0x62, 0x0deb8}}, 0x4, 0x0},
37 {0x00,(0x07 << 3)|0x1, {{0x60, 0xdeb8}, {0x61, 0xdeb8}, {0x00, 0xdeb8}, {0x00, 0x0deb8}}, 0x0, 0x0},
38 {0x00,(0x01 << 3)|0x0, {{0x60, 0xdeb8}, {0x61, 0xdeb8}, {0x62, 0xdeb8}, {0x63, 0x0deb8}}, 0x0, 0x0},
39 {0x00,(0x07 << 3)|0x2, {{0x00, 0xdeb8}, {0x00, 0xdeb8}, {0x00, 0xdeb8}, {0x63, 0x0deb8}}, 0x0, 0x0},
Uwe Hermann6d90afe2007-10-31 00:25:06 +000040 }
41};
42
43unsigned long write_pirq_routing_table(unsigned long addr)
44{
Stefan Reinauera47bd912012-11-15 15:15:15 -080045 return copy_pirq_routing_table(addr, &intel_irq_routing_table);
Uwe Hermann6d90afe2007-10-31 00:25:06 +000046}