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review.coreboot.org / coreboot / a50ced2eba20a007fa5b486c251c252ad09868cf / . / src / mainboard / biostar / am1ml / mptable.c
blob: af38362145884c15b23fd12fa879a2b9c39e63aa [file] [log] [blame]
Sergej Ivanovd777c782015-04-03 18:10:27 +0300[diff] [blame]1/*
2 * This file is part of the coreboot project.
3 *
4 * Copyright (C) 2012 Advanced Micro Devices, Inc.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; version 2 of the License.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
Sergej Ivanovd777c782015-04-03 18:10:27 +0300[diff] [blame]14 */
15
16#include <console/console.h>
17#include <arch/smp/mpspec.h>
18#include <device/pci.h>
19#include <arch/io.h>
20#include <arch/ioapic.h>
21#include <string.h>
22#include <stdint.h>
23#include <cpu/amd/amdfam16.h>
24#include <arch/cpu.h>
25#include <cpu/x86/lapic.h>
Stefan Reinauer13e41822015-04-27 14:02:36 -0700[diff] [blame]26#include <southbridge/amd/common/amd_pci_util.h>
Sergej Ivanovd777c782015-04-03 18:10:27 +0300[diff] [blame]27#include <drivers/generic/ioapic/chip.h>
28
29static void *smp_write_config_table(void *v)
30{
31 struct mp_config_table *mc;
32 int bus_isa;
33
34 /*
35 * By the time this function gets called, the IOAPIC registers
36 * have been written so they can be read to get the correct
37 * APIC ID and Version
38 */
39 u8 ioapic_id = (io_apic_read(VIO_APIC_VADDR, 0x00) >> 24);
40 u8 ioapic_ver = (io_apic_read(VIO_APIC_VADDR, 0x01) & 0xFF);
41
42 /* Intialize the MP_Table */
43 mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
44
45 mptable_init(mc, LOCAL_APIC_ADDR);
46
47 /*
48 * Type 0: Processor Entries:
49 * LAPIC ID, LAPIC Version, CPU Flags:EN/BP,
50 * CPU Signature (Stepping, Model, Family),
51 * Feature Flags
52 */
53 smp_write_processors(mc);
54
55 /*
56 * Type 1: Bus Entries:
57 * Bus ID, Bus Type
58 */
59 mptable_write_buses(mc, NULL, &bus_isa);
60
61 /*
62 * Type 2: I/O APICs:
63 * APIC ID, Version, APIC Flags:EN, Address
64 */
65 smp_write_ioapic(mc, ioapic_id, ioapic_ver, VIO_APIC_VADDR);
66
67 /*
68 * Type 3: I/O Interrupt Table Entries:
69 * Int Type, Int Polarity, Int Level, Source Bus ID,
70 * Source Bus IRQ, Dest APIC ID, Dest PIN#
71 */
72 mptable_add_isa_interrupts(mc, bus_isa, ioapic_id, 0);
73
74 /* PCI interrupts are level triggered, and are
75 * associated with a specific bus/device/function tuple.
76 */
77#define PCI_INT(bus, dev, fn, pin) \
78 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(fn)), ioapic_id, (pin))
79
80 /* APU Internal Graphic Device */
81 PCI_INT(0x0, 0x01, 0x0, intr_data_ptr[PIRQ_C]);
82 PCI_INT(0x0, 0x01, 0x1, intr_data_ptr[PIRQ_D]);
83
84 /* SMBUS / ACPI */
85 PCI_INT(0x0, 0x14, 0x0, intr_data_ptr[PIRQ_SMBUS]);
86
87 /* Southbridge HD Audio */
88 PCI_INT(0x0, 0x14, 0x2, intr_data_ptr[PIRQ_HDA]);
89
90 /* LPC */
91 PCI_INT(0x0, 0x14, 0x3, intr_data_ptr[PIRQ_C]);
92
93 /* USB */
94 PCI_INT(0x0, 0x12, 0x0, intr_data_ptr[PIRQ_OHCI1]);
95 PCI_INT(0x0, 0x12, 0x2, intr_data_ptr[PIRQ_EHCI1]);
96 PCI_INT(0x0, 0x13, 0x0, intr_data_ptr[PIRQ_OHCI2]);
97 PCI_INT(0x0, 0x13, 0x2, intr_data_ptr[PIRQ_EHCI2]);
98 PCI_INT(0x0, 0x16, 0x0, intr_data_ptr[PIRQ_OHCI3]);
99 PCI_INT(0x0, 0x16, 0x2, intr_data_ptr[PIRQ_EHCI3]);
100 PCI_INT(0x0, 0x14, 0x2, intr_data_ptr[PIRQ_OHCI4]);
101
102 /* SATA */
103 PCI_INT(0x0, 0x11, 0x0, intr_data_ptr[PIRQ_SATA]);
104
105 /* on board NIC & Slot PCIE */
106 PCI_INT(0x1, 0x0, 0x0, intr_data_ptr[PIRQ_E]);
107 PCI_INT(0x2, 0x0, 0x0, intr_data_ptr[PIRQ_F]);
108
109 /* PCI slots */
110 device_t dev = dev_find_slot(0, PCI_DEVFN(0x14, 4));
111 if (dev && dev->enabled) {
112 u8 bus_pci = dev->link_list->secondary;
113 /* PCI_SLOT 0 */
114 PCI_INT(bus_pci, 0x5, 0x0, intr_data_ptr[PIRQ_E]);
115 PCI_INT(bus_pci, 0x5, 0x1, intr_data_ptr[PIRQ_F]);
116 PCI_INT(bus_pci, 0x5, 0x2, intr_data_ptr[PIRQ_G]);
117 PCI_INT(bus_pci, 0x5, 0x3, intr_data_ptr[PIRQ_H]);
118
119 /* PCI_SLOT 1 */
120 PCI_INT(bus_pci, 0x6, 0x0, intr_data_ptr[PIRQ_F]);
121 PCI_INT(bus_pci, 0x6, 0x1, intr_data_ptr[PIRQ_G]);
122 PCI_INT(bus_pci, 0x6, 0x2, intr_data_ptr[PIRQ_H]);
123 PCI_INT(bus_pci, 0x6, 0x3, intr_data_ptr[PIRQ_E]);
124
125 /* PCI_SLOT 2 */
126 PCI_INT(bus_pci, 0x7, 0x0, intr_data_ptr[PIRQ_G]);
127 PCI_INT(bus_pci, 0x7, 0x1, intr_data_ptr[PIRQ_H]);
128 PCI_INT(bus_pci, 0x7, 0x2, intr_data_ptr[PIRQ_E]);
129 PCI_INT(bus_pci, 0x7, 0x3, intr_data_ptr[PIRQ_F]);
130
131 PCI_INT(bus_pci, 0x0, 0x0, intr_data_ptr[PIRQ_C]);
132 PCI_INT(bus_pci, 0x0, 0x1, intr_data_ptr[PIRQ_D]);
133 PCI_INT(bus_pci, 0x0, 0x2, intr_data_ptr[PIRQ_E]);
134 }
135
136 /* PCIe Lan*/
137 //PCI_INT(0x0, 0x06, 0x0, intr_data_ptr[PIRQ_D]);
138
139 /* FCH PCIe PortA */
140 PCI_INT(0x0, 0x15, 0x0, intr_data_ptr[PIRQ_A]);
141 /* FCH PCIe PortB */
142 PCI_INT(0x0, 0x15, 0x1, intr_data_ptr[PIRQ_B]);
143 /* FCH PCIe PortC */
144 PCI_INT(0x0, 0x15, 0x2, intr_data_ptr[PIRQ_C]);
145 /* FCH PCIe PortD */
146 PCI_INT(0x0, 0x15, 0x3, intr_data_ptr[PIRQ_D]);
147
148 /*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
149#define IO_LOCAL_INT(type, intr, apicid, pin) \
150 smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin));
151
152 IO_LOCAL_INT(mp_ExtINT, 0x0, MP_APIC_ALL, 0x0);
153 IO_LOCAL_INT(mp_NMI, 0x0, MP_APIC_ALL, 0x1);
154 /* There is no extension information... */
155
156 /* Compute the checksums */
157 return mptable_finalize(mc);
158}
159
160unsigned long write_smp_table(unsigned long addr)
161{
162 void *v;
163 v = smp_write_floating_table(addr, 0);
164 return (unsigned long)smp_write_config_table(v);
165}