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review.coreboot.org / coreboot / a50ced2eba20a007fa5b486c251c252ad09868cf / . / src / mainboard / biostar / am1ml / buildOpts.c
blob: 404935b19f9d4a0533f8b22a4e930c2bd6991271 [file] [log] [blame]
Sergej Ivanovd777c782015-04-03 18:10:27 +0300[diff] [blame]1/*
2 * This file is part of the coreboot project.
3 *
4 * Copyright (C) 2012 Advanced Micro Devices, Inc.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; version 2 of the License.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
Sergej Ivanovd777c782015-04-03 18:10:27 +0300[diff] [blame]14 */
15
16/**
17 * @file
18 *
19 * AMD User options selection for a Brazos platform solution system
20 *
21 * This file is placed in the user's platform directory and contains the
22 * build option selections desired for that platform.
23 *
24 * For Information about this file, see @ref platforminstall.
25 *
26 */
27
28#include <stdlib.h>
29#include "AGESA.h"
30#include "Filecode.h"
31#define FILECODE PLATFORM_SPECIFIC_OPTIONS_FILECODE
32
33#define INSTALL_FT3_SOCKET_SUPPORT TRUE
34#define INSTALL_FAMILY_16_MODEL_0x_SUPPORT TRUE
35
36#define INSTALL_G34_SOCKET_SUPPORT FALSE
37#define INSTALL_C32_SOCKET_SUPPORT FALSE
38#define INSTALL_S1G3_SOCKET_SUPPORT FALSE
39#define INSTALL_S1G4_SOCKET_SUPPORT FALSE
40#define INSTALL_ASB2_SOCKET_SUPPORT FALSE
41#define INSTALL_FS1_SOCKET_SUPPORT FALSE
42#define INSTALL_FM1_SOCKET_SUPPORT FALSE
43#define INSTALL_FP2_SOCKET_SUPPORT FALSE
44#define INSTALL_FT1_SOCKET_SUPPORT FALSE
45#define INSTALL_AM3_SOCKET_SUPPORT FALSE
46#define INSTALL_FM2_SOCKET_SUPPORT FALSE
47
48
49#ifdef BLDOPT_REMOVE_FT3_SOCKET_SUPPORT
50 #if BLDOPT_REMOVE_FT3_SOCKET_SUPPORT == TRUE
51 #undef INSTALL_FT3_SOCKET_SUPPORT
52 #define INSTALL_FT3_SOCKET_SUPPORT FALSE
53 #endif
54#endif
55
56//#define BLDOPT_REMOVE_UDIMMS_SUPPORT TRUE
57//#define BLDOPT_REMOVE_RDIMMS_SUPPORT TRUE
58//#define BLDOPT_REMOVE_LRDIMMS_SUPPORT TRUE
59#define BLDOPT_REMOVE_ECC_SUPPORT TRUE
60//#define BLDOPT_REMOVE_BANK_INTERLEAVE TRUE
61//#define BLDOPT_REMOVE_DCT_INTERLEAVE TRUE
62//#define BLDOPT_REMOVE_NODE_INTERLEAVE TRUE
63#define BLDOPT_REMOVE_PARALLEL_TRAINING TRUE
64#define BLDOPT_REMOVE_ONLINE_SPARE_SUPPORT TRUE
65//#define BLDOPT_REMOVE_MEM_RESTORE_SUPPORT TRUE
66#define BLDOPT_REMOVE_MULTISOCKET_SUPPORT TRUE
67//#define BLDOPT_REMOVE_ACPI_PSTATES FALSE
68#define BLDOPT_REMOVE_SRAT FALSE //TRUE
69#define BLDOPT_REMOVE_SLIT FALSE //TRUE
70#define BLDOPT_REMOVE_WHEA FALSE //TRUE
71#define BLDOPT_REMOVE_CRAT TRUE
72#define BLDOPT_REMOVE_CDIT TRUE
73#define BLDOPT_REMOVE_DMI TRUE
74//#define BLDOPT_REMOVE_EARLY_SAMPLES FALSE
75//#define BLDCFG_REMOVE_ACPI_PSTATES_PPC TRUE
76//#define BLDCFG_REMOVE_ACPI_PSTATES_PCT TRUE
77//#define BLDCFG_REMOVE_ACPI_PSTATES_PSD TRUE
78//#define BLDCFG_REMOVE_ACPI_PSTATES_PSS TRUE
79//#define BLDCFG_REMOVE_ACPI_PSTATES_XPSS TRUE
80
81//This element selects whether P-States should be forced to be independent,
82// as reported by the ACPI _PSD object. For single-link processors,
83// setting TRUE for OS to support this feature.
84
85//#define BLDCFG_FORCE_INDEPENDENT_PSD_OBJECT TRUE
86
87#define BLDCFG_PCI_MMIO_BASE CONFIG_MMCONF_BASE_ADDRESS
88#define BLDCFG_PCI_MMIO_SIZE CONFIG_MMCONF_BUS_NUMBER
89/* Build configuration values here.
90 */
91#define BLDCFG_VRM_CURRENT_LIMIT 15000
92#define BLDCFG_VRM_NB_CURRENT_LIMIT 13000
93#define BLDCFG_VRM_MAXIMUM_CURRENT_LIMIT 21000
94#define BLDCFG_VRM_SVI_OCP_LEVEL BLDCFG_VRM_MAXIMUM_CURRENT_LIMIT
95#define BLDCFG_VRM_NB_MAXIMUM_CURRENT_LIMIT 17000
96#define BLDCFG_VRM_NB_SVI_OCP_LEVEL BLDCFG_VRM_NB_MAXIMUM_CURRENT_LIMIT
97#define BLDCFG_VRM_LOW_POWER_THRESHOLD 0
98#define BLDCFG_VRM_NB_LOW_POWER_THRESHOLD 0
99#define BLDCFG_VRM_SLEW_RATE 10000
100#define BLDCFG_VRM_NB_SLEW_RATE BLDCFG_VRM_SLEW_RATE
101#define BLDCFG_VRM_HIGH_SPEED_ENABLE TRUE
102
103#define BLDCFG_PLAT_NUM_IO_APICS 3
104#define BLDCFG_GNB_IOAPIC_ADDRESS 0xFEC20000
105#define BLDCFG_CORE_LEVELING_MODE CORE_LEVEL_LOWEST
106#define BLDCFG_MEM_INIT_PSTATE 0
107#define BLDCFG_PLATFORM_CSTATE_IO_BASE_ADDRESS 0x1770 // Specifies the IO addresses trapped by the
108 // core for C-state entry requests. A value
109 // of 0 in this field specifies that the core
110 // does not trap any IO addresses for C-state entry.
111 // Values greater than 0xFFF8 results in undefined behavior.
112#define BLDCFG_PLATFORM_CSTATE_OPDATA 0x1770
113
114#define BLDCFG_AMD_PLATFORM_TYPE AMD_PLATFORM_MOBILE
115
116#define BLDCFG_MEMORY_BUS_FREQUENCY_LIMIT DDR1600_FREQUENCY
117#define BLDCFG_MEMORY_MODE_UNGANGED TRUE
118#define BLDCFG_MEMORY_QUAD_RANK_CAPABLE TRUE
119#define BLDCFG_MEMORY_QUADRANK_TYPE QUADRANK_UNBUFFERED
120#define BLDCFG_MEMORY_RDIMM_CAPABLE TRUE
121#define BLDCFG_MEMORY_UDIMM_CAPABLE TRUE
122#define BLDCFG_MEMORY_SODIMM_CAPABLE FALSE
123#define BLDCFG_MEMORY_ENABLE_BANK_INTERLEAVING FALSE
124#define BLDCFG_MEMORY_ENABLE_NODE_INTERLEAVING FALSE
125#define BLDCFG_MEMORY_CHANNEL_INTERLEAVING FALSE
126#define BLDCFG_MEMORY_POWER_DOWN TRUE
127#define BLDCFG_POWER_DOWN_MODE POWER_DOWN_BY_CHIP_SELECT
128#define BLDCFG_ONLINE_SPARE FALSE
129#define BLDCFG_BANK_SWIZZLE TRUE
130#define BLDCFG_TIMING_MODE_SELECT TIMING_MODE_AUTO
131#define BLDCFG_MEMORY_CLOCK_SELECT DDR1333_FREQUENCY
132#define BLDCFG_DQS_TRAINING_CONTROL TRUE
133#define BLDCFG_IGNORE_SPD_CHECKSUM TRUE
134#define BLDCFG_USE_BURST_MODE FALSE
135#define BLDCFG_MEMORY_ALL_CLOCKS_ON FALSE
136#define BLDCFG_ENABLE_ECC_FEATURE FALSE
137#define BLDCFG_ECC_REDIRECTION FALSE
138#define BLDCFG_SCRUB_DRAM_RATE 0
139#define BLDCFG_SCRUB_L2_RATE 0
140#define BLDCFG_SCRUB_L3_RATE 0
141#define BLDCFG_SCRUB_IC_RATE 0
142#define BLDCFG_SCRUB_DC_RATE 0
143#define BLDCFG_ECC_SYNC_FLOOD FALSE
144#define BLDCFG_ECC_SYMBOL_SIZE 4
145#define BLDCFG_HEAP_DRAM_ADDRESS 0xB0000ul
146#define BLDCFG_1GB_ALIGN FALSE
147#define BLDCFG_UMA_ALIGNMENT UMA_4MB_ALIGNED
148#define BLDCFG_UMA_ALLOCATION_MODE UMA_AUTO
149#define BLDCFG_PLATFORM_CSTATE_MODE CStateModeDisabled
150#define BLDCFG_IOMMU_SUPPORT FALSE
151#define OPTION_GFX_INIT_SVIEW FALSE
152//#define BLDCFG_PLATFORM_POWER_POLICY_MODE BatteryLife
153
154//#define BLDCFG_CFG_LCD_BACK_LIGHT_CONTROL OEM_LCD_BACK_LIGHT_CONTROL
155#define BLDCFG_CFG_ABM_SUPPORT TRUE
156
157#define BLDCFG_CFG_GNB_HD_AUDIO TRUE
158//#define BLDCFG_IGPU_SUBSYSTEM_ID OEM_IGPU_SSID
159//#define BLDCFG_IGPU_HD_AUDIO_SUBSYSTEM_ID OEM_IGPU_HD_AUDIO_SSID
160//#define BLFCFG_APU_PCIE_PORTS_SUBSYSTEM_ID OEM_APU_PCIE_PORTS_SSID
161
162#ifdef PCIEX_BASE_ADDRESS
163#define BLDCFG_PCI_MMIO_BASE PCIEX_BASE_ADDRESS
164#define BLDCFG_PCI_MMIO_SIZE (PCIEX_LENGTH >> 20)
165#endif
166
167#define BLDCFG_PROCESSOR_SCOPE_NAME0 'P'
168#define BLDCFG_PROCESSOR_SCOPE_NAME1 '0'
169#define BLDCFG_PCIE_TRAINING_ALGORITHM PcieTrainingDistributed
170
171/* Process the options...
172 * This file include MUST occur AFTER the user option selection settings
173 */
Sergej Ivanovd777c782015-04-03 18:10:27 +0300[diff] [blame]174/*
175 * Customized OEM build configurations for FCH component
176 */
177// #define BLDCFG_SMBUS0_BASE_ADDRESS 0xB00
178// #define BLDCFG_SMBUS1_BASE_ADDRESS 0xB20
179// #define BLDCFG_SIO_PME_BASE_ADDRESS 0xE00
180// #define BLDCFG_ACPI_PM1_EVT_BLOCK_ADDRESS 0x400
181// #define BLDCFG_ACPI_PM1_CNT_BLOCK_ADDRESS 0x404
182// #define BLDCFG_ACPI_PM_TMR_BLOCK_ADDRESS 0x408
183// #define BLDCFG_ACPI_CPU_CNT_BLOCK_ADDRESS 0x410
184// #define BLDCFG_ACPI_GPE0_BLOCK_ADDRESS 0x420
185// #define BLDCFG_SPI_BASE_ADDRESS 0xFEC10000
186// #define BLDCFG_WATCHDOG_TIMER_BASE 0xFEC00000
187// #define BLDCFG_HPET_BASE_ADDRESS 0xFED00000
188// #define BLDCFG_SMI_CMD_PORT_ADDRESS 0xB0
189// #define BLDCFG_ACPI_PMA_BLK_ADDRESS 0xFE00
190// #define BLDCFG_ROM_BASE_ADDRESS 0xFED61000
191// #define BLDCFG_AZALIA_SSID 0x780D1022
192// #define BLDCFG_SMBUS_SSID 0x780B1022
193// #define BLDCFG_IDE_SSID 0x780C1022
194// #define BLDCFG_SATA_AHCI_SSID 0x78011022
195// #define BLDCFG_SATA_IDE_SSID 0x78001022
196// #define BLDCFG_SATA_RAID5_SSID 0x78031022
197// #define BLDCFG_SATA_RAID_SSID 0x78021022
198// #define BLDCFG_EHCI_SSID 0x78081022
199// #define BLDCFG_OHCI_SSID 0x78071022
200// #define BLDCFG_LPC_SSID 0x780E1022
201// #define BLDCFG_SD_SSID 0x78061022
202// #define BLDCFG_XHCI_SSID 0x78121022
203// #define BLDCFG_FCH_PORT80_BEHIND_PCIB FALSE
204// #define BLDCFG_FCH_ENABLE_ACPI_SLEEP_TRAP TRUE
205// #define BLDCFG_FCH_GPP_LINK_CONFIG PortA4
206// #define BLDCFG_FCH_GPP_PORT0_PRESENT FALSE
207// #define BLDCFG_FCH_GPP_PORT1_PRESENT FALSE
208// #define BLDCFG_FCH_GPP_PORT2_PRESENT FALSE
209// #define BLDCFG_FCH_GPP_PORT3_PRESENT FALSE
210// #define BLDCFG_FCH_GPP_PORT0_HOTPLUG FALSE
211// #define BLDCFG_FCH_GPP_PORT1_HOTPLUG FALSE
212// #define BLDCFG_FCH_GPP_PORT2_HOTPLUG FALSE
213// #define BLDCFG_FCH_GPP_PORT3_HOTPLUG FALSE
214
215CONST AP_MTRR_SETTINGS ROMDATA KabiniApMtrrSettingsList[] =
216{
217 { AMD_AP_MTRR_FIX64k_00000, 0x1E1E1E1E1E1E1E1E },
218 { AMD_AP_MTRR_FIX16k_80000, 0x1E1E1E1E1E1E1E1E },
219 { AMD_AP_MTRR_FIX16k_A0000, 0x0000000000000000 },
220 { AMD_AP_MTRR_FIX4k_C0000, 0x0000000000000000 },
221 { AMD_AP_MTRR_FIX4k_C8000, 0x0000000000000000 },
222 { AMD_AP_MTRR_FIX4k_D0000, 0x0000000000000000 },
223 { AMD_AP_MTRR_FIX4k_D8000, 0x0000000000000000 },
224 { AMD_AP_MTRR_FIX4k_E0000, 0x1818181818181818 },
225 { AMD_AP_MTRR_FIX4k_E8000, 0x1818181818181818 },
226 { AMD_AP_MTRR_FIX4k_F0000, 0x1818181818181818 },
227 { AMD_AP_MTRR_FIX4k_F8000, 0x1818181818181818 },
228 { CPU_LIST_TERMINAL }
229};
230
231#define BLDCFG_AP_MTRR_SETTINGS_LIST &KabiniApMtrrSettingsList
232
233
234/* Include the files that instantiate the configuration definitions. */
235#include "cpuRegisters.h"
236#include "cpuFamRegisters.h"
237#include "cpuFamilyTranslation.h"
238#include "AdvancedApi.h"
239#include "heapManager.h"
240#include "CreateStruct.h"
241#include "cpuFeatures.h"
242#include "Table.h"
Sergej Ivanovd777c782015-04-03 18:10:27 +0300[diff] [blame]243#include "cpuEarlyInit.h"
244#include "cpuLateInit.h"
245#include "GnbInterface.h"
246
247 // This is the delivery package title, "BrazosPI"
248 // This string MUST be exactly 8 characters long
249#define AGESA_PACKAGE_STRING {'c', 'b', '_', 'A', 'g', 'e', 's', 'a'}
250
251 // This is the release version number of the AGESA component
252 // This string MUST be exactly 12 characters long
253#define AGESA_VERSION_STRING {'V', '0', '.', '0', '.', '0', '.', '1', ' ', ' ', ' ', ' '}
254
255/* MEMORY_BUS_SPEED */
256//#define DDR400_FREQUENCY 200 ///< DDR 400
257//#define DDR533_FREQUENCY 266 ///< DDR 533
258//#define DDR667_FREQUENCY 333 ///< DDR 667
259//#define DDR800_FREQUENCY 400 ///< DDR 800
260//#define DDR1066_FREQUENCY 533 ///< DDR 1066
261//#define DDR1333_FREQUENCY 667 ///< DDR 1333
262//#define DDR1600_FREQUENCY 800 ///< DDR 1600
263//#define DDR1866_FREQUENCY 933 ///< DDR 1866
264//#define DDR2100_FREQUENCY 1050 ///< DDR 2100
265//#define DDR2133_FREQUENCY 1066 ///< DDR 2133
266//#define DDR2400_FREQUENCY 1200 ///< DDR 2400
267//#define UNSUPPORTED_DDR_FREQUENCY 1201 ///< Highest limit of DDR frequency
268//
269///* QUANDRANK_TYPE*/
270//#define QUADRANK_REGISTERED 0 ///< Quadrank registered DIMM
271//#define QUADRANK_UNBUFFERED 1 ///< Quadrank unbuffered DIMM
272//
273///* USER_MEMORY_TIMING_MODE */
274//#define TIMING_MODE_AUTO 0 ///< Use best rate possible
275//#define TIMING_MODE_LIMITED 1 ///< Set user top limit
276//#define TIMING_MODE_SPECIFIC 2 ///< Set user specified speed
277//
278///* POWER_DOWN_MODE */
279//#define POWER_DOWN_BY_CHANNEL 0 ///< Channel power down mode
280//#define POWER_DOWN_BY_CHIP_SELECT 1 ///< Chip select power down mode
281
282/*
283 * Agesa optional capabilities selection.
284 * Uncomment and mark FALSE those features you wish to include in the build.
285 * Comment out or mark TRUE those features you want to REMOVE from the build.
286 */
287
288#define DFLT_SMBUS0_BASE_ADDRESS 0xB00
289#define DFLT_SMBUS1_BASE_ADDRESS 0xB20
290#define DFLT_SIO_PME_BASE_ADDRESS 0xE00
291#define DFLT_ACPI_PM1_EVT_BLOCK_ADDRESS 0x800
292#define DFLT_ACPI_PM1_CNT_BLOCK_ADDRESS 0x804
293#define DFLT_ACPI_PM_TMR_BLOCK_ADDRESS 0x808
294#define DFLT_ACPI_CPU_CNT_BLOCK_ADDRESS 0x810
295#define DFLT_ACPI_GPE0_BLOCK_ADDRESS 0x820
296#define DFLT_SPI_BASE_ADDRESS 0xFEC10000
297#define DFLT_WATCHDOG_TIMER_BASE_ADDRESS 0xFEC000F0
298#define DFLT_HPET_BASE_ADDRESS 0xFED00000
299#define DFLT_SMI_CMD_PORT 0xB0
300#define DFLT_ACPI_PMA_CNT_BLK_ADDRESS 0xFE00
301#define DFLT_GEC_BASE_ADDRESS 0xFED61000
302#define DFLT_AZALIA_SSID 0x780D1022
303#define DFLT_SMBUS_SSID 0x780B1022
304#define DFLT_IDE_SSID 0x780C1022
305#define DFLT_SATA_AHCI_SSID 0x78011022
306#define DFLT_SATA_IDE_SSID 0x78001022
307#define DFLT_SATA_RAID5_SSID 0x78031022
308#define DFLT_SATA_RAID_SSID 0x78021022
309#define DFLT_EHCI_SSID 0x78081022
310#define DFLT_OHCI_SSID 0x78071022
311#define DFLT_LPC_SSID 0x780E1022
312#define DFLT_SD_SSID 0x78061022
313#define DFLT_XHCI_SSID 0x78121022
314#define DFLT_FCH_PORT80_BEHIND_PCIB FALSE
315#define DFLT_FCH_ENABLE_ACPI_SLEEP_TRAP TRUE
316#define DFLT_FCH_GPP_LINK_CONFIG PortA4
317#define DFLT_FCH_GPP_PORT0_PRESENT FALSE
318#define DFLT_FCH_GPP_PORT1_PRESENT FALSE
319#define DFLT_FCH_GPP_PORT2_PRESENT FALSE
320#define DFLT_FCH_GPP_PORT3_PRESENT FALSE
321#define DFLT_FCH_GPP_PORT0_HOTPLUG FALSE
322#define DFLT_FCH_GPP_PORT1_HOTPLUG FALSE
323#define DFLT_FCH_GPP_PORT2_HOTPLUG FALSE
324#define DFLT_FCH_GPP_PORT3_HOTPLUG FALSE
325//#define BLDCFG_IR_PIN_CONTROL 0x33
326
327GPIO_CONTROL imba180_gpio[] = {
328 {183, Function1, GpioIn | GpioOutEnB | PullUpB},
329 {-1}
330};
331//#define BLDCFG_FCH_GPIO_CONTROL_LIST (&imba180_gpio[0])
332
333// The following definitions specify the default values for various parameters in which there are
334// no clearly defined defaults to be used in the common file. The values below are based on product
335// and BKDG content, please consult the AGESA Memory team for consultation.
336#define DFLT_SCRUB_DRAM_RATE (0)
337#define DFLT_SCRUB_L2_RATE (0)
338#define DFLT_SCRUB_L3_RATE (0)
339#define DFLT_SCRUB_IC_RATE (0)
340#define DFLT_SCRUB_DC_RATE (0)
341#define DFLT_MEMORY_QUADRANK_TYPE QUADRANK_UNBUFFERED
342#define DFLT_VRM_SLEW_RATE (5000)
343
344#include "PlatformInstall.h"