blob: 3750ba430573a370b4c46461c9219959d6abb45c [file] [log] [blame]
Fabian Kunkel171e2c92016-07-27 17:30:49 +02001/*
2 * This file is part of the coreboot project.
3 *
4 * Copyright (C) 2012 Advanced Micro Devices, Inc.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; version 2 of the License.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 */
15
16#include <northbridge/amd/pi/agesawrapper.h>
17
18#define FILECODE PROC_GNB_PCIE_FAMILY_0X15_F15PCIECOMPLEXCONFIG_FILECODE
19
20static const PCIe_PORT_DESCRIPTOR PortList [] = {
Fabian Kunkelcf051832016-07-27 17:42:39 +020021 /* Initialize Port descriptor (PCIe port, Lanes 2-3, PCI Device 2, Function 4) */
Fabian Kunkel171e2c92016-07-27 17:30:49 +020022 {
23 0,
Fabian Kunkelcf051832016-07-27 17:42:39 +020024 PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 2, 3),
Fabian Kunkel171e2c92016-07-27 17:30:49 +020025 PCIE_PORT_DATA_INITIALIZER_V2 (PortEnabled, ChannelTypeExt6db, 2, 4,
26 HotplugDisabled,
27 PcieGenMaxSupported,
28 PcieGenMaxSupported,
29 AspmDisabled, 0x02, 0)
30 },
31 /* Initialize Port descriptor (PCIe port, Lane 1, PCI Device 2, Function 3) */
32 {
33 0,
34 PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 1, 1),
35 PCIE_PORT_DATA_INITIALIZER_V2 (PortEnabled, ChannelTypeExt6db, 2, 3,
36 HotplugDisabled,
37 PcieGenMaxSupported,
38 PcieGenMaxSupported,
39 AspmDisabled, 0x03, 0)
40 },
41 /* Initialize Port descriptor (PCIe port, Lane 0, PCI Device 2, Function 2) */
42 {
43 0,
44 PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 0, 0),
45 PCIE_PORT_DATA_INITIALIZER_V2 (PortEnabled, ChannelTypeExt6db, 2, 2,
46 HotplugDisabled,
47 PcieGenMaxSupported,
48 PcieGenMaxSupported,
49 AspmDisabled, 0x04, 0)
50 },
51 /* Initialize Port descriptor (PCIe port, Lanes 4-7, PCI Device 2, Function 1) */
52 {
53 DESCRIPTOR_TERMINATE_LIST,
54 PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 4, 7),
55 PCIE_PORT_DATA_INITIALIZER_V2 (PortEnabled, ChannelTypeExt6db, 2, 1,
56 HotplugDisabled,
57 PcieGenMaxSupported,
58 PcieGenMaxSupported,
59 AspmDisabled, 0x05, 0)
60 }
61};
62
63static const PCIe_DDI_DESCRIPTOR DdiList [] = {
Fabian Kunkelcf051832016-07-27 17:42:39 +020064 /* eDP0 to LVDS connector */
Fabian Kunkel171e2c92016-07-27 17:30:49 +020065 {
66 0,
67 PCIE_ENGINE_DATA_INITIALIZER (PcieDdiEngine, 8, 11),
68 PCIE_DDI_DATA_INITIALIZER (ConnectorTypeDP, Aux1, Hdp1)
69 },
Fabian Kunkelcf051832016-07-27 17:42:39 +020070 /* DP1 to HDMI */
Fabian Kunkel171e2c92016-07-27 17:30:49 +020071 {
72 DESCRIPTOR_TERMINATE_LIST,
Fabian Kunkelcf051832016-07-27 17:42:39 +020073 PCIE_ENGINE_DATA_INITIALIZER (PcieDdiEngine, 12, 15),
74 PCIE_DDI_DATA_INITIALIZER (ConnectorTypeHDMI, Aux2, Hdp2)
Fabian Kunkel171e2c92016-07-27 17:30:49 +020075 },
76};
77
78static const PCIe_COMPLEX_DESCRIPTOR PcieComplex = {
79 .Flags = DESCRIPTOR_TERMINATE_LIST,
80 .SocketId = 0,
81 .PciePortList = PortList,
82 .DdiLinkList = DdiList
83};
84
85/*---------------------------------------------------------------------------------------*/
86/**
87 * OemCustomizeInitEarly
88 *
89 * Description:
90 * This stub function will call the host environment through the binary block
91 * interface (call-out port) to provide a user hook opportunity
92 *
93 * Parameters:
94 * @param[in] *InitEarly
95 *
96 * @retval VOID
97 *
98 **/
99/*---------------------------------------------------------------------------------------*/
100VOID
101OemCustomizeInitEarly (
102 IN OUT AMD_EARLY_PARAMS *InitEarly
103 )
104{
105 InitEarly->GnbConfig.PcieComplexList = &PcieComplex;
106}