WANG Siyuan | f77f734 | 2013-08-13 17:09:51 +0800 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2012 Advanced Micro Devices, Inc. |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or modify |
| 7 | * it under the terms of the GNU General Public License as published by |
| 8 | * the Free Software Foundation; version 2 of the License. |
| 9 | * |
| 10 | * This program is distributed in the hope that it will be useful, |
| 11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 13 | * GNU General Public License for more details. |
WANG Siyuan | f77f734 | 2013-08-13 17:09:51 +0800 | [diff] [blame] | 14 | */ |
| 15 | |
| 16 | #include <console/console.h> |
| 17 | #include <arch/smp/mpspec.h> |
| 18 | #include <device/pci.h> |
| 19 | #include <arch/io.h> |
Kyösti Mälkki | b426107 | 2014-07-22 10:24:20 +0300 | [diff] [blame] | 20 | #include <arch/ioapic.h> |
WANG Siyuan | f77f734 | 2013-08-13 17:09:51 +0800 | [diff] [blame] | 21 | #include <string.h> |
| 22 | #include <stdint.h> |
| 23 | #include <cpu/amd/amdfam15.h> |
| 24 | #include <arch/cpu.h> |
| 25 | #include <cpu/x86/lapic.h> |
Kyösti Mälkki | 11f3443 | 2016-05-26 11:21:02 +0300 | [diff] [blame] | 26 | #include "southbridge/amd/agesa/hudson/hudson.h" |
WANG Siyuan | f77f734 | 2013-08-13 17:09:51 +0800 | [diff] [blame] | 27 | |
WANG Siyuan | f77f734 | 2013-08-13 17:09:51 +0800 | [diff] [blame] | 28 | |
| 29 | u8 picr_data[0x54] = { |
| 30 | 0x03,0x04,0x05,0x07,0x0B,0x0A,0x1F,0x1F,0xFA,0xF1,0x00,0x00,0x1F,0x1F,0x1F,0x1F, |
| 31 | 0x1F,0x1F,0x1F,0x03,0x1F,0x1F,0x1F,0x1F,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00, |
| 32 | 0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, |
| 33 | 0x05,0x04,0x05,0x04,0x04,0x05,0x04,0x05,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, |
| 34 | 0x04,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, |
| 35 | 0x03,0x04,0x05,0x07 |
| 36 | }; |
| 37 | u8 intr_data[0x54] = { |
| 38 | 0x10,0x11,0x12,0x13,0x14,0x15,0x16,0x17,0x00,0x00,0x00,0x00,0x1F,0x1F,0x1F,0x1F, |
| 39 | 0x09,0x1F,0x1F,0x10,0x1F,0x10,0x1F,0x10,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00, |
| 40 | 0x05,0x1F,0x1F,0x1F,0x1F,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, |
| 41 | 0x12,0x11,0x12,0x11,0x12,0x11,0x12,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, |
| 42 | 0x11,0x13,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, |
| 43 | 0x10,0x11,0x12,0x13 |
| 44 | }; |
| 45 | |
| 46 | static void smp_add_mpc_entry(struct mp_config_table *mc, unsigned length) |
| 47 | { |
| 48 | mc->mpc_length += length; |
| 49 | mc->mpc_entry_count++; |
| 50 | } |
| 51 | |
| 52 | static void my_smp_write_bus(struct mp_config_table *mc, |
| 53 | unsigned char id, const char *bustype) |
| 54 | { |
| 55 | struct mpc_config_bus *mpc; |
| 56 | mpc = smp_next_mpc_entry(mc); |
| 57 | memset(mpc, '\0', sizeof(*mpc)); |
| 58 | mpc->mpc_type = MP_BUS; |
| 59 | mpc->mpc_busid = id; |
| 60 | memcpy(mpc->mpc_bustype, bustype, sizeof(mpc->mpc_bustype)); |
| 61 | smp_add_mpc_entry(mc, sizeof(*mpc)); |
| 62 | } |
| 63 | |
| 64 | static void *smp_write_config_table(void *v) |
| 65 | { |
| 66 | struct mp_config_table *mc; |
| 67 | int bus_isa; |
WANG Siyuan | f77f734 | 2013-08-13 17:09:51 +0800 | [diff] [blame] | 68 | u8 byte; |
| 69 | |
Kyösti Mälkki | b426107 | 2014-07-22 10:24:20 +0300 | [diff] [blame] | 70 | /* |
| 71 | * By the time this function gets called, the IOAPIC registers |
| 72 | * have been written so they can be read to get the correct |
| 73 | * APIC ID and Version |
| 74 | */ |
Kevin Paul Herbert | bde6d30 | 2014-12-24 18:43:20 -0800 | [diff] [blame] | 75 | u8 ioapic_id = (io_apic_read(VIO_APIC_VADDR, 0x00) >> 24); |
| 76 | u8 ioapic_ver = (io_apic_read(VIO_APIC_VADDR, 0x01) & 0xFF); |
Kyösti Mälkki | b426107 | 2014-07-22 10:24:20 +0300 | [diff] [blame] | 77 | |
WANG Siyuan | f77f734 | 2013-08-13 17:09:51 +0800 | [diff] [blame] | 78 | mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); |
| 79 | |
| 80 | mptable_init(mc, LOCAL_APIC_ADDR); |
| 81 | memcpy(mc->mpc_oem, "AMD ", 8); |
| 82 | |
| 83 | smp_write_processors(mc); |
| 84 | |
WANG Siyuan | f77f734 | 2013-08-13 17:09:51 +0800 | [diff] [blame] | 85 | //mptable_write_buses(mc, NULL, &bus_isa); |
| 86 | my_smp_write_bus(mc, 0, "PCI "); |
| 87 | my_smp_write_bus(mc, 1, "PCI "); |
| 88 | bus_isa = 0x02; |
| 89 | my_smp_write_bus(mc, bus_isa, "ISA "); |
| 90 | |
| 91 | /* I/O APICs: APIC ID Version State Address */ |
Kevin Paul Herbert | bde6d30 | 2014-12-24 18:43:20 -0800 | [diff] [blame] | 92 | smp_write_ioapic(mc, ioapic_id, ioapic_ver, VIO_APIC_VADDR); |
WANG Siyuan | f77f734 | 2013-08-13 17:09:51 +0800 | [diff] [blame] | 93 | |
Kevin Paul Herbert | bde6d30 | 2014-12-24 18:43:20 -0800 | [diff] [blame] | 94 | smp_write_ioapic(mc, ioapic_id+1, 0x21, (void *)0xFEC20000); |
WANG Siyuan | f77f734 | 2013-08-13 17:09:51 +0800 | [diff] [blame] | 95 | /* PIC IRQ routine */ |
| 96 | for (byte = 0x0; byte < sizeof(picr_data); byte ++) { |
| 97 | outb(byte, 0xC00); |
| 98 | outb(picr_data[byte], 0xC01); |
| 99 | } |
| 100 | |
| 101 | /* APIC IRQ routine */ |
| 102 | for (byte = 0x0; byte < sizeof(intr_data); byte ++) { |
| 103 | outb(byte | 0x80, 0xC00); |
| 104 | outb(intr_data[byte], 0xC01); |
| 105 | } |
| 106 | #if 0 |
| 107 | outb(0x0B, 0xCD6); |
| 108 | outb(0x02, 0xCD7); |
| 109 | |
| 110 | outb(0x50, 0xCD6); |
| 111 | outb(0x1F, 0xCD7); |
| 112 | |
| 113 | outb(0x48, 0xCD6); |
| 114 | outb(0xF2, 0xCD7); |
| 115 | |
| 116 | //outb(0xBE, 0xCD6); |
| 117 | //outb(0x52, 0xCD7); |
| 118 | |
| 119 | outb(0xED, 0xCD6); |
| 120 | outb(0x17, 0xCD7); |
| 121 | |
| 122 | *(volatile u8 *) (0xFED80D00 + 0x31) = 2; |
| 123 | *(volatile u8 *) (0xFED80D00 + 0x32) = 2; |
| 124 | *(volatile u8 *) (0xFED80D00 + 0x33) = 2; |
| 125 | *(volatile u8 *) (0xFED80D00 + 0x34) = 2; |
| 126 | |
| 127 | *(volatile u8 *) (0xFED80100 + 0x31) = 0xc8; |
| 128 | *(volatile u8 *) (0xFED80100 + 0x32) = 0xc8; |
| 129 | *(volatile u8 *) (0xFED80100 + 0x33) = 0xc8; |
| 130 | *(volatile u8 *) (0xFED80100 + 0x34) = 0xa0; |
| 131 | |
| 132 | *(volatile u8 *) (0xFED80D00 + 0x6c) = 1; |
| 133 | *(volatile u8 *) (0xFED80D00 + 0x6E) = 2; |
| 134 | *(volatile u8 *) (0xFED80D00 + 0x6f) = 2; |
| 135 | |
| 136 | *(volatile u8 *) (0xFED80100 + 0x6c) = 0xa0; |
| 137 | *(volatile u8 *) (0xFED80100 + 0x6E) = 0xa8; |
| 138 | *(volatile u8 *) (0xFED80100 + 0x6f) = 0xa0; |
| 139 | |
| 140 | *(volatile u8 *) (0xFED80D00 + 0xA6) = 2; |
| 141 | *(volatile u8 *) (0xFED80100 + 0xA6) = 0; |
| 142 | |
| 143 | *(volatile u8 *) (0xFED80100 + 0x40) = 0xC8; |
| 144 | #endif |
| 145 | /* I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ |
| 146 | #define IO_LOCAL_INT(type, intr, apicid, pin) \ |
| 147 | smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin)); |
Kyösti Mälkki | b426107 | 2014-07-22 10:24:20 +0300 | [diff] [blame] | 148 | mptable_add_isa_interrupts(mc, bus_isa, ioapic_id, 0); |
WANG Siyuan | f77f734 | 2013-08-13 17:09:51 +0800 | [diff] [blame] | 149 | |
| 150 | /* PCI interrupts are level triggered, and are |
| 151 | * associated with a specific bus/device/function tuple. |
| 152 | */ |
| 153 | #define PCI_INT(bus, dev, int_sign, pin) \ |
Elyes HAOUAS | 8da96e5 | 2016-09-22 21:20:54 +0200 | [diff] [blame] | 154 | smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(int_sign)), ioapic_id, (pin)) |
WANG Siyuan | f77f734 | 2013-08-13 17:09:51 +0800 | [diff] [blame] | 155 | |
| 156 | /* Internal VGA */ |
| 157 | PCI_INT(0x0, 0x01, 0x0, intr_data[0x02]); |
| 158 | PCI_INT(0x0, 0x01, 0x1, intr_data[0x03]); |
| 159 | |
| 160 | /* SMBUS */ |
| 161 | PCI_INT(0x0, 0x14, 0x0, 0x10); |
| 162 | |
| 163 | /* HD Audio */ |
| 164 | PCI_INT(0x0, 0x14, 0x0, intr_data[0x13]); |
| 165 | |
| 166 | /* USB */ |
| 167 | PCI_INT(0x0, 0x12, 0x0, intr_data[0x30]); |
| 168 | PCI_INT(0x0, 0x12, 0x1, intr_data[0x31]); |
| 169 | PCI_INT(0x0, 0x13, 0x0, intr_data[0x32]); |
| 170 | PCI_INT(0x0, 0x13, 0x1, intr_data[0x33]); |
| 171 | PCI_INT(0x0, 0x16, 0x0, intr_data[0x34]); |
| 172 | PCI_INT(0x0, 0x16, 0x1, intr_data[0x35]); |
| 173 | PCI_INT(0x0, 0x14, 0x2, intr_data[0x36]); |
| 174 | |
| 175 | /* sata */ |
| 176 | PCI_INT(0x0, 0x11, 0x0, intr_data[0x40]); |
| 177 | PCI_INT(0x0, 0x11, 0x0, intr_data[0x41]); |
| 178 | |
| 179 | /* on board NIC & Slot PCIE. */ |
| 180 | |
| 181 | /* PCI slots */ |
Kyösti Mälkki | cdfb462 | 2014-07-22 15:24:15 +0300 | [diff] [blame] | 182 | device_t dev = dev_find_slot(0, PCI_DEVFN(0x14, 4)); |
| 183 | if (dev && dev->enabled) { |
| 184 | u8 bus_pci = dev->link_list->secondary; |
| 185 | /* PCI_SLOT 0. */ |
| 186 | PCI_INT(bus_pci, 0x5, 0x0, 0x14); |
| 187 | PCI_INT(bus_pci, 0x5, 0x1, 0x15); |
| 188 | PCI_INT(bus_pci, 0x5, 0x2, 0x16); |
| 189 | PCI_INT(bus_pci, 0x5, 0x3, 0x17); |
WANG Siyuan | f77f734 | 2013-08-13 17:09:51 +0800 | [diff] [blame] | 190 | |
Kyösti Mälkki | cdfb462 | 2014-07-22 15:24:15 +0300 | [diff] [blame] | 191 | /* PCI_SLOT 1. */ |
| 192 | PCI_INT(bus_pci, 0x6, 0x0, 0x15); |
| 193 | PCI_INT(bus_pci, 0x6, 0x1, 0x16); |
| 194 | PCI_INT(bus_pci, 0x6, 0x2, 0x17); |
| 195 | PCI_INT(bus_pci, 0x6, 0x3, 0x14); |
WANG Siyuan | f77f734 | 2013-08-13 17:09:51 +0800 | [diff] [blame] | 196 | |
Kyösti Mälkki | cdfb462 | 2014-07-22 15:24:15 +0300 | [diff] [blame] | 197 | /* PCI_SLOT 2. */ |
| 198 | PCI_INT(bus_pci, 0x7, 0x0, 0x16); |
| 199 | PCI_INT(bus_pci, 0x7, 0x1, 0x17); |
| 200 | PCI_INT(bus_pci, 0x7, 0x2, 0x14); |
| 201 | PCI_INT(bus_pci, 0x7, 0x3, 0x15); |
| 202 | } |
WANG Siyuan | f77f734 | 2013-08-13 17:09:51 +0800 | [diff] [blame] | 203 | |
| 204 | /* PCIe Lan*/ |
| 205 | PCI_INT(0x0, 0x06, 0x0, 0x13); |
| 206 | |
| 207 | /* FCH PCIe PortA */ |
| 208 | PCI_INT(0x0, 0x15, 0x0, 0x10); |
| 209 | /* FCH PCIe PortB */ |
| 210 | PCI_INT(0x0, 0x15, 0x1, 0x11); |
| 211 | /* FCH PCIe PortC */ |
| 212 | PCI_INT(0x0, 0x15, 0x2, 0x12); |
| 213 | /* FCH PCIe PortD */ |
| 214 | PCI_INT(0x0, 0x15, 0x3, 0x13); |
| 215 | |
| 216 | /*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ |
| 217 | IO_LOCAL_INT(mp_ExtINT, 0, MP_APIC_ALL, 0x0); |
| 218 | IO_LOCAL_INT(mp_NMI, 0, MP_APIC_ALL, 0x1); |
| 219 | /* There is no extension information... */ |
| 220 | |
| 221 | /* Compute the checksums */ |
| 222 | return mptable_finalize(mc); |
| 223 | } |
| 224 | |
| 225 | unsigned long write_smp_table(unsigned long addr) |
| 226 | { |
| 227 | void *v; |
| 228 | v = smp_write_floating_table(addr, 0); |
| 229 | return (unsigned long)smp_write_config_table(v); |
| 230 | } |