WANG Siyuan | f77f734 | 2013-08-13 17:09:51 +0800 | [diff] [blame] | 1 | # |
| 2 | # This file is part of the coreboot project. |
| 3 | # |
| 4 | # Copyright (C) 2013 Advanced Micro Devices, Inc. |
| 5 | # |
| 6 | # This program is free software; you can redistribute it and/or modify |
| 7 | # it under the terms of the GNU General Public License as published by |
| 8 | # the Free Software Foundation; version 2 of the License. |
| 9 | # |
| 10 | # This program is distributed in the hope that it will be useful, |
| 11 | # but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 12 | # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 13 | # GNU General Public License for more details. |
| 14 | # |
WANG Siyuan | f77f734 | 2013-08-13 17:09:51 +0800 | [diff] [blame] | 15 | chip northbridge/amd/agesa/family16kb/root_complex |
| 16 | device cpu_cluster 0 on |
| 17 | chip cpu/amd/agesa/family16kb |
| 18 | device lapic 0 on end |
| 19 | end |
| 20 | end |
| 21 | |
| 22 | device domain 0 on |
| 23 | subsystemid 0x1022 0x1410 inherit |
| 24 | chip northbridge/amd/agesa/family16kb # CPU side of HT root complex |
| 25 | |
| 26 | chip northbridge/amd/agesa/family16kb # PCI side of HT root complex |
| 27 | device pci 0.0 on end # Root Complex |
| 28 | device pci 1.0 on end # Internal Graphics P2P bridge 0x9804 |
| 29 | device pci 1.1 on end # Internal Multimedia |
| 30 | device pci 2.0 on end # PCIe Host Bridge |
| 31 | device pci 2.1 on end # x4 PCIe slot |
| 32 | device pci 2.2 on end # mPCIe slot |
| 33 | device pci 2.3 on end # Realtek NIC |
| 34 | device pci 2.4 on end # Edge Connector |
| 35 | device pci 2.5 on end # Edge Connector |
| 36 | end #chip northbridge/amd/agesa/family16kb |
| 37 | |
| 38 | chip southbridge/amd/agesa/hudson # it is under NB/SB Link, but on the same pci bus |
| 39 | device pci 10.0 on end # XHCI HC0 |
| 40 | device pci 11.0 on end # SATA |
| 41 | device pci 12.0 on end # USB |
| 42 | device pci 12.2 on end # USB |
| 43 | device pci 13.0 on end # USB |
| 44 | device pci 13.2 on end # USB |
| 45 | device pci 14.0 on # SM |
| 46 | chip drivers/generic/generic #dimm 0-0-0 |
| 47 | device i2c 50 on end |
| 48 | end |
| 49 | chip drivers/generic/generic #dimm 0-0-1 |
| 50 | device i2c 51 on end |
| 51 | end |
| 52 | end # SM |
| 53 | device pci 14.2 on end # HDA 0x4383 |
Dave Frodin | 812d624 | 2013-12-26 08:24:16 -0700 | [diff] [blame] | 54 | device pci 14.3 on |
| 55 | chip superio/winbond/w83627uhg |
| 56 | device pnp 2e.0 off end # FDC |
| 57 | device pnp 2e.1 off end # LPT1 |
| 58 | device pnp 2e.2 on # COM1 |
| 59 | io 0x60 = 0x3f8 |
| 60 | irq 0x70 = 4 |
| 61 | end |
| 62 | device pnp 2e.3 on # COM2 |
| 63 | io 0x60 = 0x2f8 |
| 64 | irq 0x70 = 3 |
| 65 | end |
| 66 | device pnp 2e.5 on # KEYBRD |
| 67 | io 0x60 = 0x60 |
| 68 | io 0x62 = 0x64 |
| 69 | irq 0x70 = 1 |
| 70 | irq 0x72 = 12 |
| 71 | end |
| 72 | device pnp 2e.6 on # COM3 |
| 73 | io 0x60 = 0x3e8 |
| 74 | irq 0x70 = 4 |
| 75 | end |
| 76 | device pnp 2e.7 off end # GPIO |
| 77 | device pnp 2e.8 off end # WDT |
| 78 | device pnp 2e.9 off end # GPIO |
| 79 | device pnp 2e.a off end # ACPI |
| 80 | device pnp 2e.b off end # HWMON |
| 81 | device pnp 2e.c off end # PECI |
| 82 | device pnp 2e.d on # COM4 |
| 83 | io 0x60 = 0x2e8 |
| 84 | irq 0x70 = 3 |
| 85 | end |
| 86 | device pnp 2e.e on # COM5 |
| 87 | io 0x60 = 0x3e0 |
| 88 | irq 0x70 = 4 |
| 89 | end |
| 90 | device pnp 2e.f on # COM6 |
| 91 | io 0x60 = 0x2e0 |
| 92 | irq 0x70 = 3 |
| 93 | end |
| 94 | end # w83627uhg |
| 95 | end # LPC 0x439d |
WANG Siyuan | f77f734 | 2013-08-13 17:09:51 +0800 | [diff] [blame] | 96 | device pci 14.7 on end # SD |
Marshall Dawson | f5d9d14 | 2016-12-16 12:53:53 -0500 | [diff] [blame] | 97 | end #chip southbridge/amd/agesa/hudson |
WANG Siyuan | f77f734 | 2013-08-13 17:09:51 +0800 | [diff] [blame] | 98 | |
| 99 | device pci 18.0 on end |
| 100 | device pci 18.1 on end |
| 101 | device pci 18.2 on end |
| 102 | device pci 18.3 on end |
| 103 | device pci 18.4 on end |
| 104 | device pci 18.5 on end |
| 105 | register "spdAddrLookup" = " |
| 106 | { |
| 107 | { {0xA0, 0xA2}, {0x00, 0x00}, }, // socket 0 - Channel 0 & 1 - 8-bit SPD addresses |
| 108 | { {0x00, 0x00}, {0x00, 0x00}, }, // socket 1 - Channel 0 & 1 - 8-bit SPD addresses |
| 109 | }" |
| 110 | |
| 111 | end #chip northbridge/amd/agesa/family16kb # CPU side of HT root complex |
| 112 | end #domain |
| 113 | end #northbridge/amd/agesa/family16kb/root_complex |