| Andrey Korolyov | d83b0e9 | 2016-07-01 20:06:37 +0300 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2007 Advanced Micro Devices, Inc. |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or modify |
| 7 | * it under the terms of the GNU General Public License version 2 as |
| 8 | * published by the Free Software Foundation. |
| 9 | * |
| 10 | * This program is distributed in the hope that it will be useful, |
| 11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 13 | * GNU General Public License for more details. |
| 14 | */ |
| 15 | |
| 16 | #include <arch/pirq_routing.h> |
| 17 | #include <console/console.h> |
| 18 | #include <arch/io.h> |
| 19 | #include <arch/pirq_routing.h> |
| 20 | #include "southbridge/amd/cs5536/cs5536.h" |
| 21 | |
| 22 | /* Platform IRQs */ |
| 23 | #define PIRQA 11 |
| 24 | #define PIRQB 5 |
| 25 | #define PIRQC 10 |
| 26 | #define PIRQD 10 |
| 27 | |
| 28 | /* Map */ |
| 29 | #define M_PIRQA (1 << PIRQA) /* Bitmap of supported IRQs */ |
| 30 | #define M_PIRQB (1 << PIRQB) /* Bitmap of supported IRQs */ |
| 31 | #define M_PIRQC (1 << PIRQC) /* Bitmap of supported IRQs */ |
| 32 | #define M_PIRQD (1 << PIRQD) /* Bitmap of supported IRQs */ |
| 33 | |
| 34 | /* Link */ |
| 35 | #define L_PIRQA 1 /* Means Slot INTx# Connects To Chipset INTA# */ |
| 36 | #define L_PIRQB 2 /* Means Slot INTx# Connects To Chipset INTB# */ |
| 37 | #define L_PIRQC 3 /* Means Slot INTx# Connects To Chipset INTC# */ |
| 38 | #define L_PIRQD 4 /* Means Slot INTx# Connects To Chipset INTD# */ |
| 39 | |
| 40 | static const struct irq_routing_table intel_irq_routing_table = { |
| 41 | PIRQ_SIGNATURE, /* u32 signature */ |
| 42 | PIRQ_VERSION, /* u16 version */ |
| 43 | 32 + 16 * CONFIG_IRQ_SLOT_COUNT, /* there can be total CONFIG_IRQ_SLOT_COUNT devices on the bus */ |
| 44 | 0x00, /* Where the interrupt router lies (bus) */ |
| 45 | (0x0F << 3) | 0x0, /* Where the interrupt router lies (dev) */ |
| 46 | 0x00, /* IRQs devoted exclusively to PCI usage */ |
| 47 | 0x100B, /* Vendor */ |
| 48 | 0x002B, /* Device */ |
| 49 | 0, /* Miniport data */ |
| 50 | {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}, /* u8 rfu[11] */ |
| 51 | 0x00, /* u8 checksum , this has to set to some value that would give 0 after the sum of all bytes for this structure (including checksum) */ |
| 52 | { |
| 53 | /* If you change the number of entries, change the CONFIG_IRQ_SLOT_COUNT above! */ |
| 54 | /* bus, dev|fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */ |
| Elyes HAOUAS | 8ab989e | 2016-07-30 17:46:17 +0200 | [diff] [blame] | 55 | {0x00, (0x01 << 3) | 0x0, {{L_PIRQA, M_PIRQA}, {0x00, 0x00}, {0x00, 0x00}, {0x00, 0x00}}, 0x0, 0x0}, /* CPU */ |
| Andrey Korolyov | d83b0e9 | 2016-07-01 20:06:37 +0300 | [diff] [blame] | 56 | {0x00, (0x0F << 3) | 0x0, {{L_PIRQA, M_PIRQA}, {L_PIRQB, M_PIRQB}, {L_PIRQC, M_PIRQC}, {L_PIRQD, M_PIRQD}}, 0x0, 0x0}, /* chipset */ |
| 57 | {0x00, (0x0D << 3) | 0x0, {{L_PIRQB, M_PIRQB}, {0x00, 0x00}, {0x00, 0x00}, {0x00, 0x00}}, 0x0, 0x0}, /* ethernet */ |
| 58 | } |
| 59 | }; |
| 60 | |
| 61 | unsigned long write_pirq_routing_table(unsigned long addr) |
| 62 | { |
| 63 | return copy_pirq_routing_table(addr, &intel_irq_routing_table); |
| 64 | } |