| Chris Ching | b146931 | 2016-05-11 09:06:50 -0600 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2013 Google Inc. |
| 5 | * Copyright (C) 2014 Sage Electronics Engineering, LLC. |
| 6 | * |
| 7 | * This program is free software; you can redistribute it and/or modify |
| 8 | * it under the terms of the GNU General Public License as published by |
| 9 | * the Free Software Foundation; version 2 of the License. |
| 10 | * |
| 11 | * This program is distributed in the hope that it will be useful, |
| 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 14 | * GNU General Public License for more details. |
| 15 | */ |
| 16 | |
| 17 | #ifndef IRQROUTE_H |
| 18 | #define IRQROUTE_H |
| 19 | |
| 20 | #include <southbridge/intel/fsp_rangeley/irq.h> |
| 21 | #include <southbridge/intel/fsp_rangeley/pci_devs.h> |
| 22 | |
| 23 | /* |
| 24 | * IR01h PCIe INT(ABCD) - PIRQ ABCD |
| 25 | * IR02h PCIe INT(ABCD) - PIRQ ABCD |
| 26 | * IR03h PCIe INT(ABCD) - PIRQ ABCD |
| 27 | * IR04h PCIe INT(ABCD) - PIRQ ABCD |
| 28 | * IR0Bh IQIA INT(ABCD) - PIRQ EFGH |
| 29 | * IR0Eh RAS INT(A) - PIRQ A |
| 30 | * IR13h SMBUS1 INT(A) - PIRQ B |
| 31 | * IR15h GBE INT(A) - PIRQ CDEF |
| 32 | * IR1Dh EHCI INT(A) - PIRQ G |
| 33 | * IR13h SATA2.0 INT(A) - PIRQ H |
| 34 | * IR13h SATA3.0 INT(A) - PIRQ A |
| 35 | * IR1Fh LPC INT(ABCD) - PIRQ HGBC |
| 36 | */ |
| 37 | |
| 38 | /* Devices set as A, A, A, A evaluate as 0, and don't get set */ |
| 39 | #define PCI_DEV_PIRQ_ROUTES \ |
| 40 | PCI_DEV_PIRQ_ROUTE(PCIE_PORT1_DEV, A, B, C, D), \ |
| 41 | PCI_DEV_PIRQ_ROUTE(PCIE_PORT2_DEV, D, C, B, A), \ |
| 42 | PCI_DEV_PIRQ_ROUTE(PCIE_PORT3_DEV, E, F, G, H), \ |
| 43 | PCI_DEV_PIRQ_ROUTE(PCIE_PORT4_DEV, H, G, F, E), \ |
| 44 | PCI_DEV_PIRQ_ROUTE(IQAT_DEV, E, F, G, H), \ |
| 45 | PCI_DEV_PIRQ_ROUTE(HOST_BRIDGE_DEV, H, A, A, A), \ |
| 46 | PCI_DEV_PIRQ_ROUTE(RCEC_DEV, A, A, A, B), \ |
| 47 | PCI_DEV_PIRQ_ROUTE(SMBUS1_DEV, B, A, A, A), \ |
| 48 | PCI_DEV_PIRQ_ROUTE(GBE_DEV, C, D, E, F), \ |
| 49 | PCI_DEV_PIRQ_ROUTE(USB2_DEV, G, A, A, A), \ |
| 50 | PCI_DEV_PIRQ_ROUTE(SATA2_DEV, H, A, A, A), \ |
| 51 | PCI_DEV_PIRQ_ROUTE(SATA3_DEV, A, A, A, B), \ |
| 52 | PCI_DEV_PIRQ_ROUTE(PCU_DEV, H, G, B, C) |
| 53 | |
| 54 | /* |
| 55 | * Route each PIRQ[A-H] to a PIC IRQ[0-15] |
| 56 | * Reserved: 0, 1, 2, 8, 13 |
| 57 | * PS2 keyboard: 12 |
| 58 | * ACPI/SCI: 9 |
| 59 | * Floppy: 6 |
| 60 | */ |
| 61 | #define PIRQ_PIC_ROUTES \ |
| 62 | PIRQ_PIC(A, 10), \ |
| 63 | PIRQ_PIC(B, 11), \ |
| 64 | PIRQ_PIC(C, 10), \ |
| 65 | PIRQ_PIC(D, 11), \ |
| 66 | PIRQ_PIC(E, 14), \ |
| 67 | PIRQ_PIC(F, 15), \ |
| 68 | PIRQ_PIC(G, 14), \ |
| 69 | PIRQ_PIC(H, 15) |
| 70 | |
| 71 | #endif /* IRQROUTE_H */ |