| Chris Ching | b146931 | 2016-05-11 09:06:50 -0600 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2007-2009 coresystems GmbH |
| 5 | * Copyright (C) 2011 The ChromiumOS Authors. All rights reserved. |
| 6 | * |
| 7 | * This program is free software; you can redistribute it and/or modify |
| 8 | * it under the terms of the GNU General Public License as published by |
| 9 | * the Free Software Foundation; version 2 of the License. |
| 10 | * |
| 11 | * This program is distributed in the hope that it will be useful, |
| 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 14 | * GNU General Public License for more details. |
| 15 | */ |
| 16 | |
| 17 | DefinitionBlock( |
| 18 | "dsdt.aml", |
| 19 | "DSDT", |
| 20 | 0x02, // DSDT revision: ACPI v2.0 |
| 21 | "COREv4", // OEM id |
| 22 | "COREBOOT", // OEM table id |
| 23 | 0x20110725 // OEM revision |
| 24 | ) |
| 25 | { |
| 26 | // Include mainboard configuration |
| 27 | #include <acpi/mainboard.asl> |
| 28 | |
| 29 | // Include debug methods |
| 30 | #include <arch/x86/acpi/debug.asl> |
| 31 | |
| 32 | // Some generic macros |
| 33 | #include "acpi/platform.asl" |
| 34 | |
| 35 | // global NVS and variables |
| 36 | #include <southbridge/intel/fsp_rangeley/acpi/globalnvs.asl> |
| 37 | |
| 38 | #include "acpi/thermal.asl" |
| 39 | |
| 40 | #include <cpu/intel/fsp_model_406dx/acpi/cpu.asl> |
| 41 | |
| 42 | Scope (\_SB) { |
| 43 | Device (PCI0) |
| 44 | { |
| 45 | #include <northbridge/intel/fsp_rangeley/acpi/rangeley.asl> |
| 46 | #include <southbridge/intel/fsp_rangeley/acpi/soc.asl> |
| 47 | } |
| 48 | } |
| 49 | |
| 50 | /* Chipset specific sleep states */ |
| 51 | #include <southbridge/intel/fsp_rangeley/acpi/sleepstates.asl> |
| 52 | } |