| Chris Ching | b146931 | 2016-05-11 09:06:50 -0600 | [diff] [blame] | 1 | # |
| 2 | # This file is part of the coreboot project. |
| 3 | # |
| 4 | # Copyright (C) 2013 Sage Electronic Engineering, LLC. |
| 5 | # |
| 6 | # This program is free software; you can redistribute it and/or modify |
| 7 | # it under the terms of the GNU General Public License as published by |
| 8 | # the Free Software Foundation; version 2 of the License. |
| 9 | # |
| 10 | # This program is distributed in the hope that it will be useful, |
| 11 | # but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 12 | # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 13 | # GNU General Public License for more details. |
| 14 | # |
| 15 | chip northbridge/intel/fsp_rangeley |
| 16 | |
| 17 | device cpu_cluster 0 on |
| 18 | chip cpu/intel/socket_rPGA989 |
| 19 | device lapic 0 on end |
| 20 | end |
| 21 | chip cpu/intel/fsp_model_406dx |
| 22 | # Magic APIC ID to locate this chip |
| 23 | device lapic 0xACAC off end |
| 24 | |
| 25 | register "c1_battery" = "3" # ACPI(C1) = MWAIT(C3) |
| 26 | register "c2_battery" = "4" # ACPI(C2) = MWAIT(C6) |
| 27 | register "c3_battery" = "5" # ACPI(C3) = MWAIT(C7) |
| 28 | |
| 29 | register "c1_acpower" = "3" # ACPI(C1) = MWAIT(C3) |
| 30 | register "c2_acpower" = "4" # ACPI(C2) = MWAIT(C6) |
| 31 | register "c3_acpower" = "5" # ACPI(C3) = MWAIT(C7) |
| 32 | end |
| 33 | end |
| 34 | |
| 35 | device domain 0 on |
| 36 | device pci 00.0 on end # host bridge |
| 37 | device pci 1.0 on end # PCIe Port #1 |
| 38 | device pci 2.0 on end # PCIe Port #2 |
| 39 | device pci 3.0 on end # PCIe Port #3 |
| 40 | device pci 4.0 on end # PCIe Port #4 |
| 41 | chip southbridge/intel/fsp_rangeley # Rangeley SB |
| 42 | |
| 43 | register "ide_legacy_combined" = "0x0" |
| 44 | register "sata_ahci" = "0x1" |
| 45 | register "sata_port_map" = "0x0f" |
| 46 | |
| 47 | register "fadt_pm_profile" = "PM_DESKTOP" |
| 48 | register "fadt_boot_arch" = "ACPI_FADT_LEGACY_FREE" |
| 49 | |
| 50 | device pci 0b.0 on end # IQIA |
| 51 | device pci 0e.0 on end # RAS |
| 52 | device pci 13.0 on end # SMBus 1 |
| 53 | device pci 14.0 on end # GbE 0 |
| 54 | device pci 14.1 on end # GbE 1 |
| 55 | device pci 14.2 on end # GbE 2 |
| 56 | device pci 14.3 on end # GbE 3 |
| 57 | device pci 16.0 on end # USB EHCI |
| 58 | device pci 17.0 on end # SATA 2.0 |
| 59 | device pci 18.0 on end # SATA 3.0 |
| 60 | device pci 1f.0 on end # LPC bridge |
| 61 | device pci 1f.3 on end # SMBus 0 |
| 62 | end |
| 63 | end |
| 64 | end |