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review.coreboot.org / coreboot / a50ced2eba20a007fa5b486c251c252ad09868cf / . / Documentation / Intel / fsp1_1.html
blob: 1e1e88fcb31c83ce90066e4480deb68d751137cc [file] [log] [blame]
Lee Leahyc1e4f892016-01-07 11:24:24 -0800[diff] [blame]1<!DOCTYPE html>
2<html>
3 <head>
4 <title>FSP 1.1</title>
5 </head>
6 <body>
7
Lee Leahy2d96be62016-05-17 17:03:00 -0700[diff] [blame]8<h1>x86 FSP 1.1 Integration</h1>
Lee Leahyc1e4f892016-01-07 11:24:24 -0800[diff] [blame]9<p>
Lee Leahy2d96be62016-05-17 17:03:00 -0700[diff] [blame]10 Firmware Support Package (FSP) integration requires System-on-a-Chip (SoC)
Lee Leahyc1e4f892016-01-07 11:24:24 -0800[diff] [blame]11 and board support. The combined steps are listed
Lee Leahye8424cf2016-02-03 07:28:22 -0800[diff] [blame]12 <a target="_blank" href="development.html">here</a>.
Lee Leahyc1e4f892016-01-07 11:24:24 -0800[diff] [blame]13 The development steps for FSP are listed below:
14</p>
15<ol>
16 <li><a href="#RequiredFiles">Required Files</a></li>
Lee Leahy7e0078b2016-01-31 11:48:15 -0800[diff] [blame]17 <li>Add the <a href="#FspBinary">FSP Binary File</a> to the coreboot File System</li>
Lee Leahy66decf12016-02-04 11:21:33 -0800[diff] [blame]18 <li>Enable <a href="#corebootFspDebugging">coreboot/FSP Debugging</a></li>
Lee Leahyc1e4f892016-01-07 11:24:24 -0800[diff] [blame]19</ol>
20
21<p>
22 FSP Documentation:
23</p>
24<ul>
25 <li>Intel&reg; Firmware Support Package External Architecture Specification <a target="_blank" href="http://www.intel.com/content/dam/www/public/us/en/documents/technical-specifications/fsp-architecture-spec-v1-1.pdf">V1.1</a></li>
26</ul>
27
28<hr>
29<h1><a name="RequiredFiles">Required Files</a></h1>
Lee Leahye8424cf2016-02-03 07:28:22 -0800[diff] [blame]30<h2><a name="corebootRequiredFiles">coreboot Required Files</a></h2>
Lee Leahyc1e4f892016-01-07 11:24:24 -0800[diff] [blame]31<ol>
32 <li>Create the following directories if they do not already exist:
33 <ul>
34 <li>src/vendorcode/intel/fsp/fsp1_1/&lt;Chip Family&gt;</li>
35 <li>3rdparty/blobs/mainboard/&lt;Board Vendor&gt;/&lt;Board Name&gt;</li>
36 </ul>
37 </li>
38 <li>
39 The following files may need to be copied from the FSP build or release into the
40 directories above if they are not present or are out of date:
41 <ul>
42 <li>FspUpdVpd.h: src/vendorcode/intel/fsp/fsp1_1/&lt;Chip Family&gt;/FspUpdVpd.h</li>
43 <li>FSP.bin: 3rdparty/blobs/mainboard/&lt;Board Vendor&gt;/&lt;Board Name&gt;/fsp.bin</li>
44 </ul>
45 </li>
46</ol>
47
48
49<hr>
Lee Leahy7e0078b2016-01-31 11:48:15 -0800[diff] [blame]50<h1><a name="FspBinary">Add the FSP Binary File to coreboot File System</a></h1>
51<p>
52 Add the FSP binary to the coreboot flash image using the following command:
53</p>
54<pre><code>util/cbfstool/cbfstool build/coreboot.rom add -t fsp -n fsp.bin -b &lt;base address&gt; -f fsp.bin</code></pre>
55<p>
56 This command relocates the FSP binary to the 4K byte aligned location in CBFS so that the
57 FSP code for TempRamInit may be executed in place.
58</p>
59
60
61<hr>
Lee Leahy66decf12016-02-04 11:21:33 -0800[diff] [blame]62<h1><a name="corebootFspDebugging">Enable coreboot/FSP Debugging</a></h1>
63<p>
64 Set the following Kconfig values:
65</p>
66<ul>
67 <li>CONFIG_DISPLAY_FSP_ENTRY_POINTS - Display the FSP entry points in romstage</li>
68 <li>CONFIG_DISPLAY_HOBS - Display and verify the hand-off-blocks (HOBs) returned by MemoryInit</li>
69 <li>CONFIG_DISPLAY_VBT - Display Video BIOS Table (VBT) used for GOP</li>
70 <li>CONFIG_DISPLAY_UPD_DATA - Display the user specified product data passed to MemoryInit and SiliconInit</li>
71</ul>
72
73
74<hr>
Lee Leahy2d96be62016-05-17 17:03:00 -0700[diff] [blame]75<p>Modified: 17 May 2016</p>
Lee Leahyc1e4f892016-01-07 11:24:24 -0800[diff] [blame]76 </body>
Lee Leahy2d96be62016-05-17 17:03:00 -0700[diff] [blame]77</html>