Vadim Bendebury | 476f731 | 2014-04-08 18:45:46 -0700 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (c) 2012 - 2013 The Linux Foundation. All rights reserved. |
| 3 | */ |
| 4 | |
Vadim Bendebury | db3e2f0 | 2014-04-09 19:23:54 -0700 | [diff] [blame] | 5 | #include <delay.h> |
Alexandru Gagniuc | a4d784e | 2015-01-25 21:08:42 -0600 | [diff] [blame^] | 6 | #include <types.h> |
Vadim Bendebury | db3e2f0 | 2014-04-09 19:23:54 -0700 | [diff] [blame] | 7 | #include <clock.h> |
Vadim Bendebury | 476f731 | 2014-04-08 18:45:46 -0700 | [diff] [blame] | 8 | |
| 9 | /** |
| 10 | * uart_pll_vote_clk_enable - enables PLL8 |
| 11 | */ |
| 12 | void uart_pll_vote_clk_enable(unsigned int clk_dummy) |
| 13 | { |
| 14 | setbits_le32(BB_PLL_ENA_SC0_REG, BIT(8)); |
| 15 | |
| 16 | if (!clk_dummy) |
| 17 | while((readl(PLL_LOCK_DET_STATUS_REG) & BIT(8)) == 0); |
| 18 | } |
| 19 | |
| 20 | /** |
| 21 | * uart_set_rate_mnd - configures divider M and D values |
| 22 | * |
| 23 | * Sets the M, D parameters of the divider to generate the GSBI UART |
| 24 | * apps clock. |
| 25 | */ |
| 26 | static void uart_set_rate_mnd(unsigned int gsbi_port, unsigned int m, |
| 27 | unsigned int n) |
| 28 | { |
| 29 | /* Assert MND reset. */ |
| 30 | setbits_le32(GSBIn_UART_APPS_NS_REG(gsbi_port), BIT(7)); |
| 31 | /* Program M and D values. */ |
| 32 | writel(MD16(m, n), GSBIn_UART_APPS_MD_REG(gsbi_port)); |
| 33 | /* Deassert MND reset. */ |
| 34 | clrbits_le32(GSBIn_UART_APPS_NS_REG(gsbi_port), BIT(7)); |
| 35 | } |
| 36 | |
| 37 | /** |
| 38 | * uart_branch_clk_enable_reg - enables branch clock |
| 39 | * |
| 40 | * Enables branch clock for GSBI UART port. |
| 41 | */ |
| 42 | static void uart_branch_clk_enable_reg(unsigned int gsbi_port) |
| 43 | { |
| 44 | setbits_le32(GSBIn_UART_APPS_NS_REG(gsbi_port), BIT(9)); |
| 45 | } |
| 46 | |
| 47 | /** |
| 48 | * uart_local_clock_enable - configures N value and enables root clocks |
| 49 | * |
| 50 | * Sets the N parameter of the divider and enables root clock and |
| 51 | * branch clocks for GSBI UART port. |
| 52 | */ |
| 53 | static void uart_local_clock_enable(unsigned int gsbi_port, unsigned int n, |
| 54 | unsigned int m) |
| 55 | { |
| 56 | unsigned int reg_val, uart_ns_val; |
| 57 | void *const reg = (void *)GSBIn_UART_APPS_NS_REG(gsbi_port); |
| 58 | |
| 59 | /* |
| 60 | * Program the NS register, if applicable. NS registers are not |
| 61 | * set in the set_rate path because power can be saved by deferring |
| 62 | * the selection of a clocked source until the clock is enabled. |
| 63 | */ |
| 64 | reg_val = readl(reg); // REG(0x29D4+(0x20*((n)-1))) |
| 65 | reg_val &= ~(Uart_clk_ns_mask); |
| 66 | uart_ns_val = NS(BIT_POS_31,BIT_POS_16,n,m, 5, 4, 3, 1, 2, 0,3); |
| 67 | reg_val |= (uart_ns_val & Uart_clk_ns_mask); |
| 68 | writel(reg_val,reg); |
| 69 | |
| 70 | /* enable MNCNTR_EN */ |
| 71 | reg_val = readl(reg); |
| 72 | reg_val |= BIT(8); |
| 73 | writel(reg_val, reg); |
| 74 | |
| 75 | /* set source to PLL8 running @384MHz */ |
| 76 | reg_val = readl(reg); |
| 77 | reg_val |= 0x3; |
| 78 | writel(reg_val, reg); |
| 79 | |
| 80 | /* Enable root. */ |
| 81 | reg_val |= Uart_en_mask; |
| 82 | writel(reg_val, reg); |
| 83 | uart_branch_clk_enable_reg(gsbi_port); |
| 84 | } |
| 85 | |
| 86 | /** |
| 87 | * uart_set_gsbi_clk - enables HCLK for UART GSBI port |
| 88 | */ |
| 89 | static void uart_set_gsbi_clk(unsigned int gsbi_port) |
| 90 | { |
| 91 | setbits_le32(GSBIn_HCLK_CTL_REG(gsbi_port), BIT(4)); |
| 92 | } |
| 93 | |
| 94 | /** |
| 95 | * uart_clock_config - configures UART clocks |
| 96 | * |
| 97 | * Configures GSBI UART dividers, enable root and branch clocks. |
| 98 | */ |
| 99 | void uart_clock_config(unsigned int gsbi_port, unsigned int m, |
| 100 | unsigned int n, unsigned int d, unsigned int clk_dummy) |
| 101 | { |
| 102 | uart_set_rate_mnd(gsbi_port, m, d); |
| 103 | uart_pll_vote_clk_enable(clk_dummy); |
| 104 | uart_local_clock_enable(gsbi_port, n, m); |
| 105 | uart_set_gsbi_clk(gsbi_port); |
| 106 | } |
| 107 | |
| 108 | /** |
| 109 | * nand_clock_config - configure NAND controller clocks |
| 110 | * |
| 111 | * Enable clocks to EBI2. Must be invoked before touching EBI2 |
| 112 | * registers. |
| 113 | */ |
| 114 | void nand_clock_config(void) |
| 115 | { |
| 116 | writel(CLK_BRANCH_ENA(1) | ALWAYS_ON_CLK_BRANCH_ENA(1), |
| 117 | EBI2_CLK_CTL_REG); |
| 118 | |
| 119 | /* Wait for clock to stabilize. */ |
| 120 | udelay(10); |
| 121 | } |
Julius Werner | 028cba9 | 2014-05-30 18:01:44 -0700 | [diff] [blame] | 122 | |
| 123 | /** |
| 124 | * usb_clock_config - configure USB controller clocks and reset the controller |
| 125 | */ |
| 126 | void usb_clock_config(void) |
| 127 | { |
| 128 | /* Magic clock initialization numbers, nobody knows how they work... */ |
| 129 | write32(0x10, USB30_MASTER_CLK_CTL_REG); |
| 130 | write32(0x10, USB30_1_MASTER_CLK_CTL_REG); |
| 131 | write32(0x500DF, USB30_MASTER_CLK_MD); |
| 132 | write32(0xE40942, USB30_MASTER_CLK_NS); |
| 133 | write32(0x100D7, USB30_MOC_UTMI_CLK_MD); |
| 134 | write32(0xD80942, USB30_MOC_UTMI_CLK_NS); |
| 135 | write32(0x10, USB30_MOC_UTMI_CLK_CTL); |
| 136 | write32(0x10, USB30_1_MOC_UTMI_CLK_CTL); |
| 137 | |
| 138 | write32(1 << 5 | /* assert port2 HS PHY async reset */ |
| 139 | 1 << 4 | /* assert master async reset */ |
| 140 | 1 << 3 | /* assert sleep async reset */ |
| 141 | 1 << 2 | /* assert MOC UTMI async reset */ |
| 142 | 1 << 1 | /* assert power-on async reset */ |
| 143 | 1 << 0 | /* assert PHY async reset */ |
| 144 | 0, USB30_RESET); |
| 145 | udelay(5); |
| 146 | write32(0, USB30_RESET); /* deassert all USB resets again */ |
| 147 | } |