Angel Pons | ae59387 | 2020-04-04 18:50:57 +0200 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
Marshall Dawson | 4ee83b2 | 2019-05-03 11:44:22 -0600 | [diff] [blame] | 2 | |
Felix Held | 14e3432 | 2020-11-14 00:30:21 +0100 | [diff] [blame] | 3 | #ifndef AMD_BLOCK_ACPI_H |
| 4 | #define AMD_BLOCK_ACPI_H |
Marshall Dawson | 4ee83b2 | 2019-05-03 11:44:22 -0600 | [diff] [blame] | 5 | |
Raul E Rangel | 0f3bc81 | 2021-02-10 16:36:33 -0700 | [diff] [blame] | 6 | #include <acpi/acpi.h> |
Felix Held | dea4e0f | 2021-09-22 20:05:53 +0200 | [diff] [blame] | 7 | #include <amdblocks/gpio.h> |
Raul E Rangel | 0f3bc81 | 2021-02-10 16:36:33 -0700 | [diff] [blame] | 8 | #include <types.h> |
Marshall Dawson | 4ee83b2 | 2019-05-03 11:44:22 -0600 | [diff] [blame] | 9 | |
| 10 | /* ACPI MMIO registers 0xfed80800 */ |
Raul E Rangel | 12c6a58 | 2021-02-10 16:45:49 -0700 | [diff] [blame] | 11 | #define MMIO_ACPI_PM1_EVT_BLK 0x00 |
| 12 | #define MMIO_ACPI_PM1_STS 0x00 |
| 13 | #define MMIO_ACPI_PM1_EN 0x02 |
Marshall Dawson | 4ee83b2 | 2019-05-03 11:44:22 -0600 | [diff] [blame] | 14 | #define MMIO_ACPI_PM1_CNT_BLK 0x04 |
Felix Held | 30c1bb6 | 2021-11-22 20:29:04 +0100 | [diff] [blame] | 15 | /* sleep types defined in include/acpi/acpi.h */ |
Marshall Dawson | 4ee83b2 | 2019-05-03 11:44:22 -0600 | [diff] [blame] | 16 | #define ACPI_PM1_CNT_SCIEN BIT(0) |
| 17 | #define MMIO_ACPI_PM_TMR_BLK 0x08 |
Raul E Rangel | 12c6a58 | 2021-02-10 16:45:49 -0700 | [diff] [blame] | 18 | #define MMIO_ACPI_GPE0_BLK 0x14 |
| 19 | #define MMIO_ACPI_GPE0_STS 0x14 |
| 20 | #define MMIO_ACPI_GPE0_EN 0x18 |
Marshall Dawson | 4ee83b2 | 2019-05-03 11:44:22 -0600 | [diff] [blame] | 21 | |
Aaron Durbin | 746e598 | 2020-08-14 14:48:45 -0600 | [diff] [blame] | 22 | /* Structure to maintain standard ACPI register state for reporting purposes. */ |
| 23 | struct acpi_pm_gpe_state { |
| 24 | uint16_t pm1_sts; |
| 25 | uint16_t pm1_en; |
| 26 | uint32_t gpe0_sts; |
| 27 | uint32_t gpe0_en; |
| 28 | uint16_t previous_sx_state; |
| 29 | uint16_t aligning_field; |
| 30 | }; |
| 31 | |
| 32 | /* Fill object with the ACPI PM and GPE state. */ |
| 33 | void acpi_fill_pm_gpe_state(struct acpi_pm_gpe_state *state); |
| 34 | /* Save events to eventlog log and also print information on console. */ |
Kyösti Mälkki | b0db813 | 2021-01-21 16:34:43 +0200 | [diff] [blame] | 35 | void acpi_pm_gpe_add_events_print_events(void); |
Aaron Durbin | 746e598 | 2020-08-14 14:48:45 -0600 | [diff] [blame] | 36 | /* Clear PM and GPE status registers. */ |
| 37 | void acpi_clear_pm_gpe_status(void); |
| 38 | |
Marshall Dawson | 4ee83b2 | 2019-05-03 11:44:22 -0600 | [diff] [blame] | 39 | /* |
| 40 | * If a system reset is about to be requested, modify the PM1 register so it |
| 41 | * will never be misinterpreted as an S3 resume. |
| 42 | */ |
| 43 | void set_pm1cnt_s5(void); |
| 44 | void acpi_enable_sci(void); |
| 45 | void acpi_disable_sci(void); |
| 46 | |
Kyösti Mälkki | b0db813 | 2021-01-21 16:34:43 +0200 | [diff] [blame] | 47 | struct chipset_power_state { |
| 48 | struct acpi_pm_gpe_state gpe_state; |
| 49 | struct gpio_wake_state gpio_state; |
| 50 | }; |
| 51 | |
Raul E Rangel | 0f3bc81 | 2021-02-10 16:36:33 -0700 | [diff] [blame] | 52 | unsigned long southbridge_write_acpi_tables(const struct device *device, unsigned long current, |
| 53 | struct acpi_rsdp *rsdp); |
| 54 | |
Felix Held | 245adca | 2021-05-04 20:01:46 +0200 | [diff] [blame] | 55 | uintptr_t add_agesa_fsp_acpi_table(guid_t guid, const char *name, acpi_rsdp_t *rsdp, |
| 56 | uintptr_t current); |
| 57 | |
Karthikeyan Ramasubramanian | 589ac69 | 2021-07-15 14:58:23 -0600 | [diff] [blame] | 58 | void acpi_log_events(const struct chipset_power_state *ps); |
Felix Held | a4a2a4f | 2024-01-25 18:53:54 +0100 | [diff] [blame^] | 59 | unsigned long acpi_add_ivrs_table(unsigned long current, acpi_rsdp_t *rsdp); |
Karthikeyan Ramasubramanian | 589ac69 | 2021-07-15 14:58:23 -0600 | [diff] [blame] | 60 | |
Felix Held | 14e3432 | 2020-11-14 00:30:21 +0100 | [diff] [blame] | 61 | #endif /* AMD_BLOCK_ACPI_H */ |