| Patrick Georgi | ac95903 | 2020-05-05 22:49:26 +0200 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-or-later */ |
| Uwe Hermann | 26f0abd | 2007-10-31 00:00:57 +0000 | [diff] [blame] | 2 | |
| Kyösti Mälkki | bdaec07 | 2019-03-02 23:18:29 +0200 | [diff] [blame] | 3 | #include <arch/io.h> |
| Edward O'Callaghan | 77757c2 | 2015-01-04 21:33:39 +1100 | [diff] [blame] | 4 | #include <southbridge/intel/i82371eb/i82371eb.h> |
| 5 | #include <northbridge/intel/i440bx/raminit.h> |
| Uwe Hermann | 26f0abd | 2007-10-31 00:00:57 +0000 | [diff] [blame] | 6 | |
| Uwe Hermann | 0865b4d | 2010-09-19 21:12:05 +0000 | [diff] [blame] | 7 | /* |
| 8 | * ASUS P3B-F specific SPD enable magic. |
| 9 | * |
| 10 | * Setting the byte at offset 0x37 in the PM I/O space to 0x6f will make the |
| 11 | * board DIMMs accessible at SMBus/SPD offsets 0x50-0x53. Per default the SPD |
| 12 | * offsets 0x50-0x53 are _not_ readable (all SPD reads will return 0xff) which |
| 13 | * will make RAM init fail. |
| 14 | * |
| 15 | * Tested values for PM I/O offset 0x37: |
| 16 | * 0x67: 11 00 111: Only SMBus/I2C offsets 0x48/0x49/0x2d accessible |
| 17 | * 0x6f: 11 01 111: Only SMBus/I2C offsets 0x50-0x53 (SPD) accessible |
| 18 | * 0x77: 11 10 111: Only SMBus/I2C offset 0x69 accessible |
| 19 | * |
| 20 | * PM I/O space offset 0x37 is GPOREG[31:24], i.e. it controls the GPIOs |
| 21 | * 24-30 of the PIIX4E (bit 31 is reserved). Thus, GPIOs 27 and 28 |
| 22 | * control which SMBus/I2C offsets can be accessed. |
| 23 | */ |
| Kyösti Mälkki | 93e08c7 | 2020-01-07 15:17:48 +0200 | [diff] [blame] | 24 | void enable_spd(void) |
| Uwe Hermann | 0865b4d | 2010-09-19 21:12:05 +0000 | [diff] [blame] | 25 | { |
| 26 | outb(0x6f, PM_IO_BASE + 0x37); |
| 27 | } |