blob: fa765aa8362964d59623909573dcbb19be079e9d [file] [log] [blame]
Aaron Lwefcb2a312008-05-19 12:17:43 +00001/*
2 * This file is part of the coreboot project.
3 *
4 * Copyright (C) 2008 VIA Technologies, Inc.
5 * (Written by Aaron Lwe <aaron.lwe@gmail.com> for VIA)
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
20 */
21
22#include <arch/pirq_routing.h>
23
Stefan Reinauera47bd912012-11-15 15:15:15 -080024static const struct irq_routing_table intel_irq_routing_table = {
Aaron Lwefcb2a312008-05-19 12:17:43 +000025 PIRQ_SIGNATURE,
26 PIRQ_VERSION,
Stefan Reinauer08670622009-06-30 15:17:49 +000027 32 + 16 * CONFIG_IRQ_SLOT_COUNT,/* Max. number of devices on the bus */
Aaron Lwefcb2a312008-05-19 12:17:43 +000028 0x00, /* Interrupt router bus */
29 (0x11 << 3) | 0x0, /* Interrupt router device */
Ronald G. Minnichd4ef0542008-11-03 04:08:35 +000030 0xc20, /* IRQs devoted exclusively to PCI usage */
Aaron Lwefcb2a312008-05-19 12:17:43 +000031 0x1106, /* Vendor */
32 0x596, /* Device */
Uwe Hermann8fa90ec2010-09-21 21:16:27 +000033 0, /* Miniport data */
Aaron Lwefcb2a312008-05-19 12:17:43 +000034 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* u8 rfu[11] */
Ronald G. Minnichd4ef0542008-11-03 04:08:35 +000035 0x66, /* Checksum */
Aaron Lwefcb2a312008-05-19 12:17:43 +000036 {
37 /* bus, dev|fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */
Ronald G. Minnichd4ef0542008-11-03 04:08:35 +000038 {0x00,(0x14<<3)|0x0, {{0x02, 0xdeb8}, {0x03, 0xdeb8}, {0x05, 0xdeb8}, {0x01, 0x0deb8}}, 0x1, 0x0},
39 {0x00,(0x0d<<3)|0x0, {{0x02, 0xdeb8}, {0x03, 0xdeb8}, {0x05, 0xdeb8}, {0x01, 0x0deb8}}, 0x2, 0x0},
40 {0x00,(0x0e<<3)|0x0, {{0x03, 0xdeb8}, {0x05, 0xdeb8}, {0x01, 0xdeb8}, {0x02, 0x0deb8}}, 0x3, 0x0},
41 {0x00,(0x13<<3)|0x0, {{0x01, 0xdeb8}, {0x02, 0xdeb8}, {0x03, 0xdeb8}, {0x05, 0x0deb8}}, 0x4, 0x0},
42 {0x00,(0x11<<3)|0x0, {{0x00, 0xdeb8}, {0x00, 0xdeb8}, {0x03, 0xdeb8}, {0x05, 0x0deb8}}, 0x0, 0x0},
43 {0x00,(0x0f<<3)|0x0, {{0x01, 0xdeb8}, {0x02, 0xdeb8}, {0x03, 0xdeb8}, {0x05, 0x0deb8}}, 0x0, 0x0},
44 {0x00,(0x01<<3)|0x0, {{0x01, 0xdeb8}, {0x02, 0xdeb8}, {0x03, 0xdeb8}, {0x05, 0x0deb8}}, 0x0, 0x0},
45 {0x00,(0x10<<3)|0x0, {{0x01, 0xdeb8}, {0x02, 0xdeb8}, {0x03, 0xdeb8}, {0x05, 0x0deb8}}, 0x0, 0x0},
46 {0x00,(0x12<<3)|0x0, {{0x01, 0xdeb8}, {0x00, 0xdeb8}, {0x00, 0xdeb8}, {0x00, 0x0deb8}}, 0x0, 0x0},
Aaron Lwefcb2a312008-05-19 12:17:43 +000047 }
48};
49
50unsigned long write_pirq_routing_table(unsigned long addr)
51{
Stefan Reinauera47bd912012-11-15 15:15:15 -080052 return copy_pirq_routing_table(addr, &intel_irq_routing_table);
Aaron Lwefcb2a312008-05-19 12:17:43 +000053}