Anton Kochkov | 7c634ae | 2011-06-20 23:14:22 +0400 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of msrtool. |
| 3 | * |
| 4 | * Copyright (C) 2011 Anton Kochkov <anton.kochkov@gmail.com> |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or modify |
| 7 | * it under the terms of the GNU General Public License version 2 as |
| 8 | * published by the Free Software Foundation. |
| 9 | * |
| 10 | * This program is distributed in the hope that it will be useful, |
| 11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 13 | * GNU General Public License for more details. |
| 14 | * |
| 15 | * You should have received a copy of the GNU General Public License |
| 16 | * along with this program; if not, write to the Free Software |
Paul Menzel | a46a712 | 2013-02-23 18:37:27 +0100 | [diff] [blame^] | 17 | * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA |
Anton Kochkov | 7c634ae | 2011-06-20 23:14:22 +0400 | [diff] [blame] | 18 | */ |
| 19 | |
| 20 | #include "msrtool.h" |
| 21 | |
Anton Kochkov | 59b36f1 | 2012-07-21 07:29:48 +0400 | [diff] [blame] | 22 | int intel_pentium3_probe(const struct targetdef *target, const struct cpuid_t *id) { |
Anton Kochkov | ffbbecc | 2012-07-04 07:31:37 +0400 | [diff] [blame] | 23 | return ((0x6 == id->family) && ( |
| 24 | (0xa == id->model) || |
| 25 | (0xb == id->model) |
| 26 | )); |
Anton Kochkov | 7c634ae | 2011-06-20 23:14:22 +0400 | [diff] [blame] | 27 | } |
| 28 | |
| 29 | const struct msrdef intel_pentium3_msrs[] = { |
| 30 | {0x10, MSRTYPE_RDWR, MSR2(0,0), "IA32_TIME_STAMP_COUNTER", "", { |
| 31 | { BITS_EOT } |
| 32 | }}, |
| 33 | {0x17, MSRTYPE_RDWR, MSR2(0,0), "IA32_PLATFORM_ID", "", { |
| 34 | { BITS_EOT } |
| 35 | }}, |
| 36 | {0x1b, MSRTYPE_RDWR, MSR2(0,0), "IA32_APIC_BASE", "", { |
| 37 | { BITS_EOT } |
| 38 | }}, |
| 39 | {0x2a, MSRTYPE_RDWR, MSR2(0,0), "EBL_CR_POWERON", "", { |
| 40 | { BITS_EOT } |
| 41 | }}, |
| 42 | {0x33, MSRTYPE_RDWR, MSR2(0,0), "TEST_CTL", "", { |
| 43 | { BITS_EOT } |
| 44 | }}, |
| 45 | {0x3f, MSRTYPE_RDWR, MSR2(0,0), "THERM_DIODE_OFFSET", "", { |
| 46 | { BITS_EOT } |
| 47 | }}, |
| 48 | {0x8b, MSRTYPE_RDWR, MSR2(0,0), "IA32_BIOS_SIGN_ID", "", { |
| 49 | { BITS_EOT } |
| 50 | }}, |
| 51 | {0xc1, MSRTYPE_RDWR, MSR2(0,0), "PERFCTR0", "", { |
| 52 | { BITS_EOT } |
| 53 | }}, |
| 54 | {0xc2, MSRTYPE_RDWR, MSR2(0,0), "PERFCTR1", "", { |
| 55 | { BITS_EOT } |
| 56 | }}, |
| 57 | {0x11e, MSRTYPE_RDWR, MSR2(0,0), "BBL_CR_CTL3", "", { |
| 58 | { BITS_EOT } |
| 59 | }}, |
| 60 | {0x179, MSRTYPE_RDWR, MSR2(0,0), "IA32_MCG_CAP", "", { |
| 61 | { BITS_EOT } |
| 62 | }}, |
| 63 | {0x17a, MSRTYPE_RDWR, MSR2(0,0), "IA32_MCG_STATUS", "", { |
| 64 | { BITS_EOT } |
| 65 | }}, |
| 66 | {0x198, MSRTYPE_RDWR, MSR2(0,0), "IA32_PERF_STATUS", "", { |
| 67 | { BITS_EOT } |
| 68 | }}, |
| 69 | {0x199, MSRTYPE_RDWR, MSR2(0,0), "IA32_PERF_CONTROL", "", { |
| 70 | { BITS_EOT } |
| 71 | }}, |
| 72 | {0x19a, MSRTYPE_RDWR, MSR2(0,0), "IA32_CLOCK_MODULATION", "", { |
| 73 | { BITS_EOT } |
| 74 | }}, |
| 75 | {0x1a0, MSRTYPE_RDWR, MSR2(0,0), "IA32_MISC_ENABLES", "", { |
| 76 | { BITS_EOT } |
| 77 | }}, |
| 78 | {0x1d9, MSRTYPE_RDWR, MSR2(0,0), "IA32_DEBUGCTL", "", { |
| 79 | { BITS_EOT } |
| 80 | }}, |
| 81 | {0x200, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYSBASE0", "", { |
| 82 | { BITS_EOT } |
| 83 | }}, |
| 84 | {0x201, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYSMASK0", "", { |
| 85 | { BITS_EOT } |
| 86 | }}, |
| 87 | {0x202, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYSBASE1", "", { |
| 88 | { BITS_EOT } |
| 89 | }}, |
| 90 | {0x203, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYSMASK1", "", { |
| 91 | { BITS_EOT } |
| 92 | }}, |
| 93 | {0x204, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYSBASE2", "", { |
| 94 | { BITS_EOT } |
| 95 | }}, |
| 96 | {0x205, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYSMASK2", "", { |
| 97 | { BITS_EOT } |
| 98 | }}, |
| 99 | {0x206, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYSBASE3", "", { |
| 100 | { BITS_EOT } |
| 101 | }}, |
| 102 | {0x207, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYSMASK3", "", { |
| 103 | { BITS_EOT } |
| 104 | }}, |
| 105 | {0x208, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYSBASE4", "", { |
| 106 | { BITS_EOT } |
| 107 | }}, |
| 108 | {0x209, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYSMASK4", "", { |
| 109 | { BITS_EOT } |
| 110 | }}, |
| 111 | {0x20a, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYSBASE5", "", { |
| 112 | { BITS_EOT } |
| 113 | }}, |
| 114 | {0x20b, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYSMASK5", "", { |
| 115 | { BITS_EOT } |
| 116 | }}, |
| 117 | {0x20c, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYSBASE6", "", { |
| 118 | { BITS_EOT } |
| 119 | }}, |
| 120 | {0x20d, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYSMASK6", "", { |
| 121 | { BITS_EOT } |
| 122 | }}, |
| 123 | {0x20e, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYSBASE7", "", { |
| 124 | { BITS_EOT } |
| 125 | }}, |
| 126 | {0x20f, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYSMASK7", "", { |
| 127 | { BITS_EOT } |
| 128 | }}, |
| 129 | {0x250, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_FIX64K_00000", "", { |
| 130 | { BITS_EOT } |
| 131 | }}, |
| 132 | {0x258, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_FIX16K_80000", "", { |
| 133 | { BITS_EOT } |
| 134 | }}, |
| 135 | {0x259, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_FIX16K_A0000", "", { |
| 136 | { BITS_EOT } |
| 137 | }}, |
| 138 | {0x268, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_FIX4K_C0000", "", { |
| 139 | { BITS_EOT } |
| 140 | }}, |
| 141 | {0x269, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_FIX4K_C8000", "", { |
| 142 | { BITS_EOT } |
| 143 | }}, |
| 144 | {0x26a, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_FIX4K_D0000", "", { |
| 145 | { BITS_EOT } |
| 146 | }}, |
| 147 | {0x26b, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_FIX4K_D8000", "", { |
| 148 | { BITS_EOT } |
| 149 | }}, |
| 150 | {0x26c, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_FIX4K_E0000", "", { |
| 151 | { BITS_EOT } |
| 152 | }}, |
| 153 | {0x26d, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_FIX4K_E8000", "", { |
| 154 | { BITS_EOT } |
| 155 | }}, |
| 156 | {0x26e, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_FIX4K_F0000", "", { |
| 157 | { BITS_EOT } |
| 158 | }}, |
| 159 | {0x26f, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_FIX4K_F8000", "", { |
| 160 | { BITS_EOT } |
| 161 | }}, |
| 162 | {0x2ff, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_DEF_TYPE", "", { |
| 163 | { BITS_EOT } |
| 164 | }}, |
| 165 | {0x400, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC0_CTL", "", { |
| 166 | { BITS_EOT } |
| 167 | }}, |
| 168 | {0x401, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC0_STATUS", "", { |
| 169 | { BITS_EOT } |
| 170 | }}, |
| 171 | {0x402, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC0_ADDR", "", { |
| 172 | { BITS_EOT } |
| 173 | }}, |
| 174 | {0x40c, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC4_CTL", "", { |
| 175 | { BITS_EOT } |
| 176 | }}, |
| 177 | {0x40d, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC4_STATUS", "", { |
| 178 | { BITS_EOT } |
| 179 | }}, |
| 180 | {0x40e, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC4_ADDR", "", { |
| 181 | { BITS_EOT } |
| 182 | }}, |
| 183 | { MSR_EOT } |
| 184 | }; |