Patrick Georgi | e72a8a3 | 2012-11-06 11:05:09 +0100 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2008 Advanced Micro Devices, Inc. |
| 5 | * Copyright (C) 2008-2009 coresystems GmbH |
| 6 | * Copyright (C) 2012 secunet Security Networks AG |
| 7 | * |
| 8 | * This program is free software; you can redistribute it and/or modify |
| 9 | * it under the terms of the GNU General Public License as published by |
| 10 | * the Free Software Foundation; version 2 of the License. |
| 11 | * |
| 12 | * This program is distributed in the hope that it will be useful, |
| 13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 15 | * GNU General Public License for more details. |
| 16 | * |
| 17 | * You should have received a copy of the GNU General Public License |
| 18 | * along with this program; if not, write to the Free Software |
Paul Menzel | a46a712 | 2013-02-23 18:37:27 +0100 | [diff] [blame^] | 19 | * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA |
Patrick Georgi | e72a8a3 | 2012-11-06 11:05:09 +0100 | [diff] [blame] | 20 | */ |
| 21 | |
| 22 | #include <console/console.h> |
| 23 | #include <device/device.h> |
| 24 | #include <device/pci.h> |
| 25 | #include <device/pci_ids.h> |
| 26 | #include <device/pci_ops.h> |
| 27 | #include <arch/io.h> |
| 28 | #include <delay.h> |
| 29 | #include "i82801ix.h" |
| 30 | |
| 31 | #define HDA_ICII_REG 0x68 |
| 32 | #define HDA_ICII_BUSY (1 << 0) |
| 33 | #define HDA_ICII_VALID (1 << 1) |
| 34 | |
| 35 | typedef struct southbridge_intel_i82801ix_config config_t; |
| 36 | |
| 37 | static int set_bits(u32 port, u32 mask, u32 val) |
| 38 | { |
| 39 | u32 reg32; |
| 40 | int count; |
| 41 | |
| 42 | /* Write (val & mask) to port */ |
| 43 | val &= mask; |
| 44 | reg32 = read32(port); |
| 45 | reg32 &= ~mask; |
| 46 | reg32 |= val; |
| 47 | write32(port, reg32); |
| 48 | |
| 49 | /* Wait for readback of register to |
| 50 | * match what was just written to it |
| 51 | */ |
| 52 | count = 50; |
| 53 | do { |
| 54 | /* Wait 1ms based on BKDG wait time */ |
| 55 | mdelay(1); |
| 56 | reg32 = read32(port); |
| 57 | reg32 &= mask; |
| 58 | } while ((reg32 != val) && --count); |
| 59 | |
| 60 | /* Timeout occurred */ |
| 61 | if (!count) |
| 62 | return -1; |
| 63 | return 0; |
| 64 | } |
| 65 | |
| 66 | static int codec_detect(u32 base) |
| 67 | { |
| 68 | u32 reg32; |
| 69 | |
| 70 | /* Set Bit0 to 0 to enter reset state (BAR + 0x8)[0] */ |
| 71 | if (set_bits(base + 0x08, 1, 0) == -1) |
| 72 | goto no_codec; |
| 73 | |
| 74 | /* Set Bit 0 to 1 to exit reset state (BAR + 0x8)[0] */ |
| 75 | if (set_bits(base + 0x08, 1, 1) == -1) |
| 76 | goto no_codec; |
| 77 | |
| 78 | /* Read in Codec location (BAR + 0xe)[2..0]*/ |
| 79 | reg32 = read32(base + 0xe); |
| 80 | reg32 &= 0x0f; |
| 81 | if (!reg32) |
| 82 | goto no_codec; |
| 83 | |
| 84 | return reg32; |
| 85 | |
| 86 | no_codec: |
| 87 | /* Codec Not found */ |
| 88 | /* Put HDA back in reset (BAR + 0x8) [0] */ |
| 89 | set_bits(base + 0x08, 1, 0); |
| 90 | printk(BIOS_DEBUG, "Azalia: No codec!\n"); |
| 91 | return 0; |
| 92 | } |
| 93 | |
| 94 | const u32 * cim_verb_data = NULL; |
| 95 | u32 cim_verb_data_size = 0; |
| 96 | const u32 * pc_beep_verbs = NULL; |
| 97 | u32 pc_beep_verbs_size = 0; |
| 98 | |
| 99 | static u32 find_verb(struct device *dev, u32 viddid, const u32 ** verb) |
| 100 | { |
| 101 | int idx=0; |
| 102 | |
| 103 | while (idx < (cim_verb_data_size / sizeof(u32))) { |
| 104 | u32 verb_size = 4 * cim_verb_data[idx+2]; // in u32 |
| 105 | if (cim_verb_data[idx] != viddid) { |
| 106 | idx += verb_size + 3; // skip verb + header |
| 107 | continue; |
| 108 | } |
| 109 | *verb = &cim_verb_data[idx+3]; |
| 110 | return verb_size; |
| 111 | } |
| 112 | |
| 113 | /* Not all codecs need to load another verb */ |
| 114 | return 0; |
| 115 | } |
| 116 | |
| 117 | /** |
| 118 | * Wait 50usec for the codec to indicate it is ready |
| 119 | * no response would imply that the codec is non-operative |
| 120 | */ |
| 121 | |
| 122 | static int wait_for_ready(u32 base) |
| 123 | { |
| 124 | /* Use a 50 usec timeout - the Linux kernel uses the |
| 125 | * same duration */ |
| 126 | |
| 127 | int timeout = 50; |
| 128 | |
| 129 | while(timeout--) { |
| 130 | u32 reg32 = read32(base + HDA_ICII_REG); |
| 131 | if (!(reg32 & HDA_ICII_BUSY)) |
| 132 | return 0; |
| 133 | udelay(1); |
| 134 | } |
| 135 | |
| 136 | return -1; |
| 137 | } |
| 138 | |
| 139 | /** |
| 140 | * Wait 50usec for the codec to indicate that it accepted |
| 141 | * the previous command. No response would imply that the code |
| 142 | * is non-operative |
| 143 | */ |
| 144 | |
| 145 | static int wait_for_valid(u32 base) |
| 146 | { |
| 147 | u32 reg32; |
| 148 | |
| 149 | /* Send the verb to the codec */ |
| 150 | reg32 = read32(base + 0x68); |
| 151 | reg32 |= (1 << 0) | (1 << 1); |
| 152 | write32(base + 0x68, reg32); |
| 153 | |
| 154 | /* Use a 50 usec timeout - the Linux kernel uses the |
| 155 | * same duration */ |
| 156 | |
| 157 | int timeout = 50; |
| 158 | while(timeout--) { |
| 159 | reg32 = read32(base + HDA_ICII_REG); |
| 160 | if ((reg32 & (HDA_ICII_VALID | HDA_ICII_BUSY)) == |
| 161 | HDA_ICII_VALID) |
| 162 | return 0; |
| 163 | udelay(1); |
| 164 | } |
| 165 | |
| 166 | return -1; |
| 167 | } |
| 168 | |
| 169 | static void codec_init(struct device *dev, u32 base, int addr) |
| 170 | { |
| 171 | u32 reg32; |
| 172 | const u32 *verb; |
| 173 | u32 verb_size; |
| 174 | int i; |
| 175 | |
| 176 | printk(BIOS_DEBUG, "HD Audio: Initializing codec #%d\n", addr); |
| 177 | |
| 178 | /* 1 */ |
| 179 | if (wait_for_ready(base) == -1) |
| 180 | return; |
| 181 | |
| 182 | reg32 = (addr << 28) | 0x000f0000; |
| 183 | write32(base + 0x60, reg32); |
| 184 | |
| 185 | if (wait_for_valid(base) == -1) |
| 186 | return; |
| 187 | |
| 188 | reg32 = read32(base + 0x64); |
| 189 | |
| 190 | /* 2 */ |
| 191 | printk(BIOS_DEBUG, "Azalia: codec viddid: %08x\n", reg32); |
| 192 | verb_size = find_verb(dev, reg32, &verb); |
| 193 | |
| 194 | if (!verb_size) { |
| 195 | printk(BIOS_DEBUG, "Azalia: No verb!\n"); |
| 196 | return; |
| 197 | } |
| 198 | printk(BIOS_DEBUG, "Azalia: verb_size: %d\n", verb_size); |
| 199 | |
| 200 | /* 3 */ |
| 201 | for (i = 0; i < verb_size; i++) { |
| 202 | if (wait_for_ready(base) == -1) |
| 203 | return; |
| 204 | |
| 205 | write32(base + 0x60, verb[i]); |
| 206 | |
| 207 | if (wait_for_valid(base) == -1) |
| 208 | return; |
| 209 | } |
| 210 | printk(BIOS_DEBUG, "Azalia: verb loaded.\n"); |
| 211 | } |
| 212 | |
| 213 | static void codecs_init(struct device *dev, u32 base, u32 codec_mask) |
| 214 | { |
| 215 | int i; |
| 216 | for (i = 2; i >= 0; i--) { |
| 217 | if (codec_mask & (1 << i)) |
| 218 | codec_init(dev, base, i); |
| 219 | } |
| 220 | |
| 221 | for (i = 0; i < pc_beep_verbs_size; i++) { |
| 222 | if (wait_for_ready(base) == -1) |
| 223 | return; |
| 224 | |
| 225 | write32(base + 0x60, pc_beep_verbs[i]); |
| 226 | |
| 227 | if (wait_for_valid(base) == -1) |
| 228 | return; |
| 229 | } |
| 230 | } |
| 231 | |
| 232 | static void azalia_init(struct device *dev) |
| 233 | { |
| 234 | u32 base; |
| 235 | struct resource *res; |
| 236 | u32 codec_mask; |
| 237 | u8 reg8; |
| 238 | u32 reg32; |
| 239 | |
| 240 | #if CONFIG_MMCONF_SUPPORT |
| 241 | // ESD |
| 242 | reg32 = pci_mmio_read_config32(dev, 0x134); |
| 243 | reg32 &= 0xff00ffff; |
| 244 | reg32 |= (2 << 16); |
| 245 | pci_mmio_write_config32(dev, 0x134, reg32); |
| 246 | |
| 247 | // Link1 description |
| 248 | reg32 = pci_mmio_read_config32(dev, 0x140); |
| 249 | reg32 &= 0xff00ffff; |
| 250 | reg32 |= (2 << 16); |
| 251 | pci_mmio_write_config32(dev, 0x140, reg32); |
| 252 | |
| 253 | // Port VC0 Resource Control Register |
| 254 | reg32 = pci_mmio_read_config32(dev, 0x114); |
| 255 | reg32 &= 0xffffff00; |
| 256 | reg32 |= 1; |
| 257 | pci_mmio_write_config32(dev, 0x114, reg32); |
| 258 | |
| 259 | // VCi traffic class |
| 260 | reg8 = pci_mmio_read_config8(dev, 0x44); |
| 261 | reg8 |= (7 << 0); // TC7 |
| 262 | pci_mmio_write_config8(dev, 0x44, reg8); |
| 263 | |
| 264 | // VCi Resource Control |
| 265 | reg32 = pci_mmio_read_config32(dev, 0x120); |
| 266 | reg32 |= (1 << 31); |
| 267 | reg32 |= (1 << 24); // VCi ID |
| 268 | reg32 |= (0x80 << 0); // VCi map |
| 269 | pci_mmio_write_config32(dev, 0x120, reg32); |
| 270 | #else |
| 271 | #error ICH9 Azalia required CONFIG_MMCONF_SUPPORT |
| 272 | #endif |
| 273 | |
| 274 | /* Set Bus Master */ |
| 275 | reg32 = pci_read_config32(dev, PCI_COMMAND); |
| 276 | pci_write_config32(dev, PCI_COMMAND, reg32 | PCI_COMMAND_MASTER); |
| 277 | |
| 278 | reg8 = pci_read_config8(dev, 0x4d); // Docking Status |
| 279 | reg8 &= ~(1 << 7); // Docking not supported |
| 280 | pci_write_config8(dev, 0x4d, reg8); |
| 281 | |
| 282 | /* Lock some R/WO bits by writing their current value. */ |
| 283 | reg32 = pci_read_config32(dev, 0x74); |
| 284 | pci_write_config32(dev, 0x74, reg32); |
| 285 | |
| 286 | res = find_resource(dev, 0x10); |
| 287 | if (!res) |
| 288 | return; |
| 289 | |
| 290 | // NOTE this will break as soon as the Azalia get's a bar above |
| 291 | // 4G. Is there anything we can do about it? |
| 292 | base = (u32)res->base; |
| 293 | printk(BIOS_DEBUG, "Azalia: base = %08x\n", (u32)base); |
| 294 | codec_mask = codec_detect(base); |
| 295 | |
| 296 | if (codec_mask) { |
| 297 | printk(BIOS_DEBUG, "Azalia: codec_mask = %02x\n", codec_mask); |
| 298 | codecs_init(dev, base, codec_mask); |
| 299 | } |
| 300 | } |
| 301 | |
| 302 | static void azalia_set_subsystem(device_t dev, unsigned vendor, unsigned device) |
| 303 | { |
| 304 | if (!vendor || !device) { |
| 305 | pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, |
| 306 | pci_read_config32(dev, PCI_VENDOR_ID)); |
| 307 | } else { |
| 308 | pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, |
| 309 | ((device & 0xffff) << 16) | (vendor & 0xffff)); |
| 310 | } |
| 311 | } |
| 312 | |
| 313 | static struct pci_operations azalia_pci_ops = { |
| 314 | .set_subsystem = azalia_set_subsystem, |
| 315 | }; |
| 316 | |
| 317 | static struct device_operations azalia_ops = { |
| 318 | .read_resources = pci_dev_read_resources, |
| 319 | .set_resources = pci_dev_set_resources, |
| 320 | .enable_resources = pci_dev_enable_resources, |
| 321 | .init = azalia_init, |
| 322 | .scan_bus = 0, |
| 323 | .ops_pci = &azalia_pci_ops, |
| 324 | }; |
| 325 | |
| 326 | /* ICH9DH/ICH9DO/ICH9R/ICH9/ICH9M-E/ICH9M */ |
| 327 | static const struct pci_driver i82801ix_azalia __pci_driver = { |
| 328 | .ops = &azalia_ops, |
| 329 | .vendor = PCI_VENDOR_ID_INTEL, |
| 330 | .device = 0x293e, |
| 331 | }; |
| 332 | |