Angel Pons | 4b42983 | 2020-04-02 23:48:50 +0200 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
| 2 | /* This file is part of the coreboot project. */ |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 3 | |
Tristan Corrick | bc896cd | 2018-12-17 22:09:50 +1300 | [diff] [blame] | 4 | #include <commonlib/helpers.h> |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 5 | #include <console/console.h> |
| 6 | #include <arch/acpi.h> |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 7 | #include <stdint.h> |
| 8 | #include <delay.h> |
| 9 | #include <cpu/intel/haswell/haswell.h> |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 10 | #include <device/device.h> |
| 11 | #include <device/pci.h> |
Tristan Corrick | bc896cd | 2018-12-17 22:09:50 +1300 | [diff] [blame] | 12 | #include <device/pci_def.h> |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 13 | #include <device/pci_ids.h> |
Tristan Corrick | bc896cd | 2018-12-17 22:09:50 +1300 | [diff] [blame] | 14 | #include <device/pci_ops.h> |
Aaron Durbin | 1fef1f5 | 2012-12-19 17:15:43 -0600 | [diff] [blame] | 15 | #include <cpu/x86/smm.h> |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 16 | #include <boot/tables.h> |
Elyes HAOUAS | a1e22b8 | 2019-03-18 22:49:36 +0100 | [diff] [blame] | 17 | |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 18 | #include "chip.h" |
| 19 | #include "haswell.h" |
| 20 | |
Angel Pons | 1db5bc7 | 2020-01-15 00:49:03 +0100 | [diff] [blame] | 21 | static int get_pcie_bar(struct device *dev, unsigned int index, u32 *base, u32 *len) |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 22 | { |
Angel Pons | 1db5bc7 | 2020-01-15 00:49:03 +0100 | [diff] [blame] | 23 | u32 pciexbar_reg, mask; |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 24 | |
| 25 | *base = 0; |
| 26 | *len = 0; |
| 27 | |
Aaron Durbin | c12ef97 | 2012-12-18 14:22:49 -0600 | [diff] [blame] | 28 | pciexbar_reg = pci_read_config32(dev, index); |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 29 | |
| 30 | if (!(pciexbar_reg & (1 << 0))) |
| 31 | return 0; |
| 32 | |
| 33 | switch ((pciexbar_reg >> 1) & 3) { |
Angel Pons | 1db5bc7 | 2020-01-15 00:49:03 +0100 | [diff] [blame] | 34 | case 0: /* 256MB */ |
Ryan Salsamendi | fa0725d | 2017-06-30 17:29:37 -0700 | [diff] [blame] | 35 | mask = (1UL << 31) | (1 << 30) | (1 << 29) | (1 << 28); |
| 36 | *base = pciexbar_reg & mask; |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 37 | *len = 256 * 1024 * 1024; |
| 38 | return 1; |
Angel Pons | 1db5bc7 | 2020-01-15 00:49:03 +0100 | [diff] [blame] | 39 | case 1: /* 128M */ |
Ryan Salsamendi | fa0725d | 2017-06-30 17:29:37 -0700 | [diff] [blame] | 40 | mask = (1UL << 31) | (1 << 30) | (1 << 29) | (1 << 28); |
| 41 | mask |= (1 << 27); |
| 42 | *base = pciexbar_reg & mask; |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 43 | *len = 128 * 1024 * 1024; |
| 44 | return 1; |
Angel Pons | 1db5bc7 | 2020-01-15 00:49:03 +0100 | [diff] [blame] | 45 | case 2: /* 64M */ |
Ryan Salsamendi | fa0725d | 2017-06-30 17:29:37 -0700 | [diff] [blame] | 46 | mask = (1UL << 31) | (1 << 30) | (1 << 29) | (1 << 28); |
| 47 | mask |= (1 << 27) | (1 << 26); |
| 48 | *base = pciexbar_reg & mask; |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 49 | *len = 64 * 1024 * 1024; |
| 50 | return 1; |
| 51 | } |
| 52 | |
| 53 | return 0; |
| 54 | } |
| 55 | |
Elyes HAOUAS | 77f7a6e | 2018-05-09 17:47:59 +0200 | [diff] [blame] | 56 | static void pci_domain_set_resources(struct device *dev) |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 57 | { |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 58 | assign_resources(dev->link_list); |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 59 | } |
| 60 | |
Tristan Corrick | f3127d4 | 2018-10-31 02:25:54 +1300 | [diff] [blame] | 61 | static const char *northbridge_acpi_name(const struct device *dev) |
| 62 | { |
| 63 | if (dev->path.type == DEVICE_PATH_DOMAIN) |
| 64 | return "PCI0"; |
| 65 | |
| 66 | if (dev->path.type != DEVICE_PATH_PCI || dev->bus->secondary != 0) |
| 67 | return NULL; |
| 68 | |
| 69 | switch (dev->path.pci.devfn) { |
| 70 | case PCI_DEVFN(0, 0): |
| 71 | return "MCHC"; |
| 72 | } |
| 73 | |
| 74 | return NULL; |
| 75 | } |
| 76 | |
Angel Pons | 1db5bc7 | 2020-01-15 00:49:03 +0100 | [diff] [blame] | 77 | /* |
| 78 | * TODO: We could determine how many PCIe busses we need in the bar. |
| 79 | * For now, that number is hardcoded to a max of 64. |
| 80 | */ |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 81 | static struct device_operations pci_domain_ops = { |
Angel Pons | 1db5bc7 | 2020-01-15 00:49:03 +0100 | [diff] [blame] | 82 | .read_resources = pci_domain_read_resources, |
| 83 | .set_resources = pci_domain_set_resources, |
Angel Pons | 1db5bc7 | 2020-01-15 00:49:03 +0100 | [diff] [blame] | 84 | .scan_bus = pci_domain_scan_bus, |
| 85 | .acpi_name = northbridge_acpi_name, |
Matt DeVillier | 85d98d9 | 2018-03-04 01:41:23 -0600 | [diff] [blame] | 86 | .write_acpi_tables = northbridge_write_acpi_tables, |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 87 | }; |
| 88 | |
Elyes HAOUAS | 77f7a6e | 2018-05-09 17:47:59 +0200 | [diff] [blame] | 89 | static int get_bar(struct device *dev, unsigned int index, u32 *base, u32 *len) |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 90 | { |
Angel Pons | 1db5bc7 | 2020-01-15 00:49:03 +0100 | [diff] [blame] | 91 | u32 bar = pci_read_config32(dev, index); |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 92 | |
Angel Pons | 1db5bc7 | 2020-01-15 00:49:03 +0100 | [diff] [blame] | 93 | /* If not enabled don't report it */ |
Aaron Durbin | c12ef97 | 2012-12-18 14:22:49 -0600 | [diff] [blame] | 94 | if (!(bar & 0x1)) |
| 95 | return 0; |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 96 | |
Angel Pons | 1db5bc7 | 2020-01-15 00:49:03 +0100 | [diff] [blame] | 97 | /* Knock down the enable bit */ |
Aaron Durbin | c12ef97 | 2012-12-18 14:22:49 -0600 | [diff] [blame] | 98 | *base = bar & ~1; |
| 99 | |
| 100 | return 1; |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 101 | } |
| 102 | |
Angel Pons | 1db5bc7 | 2020-01-15 00:49:03 +0100 | [diff] [blame] | 103 | /* |
| 104 | * There are special BARs that actually are programmed in the MCHBAR. These Intel special |
| 105 | * features, but they do consume resources that need to be accounted for. |
| 106 | */ |
| 107 | static int get_bar_in_mchbar(struct device *dev, unsigned int index, u32 *base, u32 *len) |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 108 | { |
Angel Pons | 1db5bc7 | 2020-01-15 00:49:03 +0100 | [diff] [blame] | 109 | u32 bar = MCHBAR32(index); |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 110 | |
Angel Pons | 1db5bc7 | 2020-01-15 00:49:03 +0100 | [diff] [blame] | 111 | /* If not enabled don't report it */ |
Aaron Durbin | c12ef97 | 2012-12-18 14:22:49 -0600 | [diff] [blame] | 112 | if (!(bar & 0x1)) |
| 113 | return 0; |
| 114 | |
Angel Pons | 1db5bc7 | 2020-01-15 00:49:03 +0100 | [diff] [blame] | 115 | /* Knock down the enable bit */ |
Aaron Durbin | c12ef97 | 2012-12-18 14:22:49 -0600 | [diff] [blame] | 116 | *base = bar & ~1; |
| 117 | |
| 118 | return 1; |
| 119 | } |
| 120 | |
| 121 | struct fixed_mmio_descriptor { |
| 122 | unsigned int index; |
| 123 | u32 size; |
Angel Pons | 1db5bc7 | 2020-01-15 00:49:03 +0100 | [diff] [blame] | 124 | int (*get_resource)(struct device *dev, unsigned int index, u32 *base, u32 *size); |
Aaron Durbin | c12ef97 | 2012-12-18 14:22:49 -0600 | [diff] [blame] | 125 | const char *description; |
| 126 | }; |
| 127 | |
Angel Pons | 1db5bc7 | 2020-01-15 00:49:03 +0100 | [diff] [blame] | 128 | #define SIZE_KB(x) ((x) * 1024) |
Aaron Durbin | c12ef97 | 2012-12-18 14:22:49 -0600 | [diff] [blame] | 129 | struct fixed_mmio_descriptor mc_fixed_resources[] = { |
| 130 | { PCIEXBAR, SIZE_KB(0), get_pcie_bar, "PCIEXBAR" }, |
| 131 | { MCHBAR, SIZE_KB(32), get_bar, "MCHBAR" }, |
| 132 | { DMIBAR, SIZE_KB(4), get_bar, "DMIBAR" }, |
| 133 | { EPBAR, SIZE_KB(4), get_bar, "EPBAR" }, |
Angel Pons | 1db5bc7 | 2020-01-15 00:49:03 +0100 | [diff] [blame] | 134 | { GDXCBAR, SIZE_KB(4), get_bar_in_mchbar, "GDXCBAR" }, |
| 135 | { EDRAMBAR, SIZE_KB(16), get_bar_in_mchbar, "EDRAMBAR" }, |
Aaron Durbin | c12ef97 | 2012-12-18 14:22:49 -0600 | [diff] [blame] | 136 | }; |
| 137 | #undef SIZE_KB |
| 138 | |
Angel Pons | 1db5bc7 | 2020-01-15 00:49:03 +0100 | [diff] [blame] | 139 | /* Add all known fixed MMIO ranges that hang off the host bridge/memory controller device. */ |
Elyes HAOUAS | 77f7a6e | 2018-05-09 17:47:59 +0200 | [diff] [blame] | 140 | static void mc_add_fixed_mmio_resources(struct device *dev) |
Aaron Durbin | c12ef97 | 2012-12-18 14:22:49 -0600 | [diff] [blame] | 141 | { |
| 142 | int i; |
| 143 | |
| 144 | for (i = 0; i < ARRAY_SIZE(mc_fixed_resources); i++) { |
| 145 | u32 base; |
| 146 | u32 size; |
| 147 | struct resource *resource; |
| 148 | unsigned int index; |
| 149 | |
| 150 | size = mc_fixed_resources[i].size; |
| 151 | index = mc_fixed_resources[i].index; |
Angel Pons | 1db5bc7 | 2020-01-15 00:49:03 +0100 | [diff] [blame] | 152 | if (!mc_fixed_resources[i].get_resource(dev, index, &base, &size)) |
Aaron Durbin | c12ef97 | 2012-12-18 14:22:49 -0600 | [diff] [blame] | 153 | continue; |
| 154 | |
| 155 | resource = new_resource(dev, mc_fixed_resources[i].index); |
Angel Pons | 1db5bc7 | 2020-01-15 00:49:03 +0100 | [diff] [blame] | 156 | resource->flags = IORESOURCE_MEM | IORESOURCE_FIXED | IORESOURCE_STORED | |
| 157 | IORESOURCE_RESERVE | IORESOURCE_ASSIGNED; |
| 158 | |
Aaron Durbin | c12ef97 | 2012-12-18 14:22:49 -0600 | [diff] [blame] | 159 | resource->base = base; |
| 160 | resource->size = size; |
| 161 | printk(BIOS_DEBUG, "%s: Adding %s @ %x 0x%08lx-0x%08lx.\n", |
| 162 | __func__, mc_fixed_resources[i].description, index, |
| 163 | (unsigned long)base, (unsigned long)(base + size - 1)); |
| 164 | } |
| 165 | } |
| 166 | |
| 167 | /* Host Memory Map: |
| 168 | * |
| 169 | * +--------------------------+ TOUUD |
| 170 | * | | |
| 171 | * +--------------------------+ 4GiB |
| 172 | * | PCI Address Space | |
| 173 | * +--------------------------+ TOLUD (also maps into MC address space) |
| 174 | * | iGD | |
| 175 | * +--------------------------+ BDSM |
| 176 | * | GTT | |
| 177 | * +--------------------------+ BGSM |
| 178 | * | TSEG | |
| 179 | * +--------------------------+ TSEGMB |
| 180 | * | Usage DRAM | |
| 181 | * +--------------------------+ 0 |
| 182 | * |
Angel Pons | 1db5bc7 | 2020-01-15 00:49:03 +0100 | [diff] [blame] | 183 | * Some of the base registers above can be equal, making the size of the regions within 0. |
| 184 | * This is because the memory controller internally subtracts the base registers from each |
| 185 | * other to determine sizes of the regions. In other words, the memory map regions are always |
| 186 | * in a fixed order, no matter what sizes they have. |
Aaron Durbin | c12ef97 | 2012-12-18 14:22:49 -0600 | [diff] [blame] | 187 | */ |
| 188 | |
| 189 | struct map_entry { |
| 190 | int reg; |
| 191 | int is_64_bit; |
| 192 | int is_limit; |
| 193 | const char *description; |
| 194 | }; |
| 195 | |
Angel Pons | 1db5bc7 | 2020-01-15 00:49:03 +0100 | [diff] [blame] | 196 | static void read_map_entry(struct device *dev, struct map_entry *entry, uint64_t *result) |
Aaron Durbin | c12ef97 | 2012-12-18 14:22:49 -0600 | [diff] [blame] | 197 | { |
| 198 | uint64_t value; |
| 199 | uint64_t mask; |
| 200 | |
Angel Pons | 1db5bc7 | 2020-01-15 00:49:03 +0100 | [diff] [blame] | 201 | /* All registers have a 1MiB granularity */ |
| 202 | mask = ((1ULL << 20) - 1); |
Aaron Durbin | c12ef97 | 2012-12-18 14:22:49 -0600 | [diff] [blame] | 203 | mask = ~mask; |
| 204 | |
| 205 | value = 0; |
| 206 | |
| 207 | if (entry->is_64_bit) { |
| 208 | value = pci_read_config32(dev, entry->reg + 4); |
| 209 | value <<= 32; |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 210 | } |
| 211 | |
Aaron Durbin | c12ef97 | 2012-12-18 14:22:49 -0600 | [diff] [blame] | 212 | value |= pci_read_config32(dev, entry->reg); |
| 213 | value &= mask; |
| 214 | |
| 215 | if (entry->is_limit) |
| 216 | value |= ~mask; |
| 217 | |
| 218 | *result = value; |
| 219 | } |
| 220 | |
| 221 | #define MAP_ENTRY(reg_, is_64_, is_limit_, desc_) \ |
| 222 | { \ |
| 223 | .reg = reg_, \ |
| 224 | .is_64_bit = is_64_, \ |
| 225 | .is_limit = is_limit_, \ |
| 226 | .description = desc_, \ |
| 227 | } |
| 228 | |
Angel Pons | 1db5bc7 | 2020-01-15 00:49:03 +0100 | [diff] [blame] | 229 | #define MAP_ENTRY_BASE_32(reg_, desc_) MAP_ENTRY(reg_, 0, 0, desc_) |
| 230 | #define MAP_ENTRY_BASE_64(reg_, desc_) MAP_ENTRY(reg_, 1, 0, desc_) |
| 231 | #define MAP_ENTRY_LIMIT_64(reg_, desc_) MAP_ENTRY(reg_, 1, 1, desc_) |
Aaron Durbin | c12ef97 | 2012-12-18 14:22:49 -0600 | [diff] [blame] | 232 | |
| 233 | enum { |
| 234 | TOM_REG, |
| 235 | TOUUD_REG, |
| 236 | MESEG_BASE_REG, |
| 237 | MESEG_LIMIT_REG, |
| 238 | REMAP_BASE_REG, |
| 239 | REMAP_LIMIT_REG, |
| 240 | TOLUD_REG, |
| 241 | BGSM_REG, |
| 242 | BDSM_REG, |
| 243 | TSEG_REG, |
Angel Pons | 1db5bc7 | 2020-01-15 00:49:03 +0100 | [diff] [blame] | 244 | /* Must be last */ |
| 245 | NUM_MAP_ENTRIES, |
Aaron Durbin | c12ef97 | 2012-12-18 14:22:49 -0600 | [diff] [blame] | 246 | }; |
| 247 | |
| 248 | static struct map_entry memory_map[NUM_MAP_ENTRIES] = { |
Angel Pons | 1db5bc7 | 2020-01-15 00:49:03 +0100 | [diff] [blame] | 249 | [TOM_REG] = MAP_ENTRY_BASE_64(TOM, "TOM"), |
| 250 | [TOUUD_REG] = MAP_ENTRY_BASE_64(TOUUD, "TOUUD"), |
| 251 | [MESEG_BASE_REG] = MAP_ENTRY_BASE_64(MESEG_BASE, "MESEG_BASE"), |
Aaron Durbin | c12ef97 | 2012-12-18 14:22:49 -0600 | [diff] [blame] | 252 | [MESEG_LIMIT_REG] = MAP_ENTRY_LIMIT_64(MESEG_LIMIT, "MESEG_LIMIT"), |
Angel Pons | 1db5bc7 | 2020-01-15 00:49:03 +0100 | [diff] [blame] | 253 | [REMAP_BASE_REG] = MAP_ENTRY_BASE_64(REMAPBASE, "REMAP_BASE"), |
Aaron Durbin | c12ef97 | 2012-12-18 14:22:49 -0600 | [diff] [blame] | 254 | [REMAP_LIMIT_REG] = MAP_ENTRY_LIMIT_64(REMAPLIMIT, "REMAP_LIMIT"), |
Angel Pons | 1db5bc7 | 2020-01-15 00:49:03 +0100 | [diff] [blame] | 255 | [TOLUD_REG] = MAP_ENTRY_BASE_32(TOLUD, "TOLUD"), |
| 256 | [BDSM_REG] = MAP_ENTRY_BASE_32(BDSM, "BDSM"), |
| 257 | [BGSM_REG] = MAP_ENTRY_BASE_32(BGSM, "BGSM"), |
| 258 | [TSEG_REG] = MAP_ENTRY_BASE_32(TSEG, "TESGMB"), |
Aaron Durbin | c12ef97 | 2012-12-18 14:22:49 -0600 | [diff] [blame] | 259 | }; |
| 260 | |
Elyes HAOUAS | 77f7a6e | 2018-05-09 17:47:59 +0200 | [diff] [blame] | 261 | static void mc_read_map_entries(struct device *dev, uint64_t *values) |
Aaron Durbin | c12ef97 | 2012-12-18 14:22:49 -0600 | [diff] [blame] | 262 | { |
| 263 | int i; |
| 264 | for (i = 0; i < NUM_MAP_ENTRIES; i++) { |
| 265 | read_map_entry(dev, &memory_map[i], &values[i]); |
| 266 | } |
| 267 | } |
| 268 | |
Elyes HAOUAS | 77f7a6e | 2018-05-09 17:47:59 +0200 | [diff] [blame] | 269 | static void mc_report_map_entries(struct device *dev, uint64_t *values) |
Aaron Durbin | c12ef97 | 2012-12-18 14:22:49 -0600 | [diff] [blame] | 270 | { |
| 271 | int i; |
| 272 | for (i = 0; i < NUM_MAP_ENTRIES; i++) { |
| 273 | printk(BIOS_DEBUG, "MC MAP: %s: 0x%llx\n", |
| 274 | memory_map[i].description, values[i]); |
| 275 | } |
Angel Pons | 1db5bc7 | 2020-01-15 00:49:03 +0100 | [diff] [blame] | 276 | /* One can validate the BDSM and BGSM against the GGC */ |
Aaron Durbin | c12ef97 | 2012-12-18 14:22:49 -0600 | [diff] [blame] | 277 | printk(BIOS_DEBUG, "MC MAP: GGC: 0x%x\n", pci_read_config16(dev, GGC)); |
| 278 | } |
| 279 | |
Elyes HAOUAS | 77f7a6e | 2018-05-09 17:47:59 +0200 | [diff] [blame] | 280 | static void mc_add_dram_resources(struct device *dev, int *resource_cnt) |
Aaron Durbin | c12ef97 | 2012-12-18 14:22:49 -0600 | [diff] [blame] | 281 | { |
Angel Pons | 1db5bc7 | 2020-01-15 00:49:03 +0100 | [diff] [blame] | 282 | unsigned long base_k, size_k, touud_k, index; |
Aaron Durbin | c12ef97 | 2012-12-18 14:22:49 -0600 | [diff] [blame] | 283 | struct resource *resource; |
| 284 | uint64_t mc_values[NUM_MAP_ENTRIES]; |
| 285 | |
Angel Pons | 1db5bc7 | 2020-01-15 00:49:03 +0100 | [diff] [blame] | 286 | /* Read in the MAP registers and report their values */ |
Aaron Durbin | c12ef97 | 2012-12-18 14:22:49 -0600 | [diff] [blame] | 287 | mc_read_map_entries(dev, &mc_values[0]); |
| 288 | mc_report_map_entries(dev, &mc_values[0]); |
| 289 | |
| 290 | /* |
Aaron Durbin | 1fef1f5 | 2012-12-19 17:15:43 -0600 | [diff] [blame] | 291 | * These are the host memory ranges that should be added: |
Angel Pons | 1db5bc7 | 2020-01-15 00:49:03 +0100 | [diff] [blame] | 292 | * - 0 -> 0xa0000: cacheable |
| 293 | * - 0xc0000 -> TSEG: cacheable |
| 294 | * - TSEG -> BGSM: cacheable with standard MTRRs and reserved |
| 295 | * - BGSM -> TOLUD: not cacheable with standard MTRRs and reserved |
| 296 | * - 4GiB -> TOUUD: cacheable |
Aaron Durbin | c12ef97 | 2012-12-18 14:22:49 -0600 | [diff] [blame] | 297 | * |
Angel Pons | 1db5bc7 | 2020-01-15 00:49:03 +0100 | [diff] [blame] | 298 | * The default SMRAM space is reserved so that the range doesn't have to be saved |
| 299 | * during S3 Resume. Once marked reserved the OS cannot use the memory. This is a |
| 300 | * bit of an odd place to reserve the region, but the CPU devices don't have |
| 301 | * dev_ops->read_resources() called on them. |
Aaron Durbin | 1fef1f5 | 2012-12-19 17:15:43 -0600 | [diff] [blame] | 302 | * |
Angel Pons | 1db5bc7 | 2020-01-15 00:49:03 +0100 | [diff] [blame] | 303 | * The range 0xa0000 -> 0xc0000 does not have any resources associated with it to |
| 304 | * handle legacy VGA memory. If this range is not omitted the mtrr code will setup |
| 305 | * the area as cacheable, causing VGA access to not work. |
Aaron Durbin | c12ef97 | 2012-12-18 14:22:49 -0600 | [diff] [blame] | 306 | * |
Angel Pons | 1db5bc7 | 2020-01-15 00:49:03 +0100 | [diff] [blame] | 307 | * The TSEG region is mapped as cacheable so that one can perform SMRAM relocation |
| 308 | * faster. Once the SMRR is enabled, the SMRR takes precedence over the existing |
| 309 | * MTRRs covering this region. |
Aaron Durbin | e6c3b1d | 2012-12-21 21:22:07 -0600 | [diff] [blame] | 310 | * |
Angel Pons | 1db5bc7 | 2020-01-15 00:49:03 +0100 | [diff] [blame] | 311 | * It should be noted that cacheable entry types need to be added in order. The reason |
| 312 | * is that the current MTRR code assumes this and falls over itself if it isn't. |
Aaron Durbin | 1fef1f5 | 2012-12-19 17:15:43 -0600 | [diff] [blame] | 313 | * |
Angel Pons | 1db5bc7 | 2020-01-15 00:49:03 +0100 | [diff] [blame] | 314 | * The resource index starts low and should not meet or exceed PCI_BASE_ADDRESS_0. |
Aaron Durbin | c12ef97 | 2012-12-18 14:22:49 -0600 | [diff] [blame] | 315 | */ |
Matt DeVillier | a51e379 | 2018-03-04 01:44:15 -0600 | [diff] [blame] | 316 | index = *resource_cnt; |
Aaron Durbin | c12ef97 | 2012-12-18 14:22:49 -0600 | [diff] [blame] | 317 | |
Aaron Durbin | 6a36004 | 2014-02-13 10:30:42 -0600 | [diff] [blame] | 318 | /* 0 - > 0xa0000 */ |
Aaron Durbin | c12ef97 | 2012-12-18 14:22:49 -0600 | [diff] [blame] | 319 | base_k = 0; |
Aaron Durbin | 1fef1f5 | 2012-12-19 17:15:43 -0600 | [diff] [blame] | 320 | size_k = (0xa0000 >> 10) - base_k; |
| 321 | ram_resource(dev, index++, base_k, size_k); |
| 322 | |
| 323 | /* 0xc0000 -> TSEG */ |
Aaron Durbin | c12ef97 | 2012-12-18 14:22:49 -0600 | [diff] [blame] | 324 | base_k = 0xc0000 >> 10; |
| 325 | size_k = (unsigned long)(mc_values[TSEG_REG] >> 10) - base_k; |
| 326 | ram_resource(dev, index++, base_k, size_k); |
| 327 | |
Aaron Durbin | e6c3b1d | 2012-12-21 21:22:07 -0600 | [diff] [blame] | 328 | /* TSEG -> BGSM */ |
Aaron Durbin | c12ef97 | 2012-12-18 14:22:49 -0600 | [diff] [blame] | 329 | resource = new_resource(dev, index++); |
| 330 | resource->base = mc_values[TSEG_REG]; |
Aaron Durbin | e6c3b1d | 2012-12-21 21:22:07 -0600 | [diff] [blame] | 331 | resource->size = mc_values[BGSM_REG] - resource->base; |
Angel Pons | 1db5bc7 | 2020-01-15 00:49:03 +0100 | [diff] [blame] | 332 | resource->flags = IORESOURCE_MEM | IORESOURCE_FIXED | IORESOURCE_STORED | |
| 333 | IORESOURCE_RESERVE | IORESOURCE_ASSIGNED | IORESOURCE_CACHEABLE; |
Aaron Durbin | e6c3b1d | 2012-12-21 21:22:07 -0600 | [diff] [blame] | 334 | |
Angel Pons | 1db5bc7 | 2020-01-15 00:49:03 +0100 | [diff] [blame] | 335 | /* BGSM -> TOLUD. If the IGD is disabled, BGSM can equal TOLUD. */ |
Tristan Corrick | c5d367b | 2018-12-17 22:10:07 +1300 | [diff] [blame] | 336 | if (mc_values[BGSM_REG] != mc_values[TOLUD_REG]) { |
| 337 | resource = new_resource(dev, index++); |
| 338 | resource->base = mc_values[BGSM_REG]; |
| 339 | resource->size = mc_values[TOLUD_REG] - resource->base; |
Angel Pons | 1db5bc7 | 2020-01-15 00:49:03 +0100 | [diff] [blame] | 340 | resource->flags = IORESOURCE_MEM | IORESOURCE_FIXED | IORESOURCE_STORED | |
| 341 | IORESOURCE_RESERVE | IORESOURCE_ASSIGNED; |
Tristan Corrick | c5d367b | 2018-12-17 22:10:07 +1300 | [diff] [blame] | 342 | } |
Aaron Durbin | c12ef97 | 2012-12-18 14:22:49 -0600 | [diff] [blame] | 343 | |
| 344 | /* 4GiB -> TOUUD */ |
| 345 | base_k = 4096 * 1024; /* 4GiB */ |
Aaron Durbin | 27435d3 | 2013-06-03 09:46:56 -0500 | [diff] [blame] | 346 | touud_k = mc_values[TOUUD_REG] >> 10; |
| 347 | size_k = touud_k - base_k; |
| 348 | if (touud_k > base_k) |
Aaron Durbin | 5c66f08 | 2013-01-08 10:10:33 -0600 | [diff] [blame] | 349 | ram_resource(dev, index++, base_k, size_k); |
Aaron Durbin | c12ef97 | 2012-12-18 14:22:49 -0600 | [diff] [blame] | 350 | |
Aaron Durbin | c965076 | 2013-03-22 22:03:09 -0500 | [diff] [blame] | 351 | /* Reserve everything between A segment and 1MB: |
| 352 | * |
Angel Pons | 1db5bc7 | 2020-01-15 00:49:03 +0100 | [diff] [blame] | 353 | * 0xa0000 - 0xbffff: Legacy VGA |
Aaron Durbin | c965076 | 2013-03-22 22:03:09 -0500 | [diff] [blame] | 354 | * 0xc0000 - 0xfffff: RAM |
| 355 | */ |
| 356 | mmio_resource(dev, index++, (0xa0000 >> 10), (0xc0000 - 0xa0000) >> 10); |
Angel Pons | 1db5bc7 | 2020-01-15 00:49:03 +0100 | [diff] [blame] | 357 | reserved_ram_resource(dev, index++, (0xc0000 >> 10), (0x100000 - 0xc0000) >> 10); |
| 358 | |
Julius Werner | cd49cce | 2019-03-05 16:53:33 -0800 | [diff] [blame] | 359 | #if CONFIG(CHROMEOS_RAMOOPS) |
Aaron Durbin | c965076 | 2013-03-22 22:03:09 -0500 | [diff] [blame] | 360 | reserved_ram_resource(dev, index++, |
| 361 | CONFIG_CHROMEOS_RAMOOPS_RAM_START >> 10, |
Angel Pons | 1db5bc7 | 2020-01-15 00:49:03 +0100 | [diff] [blame] | 362 | CONFIG_CHROMEOS_RAMOOPS_RAM_SIZE >> 10); |
Aaron Durbin | c12ef97 | 2012-12-18 14:22:49 -0600 | [diff] [blame] | 363 | #endif |
Matt DeVillier | a51e379 | 2018-03-04 01:44:15 -0600 | [diff] [blame] | 364 | *resource_cnt = index; |
Aaron Durbin | c12ef97 | 2012-12-18 14:22:49 -0600 | [diff] [blame] | 365 | } |
| 366 | |
Elyes HAOUAS | 77f7a6e | 2018-05-09 17:47:59 +0200 | [diff] [blame] | 367 | static void mc_read_resources(struct device *dev) |
Aaron Durbin | c12ef97 | 2012-12-18 14:22:49 -0600 | [diff] [blame] | 368 | { |
Matt DeVillier | a51e379 | 2018-03-04 01:44:15 -0600 | [diff] [blame] | 369 | int index = 0; |
Angel Pons | 1db5bc7 | 2020-01-15 00:49:03 +0100 | [diff] [blame] | 370 | const bool vtd_capable = !(pci_read_config32(dev, CAPID0_A) & VTD_DISABLE); |
Matt DeVillier | a51e379 | 2018-03-04 01:44:15 -0600 | [diff] [blame] | 371 | |
Angel Pons | 1db5bc7 | 2020-01-15 00:49:03 +0100 | [diff] [blame] | 372 | /* Read standard PCI resources */ |
Aaron Durbin | c12ef97 | 2012-12-18 14:22:49 -0600 | [diff] [blame] | 373 | pci_dev_read_resources(dev); |
| 374 | |
Angel Pons | 1db5bc7 | 2020-01-15 00:49:03 +0100 | [diff] [blame] | 375 | /* Add all fixed MMIO resources */ |
Aaron Durbin | c12ef97 | 2012-12-18 14:22:49 -0600 | [diff] [blame] | 376 | mc_add_fixed_mmio_resources(dev); |
| 377 | |
Angel Pons | 1db5bc7 | 2020-01-15 00:49:03 +0100 | [diff] [blame] | 378 | /* Add VT-d MMIO resources, if capable */ |
Matt DeVillier | a51e379 | 2018-03-04 01:44:15 -0600 | [diff] [blame] | 379 | if (vtd_capable) { |
Angel Pons | 1db5bc7 | 2020-01-15 00:49:03 +0100 | [diff] [blame] | 380 | mmio_resource(dev, index++, GFXVT_BASE_ADDRESS / KiB, GFXVT_BASE_SIZE / KiB); |
| 381 | mmio_resource(dev, index++, VTVC0_BASE_ADDRESS / KiB, VTVC0_BASE_SIZE / KiB); |
Matt DeVillier | a51e379 | 2018-03-04 01:44:15 -0600 | [diff] [blame] | 382 | } |
| 383 | |
Angel Pons | 1db5bc7 | 2020-01-15 00:49:03 +0100 | [diff] [blame] | 384 | /* Calculate and add DRAM resources */ |
Matt DeVillier | a51e379 | 2018-03-04 01:44:15 -0600 | [diff] [blame] | 385 | mc_add_dram_resources(dev, &index); |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 386 | } |
| 387 | |
Tristan Corrick | bc896cd | 2018-12-17 22:09:50 +1300 | [diff] [blame] | 388 | /* |
Angel Pons | 1db5bc7 | 2020-01-15 00:49:03 +0100 | [diff] [blame] | 389 | * The Mini-HD audio device is disabled whenever the IGD is. This is because it provides |
| 390 | * audio over the integrated graphics port(s), which requires the IGD to be functional. |
Tristan Corrick | bc896cd | 2018-12-17 22:09:50 +1300 | [diff] [blame] | 391 | */ |
| 392 | static void disable_devices(void) |
| 393 | { |
| 394 | static const struct { |
| 395 | const unsigned int devfn; |
| 396 | const u32 mask; |
| 397 | const char *const name; |
| 398 | } nb_devs[] = { |
| 399 | { PCI_DEVFN(1, 2), DEVEN_D1F2EN, "PEG12" }, |
| 400 | { PCI_DEVFN(1, 1), DEVEN_D1F1EN, "PEG11" }, |
| 401 | { PCI_DEVFN(1, 0), DEVEN_D1F0EN, "PEG10" }, |
| 402 | { PCI_DEVFN(2, 0), DEVEN_D2EN | DEVEN_D3EN, "IGD" }, |
| 403 | { PCI_DEVFN(3, 0), DEVEN_D3EN, "Mini-HD audio" }, |
| 404 | { PCI_DEVFN(4, 0), DEVEN_D4EN, "\"device 4\"" }, |
| 405 | { PCI_DEVFN(7, 0), DEVEN_D7EN, "\"device 7\"" }, |
| 406 | }; |
| 407 | |
Angel Pons | 1db5bc7 | 2020-01-15 00:49:03 +0100 | [diff] [blame] | 408 | struct device *host_dev = pcidev_on_root(0, 0); |
Tristan Corrick | bc896cd | 2018-12-17 22:09:50 +1300 | [diff] [blame] | 409 | u32 deven; |
| 410 | size_t i; |
| 411 | |
| 412 | if (!host_dev) |
| 413 | return; |
| 414 | |
| 415 | deven = pci_read_config32(host_dev, DEVEN); |
| 416 | |
| 417 | for (i = 0; i < ARRAY_SIZE(nb_devs); i++) { |
Kyösti Mälkki | e737755 | 2018-06-21 16:20:55 +0300 | [diff] [blame] | 418 | struct device *dev = pcidev_path_on_root(nb_devs[i].devfn); |
Tristan Corrick | bc896cd | 2018-12-17 22:09:50 +1300 | [diff] [blame] | 419 | if (!dev || !dev->enabled) { |
| 420 | printk(BIOS_DEBUG, "Disabling %s.\n", nb_devs[i].name); |
| 421 | deven &= ~nb_devs[i].mask; |
| 422 | } |
| 423 | } |
| 424 | |
| 425 | pci_write_config32(host_dev, DEVEN, deven); |
| 426 | } |
| 427 | |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 428 | static void northbridge_init(struct device *dev) |
| 429 | { |
Duncan Laurie | c70353f | 2013-06-28 14:40:38 -0700 | [diff] [blame] | 430 | u8 bios_reset_cpl, pair; |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 431 | |
Angel Pons | 1db5bc7 | 2020-01-15 00:49:03 +0100 | [diff] [blame] | 432 | /* Enable Power Aware Interrupt Routing. */ |
| 433 | pair = MCHBAR8(INTRDIRCTL); |
Duncan Laurie | c70353f | 2013-06-28 14:40:38 -0700 | [diff] [blame] | 434 | pair &= ~0x7; /* Clear 2:0 */ |
| 435 | pair |= 0x4; /* Fixed Priority */ |
Angel Pons | 1db5bc7 | 2020-01-15 00:49:03 +0100 | [diff] [blame] | 436 | MCHBAR8(INTRDIRCTL) = pair; |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 437 | |
Tristan Corrick | bc896cd | 2018-12-17 22:09:50 +1300 | [diff] [blame] | 438 | disable_devices(); |
| 439 | |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 440 | /* |
Angel Pons | 1db5bc7 | 2020-01-15 00:49:03 +0100 | [diff] [blame] | 441 | * Set bits 0 + 1 of BIOS_RESET_CPL to indicate to the CPU |
| 442 | * that BIOS has initialized memory and power management. |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 443 | */ |
| 444 | bios_reset_cpl = MCHBAR8(BIOS_RESET_CPL); |
Duncan Laurie | c70353f | 2013-06-28 14:40:38 -0700 | [diff] [blame] | 445 | bios_reset_cpl |= 3; |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 446 | MCHBAR8(BIOS_RESET_CPL) = bios_reset_cpl; |
| 447 | printk(BIOS_DEBUG, "Set BIOS_RESET_CPL\n"); |
| 448 | |
Angel Pons | 1db5bc7 | 2020-01-15 00:49:03 +0100 | [diff] [blame] | 449 | /* Configure turbo power limits 1ms after reset complete bit. */ |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 450 | mdelay(1); |
| 451 | set_power_limits(28); |
| 452 | |
Angel Pons | 1db5bc7 | 2020-01-15 00:49:03 +0100 | [diff] [blame] | 453 | /* Set here before graphics PM init. */ |
| 454 | MCHBAR32(MMIO_PAVP_MSG) = 0x00100001; |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 455 | } |
| 456 | |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 457 | static struct pci_operations intel_pci_ops = { |
Subrata Banik | 4a0f071 | 2019-03-20 14:29:47 +0530 | [diff] [blame] | 458 | .set_subsystem = pci_dev_set_subsystem, |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 459 | }; |
| 460 | |
| 461 | static struct device_operations mc_ops = { |
Nico Huber | 68680dd | 2020-03-31 17:34:52 +0200 | [diff] [blame] | 462 | .read_resources = mc_read_resources, |
| 463 | .set_resources = pci_dev_set_resources, |
| 464 | .enable_resources = pci_dev_enable_resources, |
| 465 | .init = northbridge_init, |
| 466 | .acpi_fill_ssdt = generate_cpu_entries, |
Nico Huber | 68680dd | 2020-03-31 17:34:52 +0200 | [diff] [blame] | 467 | .ops_pci = &intel_pci_ops, |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 468 | }; |
| 469 | |
Tristan Corrick | d385624 | 2018-11-01 03:03:29 +1300 | [diff] [blame] | 470 | static const unsigned short mc_pci_device_ids[] = { |
| 471 | 0x0c00, /* Desktop */ |
| 472 | 0x0c04, /* Mobile */ |
| 473 | 0x0a04, /* ULT */ |
Iru Cai | 0766c98 | 2018-12-17 13:21:36 +0800 | [diff] [blame] | 474 | 0x0c08, /* Server */ |
Tristan Corrick | d385624 | 2018-11-01 03:03:29 +1300 | [diff] [blame] | 475 | 0 |
Tristan Corrick | 4817012 | 2018-10-31 02:21:41 +1300 | [diff] [blame] | 476 | }; |
| 477 | |
Tristan Corrick | d385624 | 2018-11-01 03:03:29 +1300 | [diff] [blame] | 478 | static const struct pci_driver mc_driver_hsw __pci_driver = { |
| 479 | .ops = &mc_ops, |
| 480 | .vendor = PCI_VENDOR_ID_INTEL, |
| 481 | .devices = mc_pci_device_ids, |
Duncan Laurie | df7be71 | 2012-12-17 11:22:57 -0800 | [diff] [blame] | 482 | }; |
| 483 | |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 484 | static struct device_operations cpu_bus_ops = { |
Edward O'Callaghan | 9f74462 | 2014-10-31 08:12:34 +1100 | [diff] [blame] | 485 | .read_resources = DEVICE_NOOP, |
| 486 | .set_resources = DEVICE_NOOP, |
Kyösti Mälkki | b3267e0 | 2019-08-13 16:44:04 +0300 | [diff] [blame] | 487 | .init = mp_cpu_bus_init, |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 488 | }; |
| 489 | |
Elyes HAOUAS | 77f7a6e | 2018-05-09 17:47:59 +0200 | [diff] [blame] | 490 | static void enable_dev(struct device *dev) |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 491 | { |
Angel Pons | 1db5bc7 | 2020-01-15 00:49:03 +0100 | [diff] [blame] | 492 | /* Set the operations if it is a special bus type. */ |
Aaron Durbin | 76c3700 | 2012-10-30 09:03:43 -0500 | [diff] [blame] | 493 | if (dev->path.type == DEVICE_PATH_DOMAIN) { |
| 494 | dev->ops = &pci_domain_ops; |
| 495 | } else if (dev->path.type == DEVICE_PATH_CPU_CLUSTER) { |
| 496 | dev->ops = &cpu_bus_ops; |
| 497 | } |
| 498 | } |
| 499 | |
| 500 | struct chip_operations northbridge_intel_haswell_ops = { |
| 501 | CHIP_NAME("Intel i7 (Haswell) integrated Northbridge") |
| 502 | .enable_dev = enable_dev, |
| 503 | }; |