Naresh G Solanki | 335781a | 2016-10-26 19:43:14 +0530 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2016 Intel Corporation. |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or modify |
| 7 | * it under the terms of the GNU General Public License as published by |
| 8 | * the Free Software Foundation; version 2 of the License. |
| 9 | * |
| 10 | * This program is distributed in the hope that it will be useful, |
| 11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 13 | * GNU General Public License for more details. |
| 14 | */ |
| 15 | |
| 16 | #include <arch/byteorder.h> |
| 17 | #include <cbfs.h> |
| 18 | #include <console/console.h> |
| 19 | #include <spd_bin.h> |
| 20 | #include <string.h> |
| 21 | #include <device/early_smbus.h> |
Patrick Georgi | 0e3c59e | 2017-01-28 15:59:25 +0100 | [diff] [blame] | 22 | #include <device/dram/ddr3.h> |
Naresh G Solanki | 335781a | 2016-10-26 19:43:14 +0530 | [diff] [blame] | 23 | |
| 24 | static u8 spd_data[CONFIG_DIMM_MAX * CONFIG_DIMM_SPD_SIZE] CAR_GLOBAL; |
| 25 | |
| 26 | void dump_spd_info(struct spd_block *blk) |
| 27 | { |
| 28 | u8 i; |
| 29 | |
| 30 | for (i = 0; i < CONFIG_DIMM_MAX; i++) |
| 31 | if (blk->spd_array[i] != NULL && blk->spd_array[i][0] != 0) { |
| 32 | printk(BIOS_DEBUG, "SPD @ 0x%02X\n", 0xA0|(i << 1)); |
| 33 | print_spd_info(blk->spd_array[i]); |
| 34 | } |
| 35 | } |
| 36 | |
| 37 | void print_spd_info(uint8_t spd[]) |
| 38 | { |
| 39 | const int spd_banks[8] = { 8, 16, 32, 64, -1, -1, -1, -1 }; |
| 40 | const int spd_capmb[8] = { 1, 2, 4, 8, 16, 32, 64, 128 }; |
| 41 | const int spd_rows[8] = {12, 13, 14, 15, 16, 17, -1, -1 }; |
| 42 | const int spd_cols[8] = { 9, 10, 11, 12, -1, -1, -1, -1 }; |
| 43 | const int spd_ranks[8] = { 1, 2, 3, 4, -1, -1, -1, -1 }; |
| 44 | const int spd_devw[8] = { 4, 8, 16, 32, -1, -1, -1, -1 }; |
| 45 | const int spd_busw[8] = { 8, 16, 32, 64, -1, -1, -1, -1 }; |
| 46 | char spd_name[DDR4_SPD_PART_LEN+1] = { 0 }; |
| 47 | |
| 48 | int banks = spd_banks[(spd[SPD_DENSITY_BANKS] >> 4) & 7]; |
| 49 | int capmb = spd_capmb[spd[SPD_DENSITY_BANKS] & 7] * 256; |
| 50 | int rows = spd_rows[(spd[SPD_ADDRESSING] >> 3) & 7]; |
| 51 | int cols = spd_cols[spd[SPD_ADDRESSING] & 7]; |
| 52 | int ranks = spd_ranks[(spd[SPD_ORGANIZATION] >> 3) & 7]; |
| 53 | int devw = spd_devw[spd[SPD_ORGANIZATION] & 7]; |
| 54 | int busw = spd_busw[spd[SPD_BUS_DEV_WIDTH] & 7]; |
| 55 | |
| 56 | /* Module type */ |
| 57 | printk(BIOS_INFO, "SPD: module type is "); |
| 58 | switch (spd[SPD_DRAM_TYPE]) { |
| 59 | case SPD_DRAM_DDR3: |
| 60 | printk(BIOS_INFO, "DDR3\n"); |
| 61 | /* Module Part Number */ |
| 62 | memcpy(spd_name, &spd[DDR3_SPD_PART_OFF], DDR3_SPD_PART_LEN); |
| 63 | spd_name[DDR3_SPD_PART_LEN] = 0; |
| 64 | break; |
| 65 | case SPD_DRAM_LPDDR3_INTEL: |
| 66 | case SPD_DRAM_LPDDR3_JEDEC: |
| 67 | printk(BIOS_INFO, "LPDDR3\n"); |
| 68 | /* Module Part Number */ |
| 69 | memcpy(spd_name, &spd[LPDDR3_SPD_PART_OFF], |
| 70 | LPDDR3_SPD_PART_LEN); |
| 71 | spd_name[LPDDR3_SPD_PART_LEN] = 0; |
| 72 | break; |
| 73 | case SPD_DRAM_DDR4: |
| 74 | printk(BIOS_INFO, "DDR4\n"); |
| 75 | memcpy(spd_name, &spd[DDR4_SPD_PART_OFF], DDR4_SPD_PART_LEN); |
| 76 | spd_name[DDR4_SPD_PART_LEN] = 0; |
| 77 | ranks = (spd[SPD_ORGANIZATION] >> 3) & 7; |
| 78 | devw = spd_devw[spd[12] & 7]; |
| 79 | busw = spd_busw[spd[13] & 7]; |
| 80 | break; |
| 81 | default: |
| 82 | printk(BIOS_INFO, "Unknown (%02x)\n", spd[SPD_DRAM_TYPE]); |
| 83 | break; |
| 84 | } |
| 85 | |
| 86 | printk(BIOS_INFO, "SPD: module part is %s\n", spd_name); |
| 87 | |
| 88 | printk(BIOS_INFO, |
| 89 | "SPD: banks %d, ranks %d, rows %d, columns %d, density %d Mb\n", |
| 90 | banks, ranks, rows, cols, capmb); |
| 91 | printk(BIOS_INFO, "SPD: device width %d bits, bus width %d bits\n", |
| 92 | devw, busw); |
| 93 | |
| 94 | if (capmb > 0 && busw > 0 && devw > 0 && ranks > 0) { |
| 95 | /* SIZE = DENSITY / 8 * BUS_WIDTH / SDRAM_WIDTH * RANKS */ |
| 96 | printk(BIOS_INFO, "SPD: module size is %u MB (per channel)\n", |
| 97 | capmb / 8 * busw / devw * ranks); |
| 98 | } |
| 99 | } |
| 100 | |
| 101 | static void update_spd_len(struct spd_block *blk) |
| 102 | { |
| 103 | u8 i, j = 0; |
| 104 | for (i = 0 ; i < CONFIG_DIMM_MAX; i++) |
| 105 | if (blk->spd_array[i] != NULL) |
| 106 | j |= blk->spd_array[i][SPD_DRAM_TYPE]; |
| 107 | |
| 108 | /* If spd used is DDR4, then its length is 512 byte. */ |
| 109 | if (j == SPD_DRAM_DDR4) |
| 110 | blk->len = SPD_PAGE_LEN_DDR4; |
| 111 | else |
| 112 | blk->len = SPD_PAGE_LEN; |
| 113 | } |
| 114 | |
| 115 | int get_spd_cbfs_rdev(struct region_device *spd_rdev, u8 spd_index) |
| 116 | { |
| 117 | struct cbfsf fh; |
| 118 | |
| 119 | uint32_t cbfs_type = CBFS_TYPE_SPD; |
| 120 | |
Naresh G Solanki | b8a5736 | 2016-12-13 20:27:15 +0530 | [diff] [blame] | 121 | if (cbfs_boot_locate(&fh, "spd.bin", &cbfs_type) < 0) |
| 122 | return -1; |
Naresh G Solanki | 335781a | 2016-10-26 19:43:14 +0530 | [diff] [blame] | 123 | cbfs_file_data(spd_rdev, &fh); |
| 124 | return rdev_chain(spd_rdev, spd_rdev, spd_index * CONFIG_DIMM_SPD_SIZE, |
| 125 | CONFIG_DIMM_SPD_SIZE); |
| 126 | } |
| 127 | |
| 128 | static void get_spd(u8 *spd, u8 addr) |
| 129 | { |
| 130 | u16 i; |
| 131 | /* Assuming addr is 8 bit address, make it 7 bit */ |
| 132 | addr = addr >> 1; |
| 133 | if (smbus_read_byte(0, addr, 0) == 0xff) { |
| 134 | printk(BIOS_INFO, "No memory dimm at address %02X\n", |
| 135 | addr << 1); |
| 136 | /* Make sure spd is zeroed if dimm doesn't exist. */ |
| 137 | memset(spd, 0, CONFIG_DIMM_SPD_SIZE); |
| 138 | return; |
| 139 | } |
| 140 | |
| 141 | for (i = 0; i < SPD_PAGE_LEN; i++) |
| 142 | spd[i] = smbus_read_byte(0, addr, i); |
| 143 | /* Check if module is DDR4, DDR4 spd is 512 byte. */ |
| 144 | if (spd[SPD_DRAM_TYPE] == SPD_DRAM_DDR4 && |
| 145 | CONFIG_DIMM_SPD_SIZE >= SPD_DRAM_DDR4) { |
| 146 | /* Switch to page 1 */ |
| 147 | smbus_write_byte(0, SPD_PAGE_1, 0, 0); |
| 148 | for (i = 0; i < SPD_PAGE_LEN; i++) |
| 149 | spd[i+SPD_PAGE_LEN] = smbus_read_byte(0, addr, i); |
| 150 | /* Restore to page 0 */ |
| 151 | smbus_write_byte(0, SPD_PAGE_0, 0, 0); |
| 152 | } |
| 153 | } |
| 154 | |
| 155 | void get_spd_smbus(struct spd_block *blk) |
| 156 | { |
Naresh G Solanki | b8a5736 | 2016-12-13 20:27:15 +0530 | [diff] [blame] | 157 | u8 i; |
Naresh G Solanki | 335781a | 2016-10-26 19:43:14 +0530 | [diff] [blame] | 158 | unsigned char *spd_data_ptr = car_get_var_ptr(&spd_data); |
| 159 | |
| 160 | for (i = 0 ; i < CONFIG_DIMM_MAX; i++) { |
| 161 | get_spd(spd_data_ptr + i * CONFIG_DIMM_SPD_SIZE, |
| 162 | 0xA0 + (i << 1)); |
| 163 | blk->spd_array[i] = spd_data_ptr + i * CONFIG_DIMM_SPD_SIZE; |
| 164 | } |
| 165 | |
Naresh G Solanki | 335781a | 2016-10-26 19:43:14 +0530 | [diff] [blame] | 166 | update_spd_len(blk); |
| 167 | } |
Patrick Georgi | 0e3c59e | 2017-01-28 15:59:25 +0100 | [diff] [blame] | 168 | |
| 169 | #if CONFIG_DIMM_SPD_SIZE == 128 |
| 170 | int read_ddr3_spd_from_cbfs(u8 *buf, int idx) |
| 171 | { |
| 172 | const int SPD_CRC_HI = 127; |
| 173 | const int SPD_CRC_LO = 126; |
| 174 | |
| 175 | const char *spd_file; |
| 176 | size_t spd_file_len = 0; |
| 177 | size_t min_len = (idx + 1) * CONFIG_DIMM_SPD_SIZE; |
| 178 | |
| 179 | spd_file = cbfs_boot_map_with_leak("spd.bin", CBFS_TYPE_SPD, |
| 180 | &spd_file_len); |
| 181 | if (!spd_file) |
| 182 | printk(BIOS_EMERG, "file [spd.bin] not found in CBFS"); |
| 183 | if (spd_file_len < min_len) |
| 184 | printk(BIOS_EMERG, "Missing SPD data."); |
| 185 | if (!spd_file || spd_file_len < min_len) |
| 186 | return -1; |
| 187 | |
Lee Leahy | 7340217 | 2017-03-10 15:23:24 -0800 | [diff] [blame] | 188 | memcpy(buf, spd_file + (idx * CONFIG_DIMM_SPD_SIZE), |
| 189 | CONFIG_DIMM_SPD_SIZE); |
Patrick Georgi | 0e3c59e | 2017-01-28 15:59:25 +0100 | [diff] [blame] | 190 | |
| 191 | u16 crc = spd_ddr3_calc_crc(buf, CONFIG_DIMM_SPD_SIZE); |
| 192 | |
| 193 | if (((buf[SPD_CRC_LO] == 0) && (buf[SPD_CRC_HI] == 0)) |
Lee Leahy | e20a319 | 2017-03-09 16:21:34 -0800 | [diff] [blame] | 194 | || (buf[SPD_CRC_LO] != (crc & 0xff)) |
| 195 | || (buf[SPD_CRC_HI] != (crc >> 8))) { |
Lee Leahy | 7340217 | 2017-03-10 15:23:24 -0800 | [diff] [blame] | 196 | printk(BIOS_WARNING, |
| 197 | "SPD CRC %02x%02x is invalid, should be %04x\n", |
Patrick Georgi | 0e3c59e | 2017-01-28 15:59:25 +0100 | [diff] [blame] | 198 | buf[SPD_CRC_HI], buf[SPD_CRC_LO], crc); |
| 199 | buf[SPD_CRC_LO] = crc & 0xff; |
| 200 | buf[SPD_CRC_HI] = crc >> 8; |
| 201 | u16 i; |
| 202 | printk(BIOS_WARNING, "\nDisplay the SPD"); |
| 203 | for (i = 0; i < CONFIG_DIMM_SPD_SIZE; i++) { |
Lee Leahy | 45fde70 | 2017-03-08 18:02:24 -0800 | [diff] [blame] | 204 | if ((i % 16) == 0x00) |
Patrick Georgi | 0e3c59e | 2017-01-28 15:59:25 +0100 | [diff] [blame] | 205 | printk(BIOS_WARNING, "\n%02x: ", i); |
| 206 | printk(BIOS_WARNING, "%02x ", buf[i]); |
| 207 | } |
| 208 | printk(BIOS_WARNING, "\n"); |
Lee Leahy | e20a319 | 2017-03-09 16:21:34 -0800 | [diff] [blame] | 209 | } |
| 210 | return 0; |
Patrick Georgi | 0e3c59e | 2017-01-28 15:59:25 +0100 | [diff] [blame] | 211 | } |
| 212 | #endif |