| Mariusz Szafranski | a404133 | 2017-08-02 17:28:17 +0200 | [diff] [blame^] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2015 - 2017 Intel Corp. |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or modify |
| 7 | * it under the terms of the GNU General Public License as published by |
| 8 | * the Free Software Foundation; version 2 of the License. |
| 9 | * |
| 10 | * This program is distributed in the hope that it will be useful, |
| 11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 13 | * GNU General Public License for more details. |
| 14 | * |
| 15 | */ |
| 16 | |
| 17 | #include <console/console.h> |
| 18 | #include <device/device.h> |
| 19 | #include <device/pci.h> |
| 20 | #include <device/pci_ids.h> |
| 21 | #include <arch/io.h> |
| 22 | |
| 23 | #include <soc/pci_devs.h> |
| 24 | #include <soc/ramstage.h> |
| 25 | |
| 26 | static void usb_xhci_init(struct device *dev) |
| 27 | { |
| 28 | /* USB XHCI configuration is handled by the FSP */ |
| 29 | |
| 30 | printk(BIOS_NOTICE, "pch: %s\n", __func__); |
| 31 | |
| 32 | /* Set the value for PCI command register. */ |
| 33 | pci_write_config16(dev, PCI_COMMAND, |
| 34 | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY); |
| 35 | } |
| 36 | |
| 37 | static struct device_operations usb_xhci_ops = { |
| 38 | .read_resources = pci_dev_read_resources, |
| 39 | .set_resources = pci_dev_set_resources, |
| 40 | .enable_resources = pci_dev_enable_resources, |
| 41 | .init = usb_xhci_init, |
| 42 | .enable = pci_dev_enable_resources, |
| 43 | .scan_bus = 0, |
| 44 | .ops_pci = &soc_pci_ops, |
| 45 | }; |
| 46 | |
| 47 | static const struct pci_driver pch_usb_xhci __pci_driver = { |
| 48 | .ops = &usb_xhci_ops, |
| 49 | .vendor = PCI_VENDOR_ID_INTEL, |
| 50 | .device = XHCI_DEVID, |
| 51 | }; |