Mariusz Szafranski | a404133 | 2017-08-02 17:28:17 +0200 | [diff] [blame^] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2007-2009 coresystems GmbH |
| 5 | * Copyright (C) 2014 Google Inc. |
| 6 | * Copyright (C) 2015 - 2017 Intel Corporation. |
| 7 | * |
| 8 | * This program is free software; you can redistribute it and/or modify |
| 9 | * it under the terms of the GNU General Public License as published by |
| 10 | * the Free Software Foundation; version 2 of the License. |
| 11 | * |
| 12 | * This program is distributed in the hope that it will be useful, |
| 13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 15 | * GNU General Public License for more details. |
| 16 | */ |
| 17 | |
| 18 | #include <console/console.h> |
| 19 | #include <arch/acpi.h> |
| 20 | #include <arch/io.h> |
| 21 | #include <stdint.h> |
| 22 | #include <delay.h> |
| 23 | #include <device/device.h> |
| 24 | #include <device/pci.h> |
| 25 | #include <device/pci_ids.h> |
| 26 | #include <stdlib.h> |
| 27 | #include <string.h> |
| 28 | #include <cbmem.h> |
| 29 | #include <romstage_handoff.h> |
| 30 | #include <delay.h> |
| 31 | #include <timer.h> |
| 32 | |
| 33 | #include <soc/iomap.h> |
| 34 | #include <soc/pci_devs.h> |
| 35 | #include <soc/ramstage.h> |
| 36 | #include <soc/systemagent.h> |
| 37 | |
| 38 | #define _1ms 1 |
| 39 | #define WAITING_STEP 100 |
| 40 | |
| 41 | static int get_pcie_bar(device_t dev, unsigned int index, u32 *base, u32 *len) |
| 42 | { |
| 43 | u32 pciexbar_reg; |
| 44 | |
| 45 | *base = 0; |
| 46 | *len = 0; |
| 47 | |
| 48 | pciexbar_reg = pci_read_config32(dev, index); |
| 49 | |
| 50 | if (!(pciexbar_reg & (1 << 0))) |
| 51 | return 0; |
| 52 | |
| 53 | switch ((pciexbar_reg >> 1) & 3) { |
| 54 | case 0: /* 256MB */ |
| 55 | *base = pciexbar_reg & |
| 56 | ((1 << 31) | (1 << 30) | (1 << 29) | (1 << 28)); |
| 57 | *len = 256 * 1024 * 1024; |
| 58 | return 1; |
| 59 | case 1: /* 128M */ |
| 60 | *base = pciexbar_reg & ((1 << 31) | (1 << 30) | (1 << 29) | |
| 61 | (1 << 28) | (1 << 27)); |
| 62 | *len = 128 * 1024 * 1024; |
| 63 | return 1; |
| 64 | case 2: /* 64M */ |
| 65 | *base = pciexbar_reg & ((1 << 31) | (1 << 30) | (1 << 29) | |
| 66 | (1 << 28) | (1 << 27) | (1 << 26)); |
| 67 | *len = 64 * 1024 * 1024; |
| 68 | return 1; |
| 69 | } |
| 70 | |
| 71 | return 0; |
| 72 | } |
| 73 | |
| 74 | static int get_bar(device_t dev, unsigned int index, u32 *base, u32 *len) |
| 75 | { |
| 76 | u32 bar; |
| 77 | |
| 78 | bar = pci_read_config32(dev, index); |
| 79 | |
| 80 | /* If not enabled don't report it. */ |
| 81 | if (!(bar & 0x1)) |
| 82 | return 0; |
| 83 | |
| 84 | /* Knock down the enable bit. */ |
| 85 | *base = bar & ~1; |
| 86 | |
| 87 | return 1; |
| 88 | } |
| 89 | |
| 90 | struct fixed_mmio_descriptor { |
| 91 | unsigned int index; |
| 92 | u32 size; |
| 93 | int (*get_resource)(device_t dev, unsigned int index, u32 *base, |
| 94 | u32 *size); |
| 95 | const char *description; |
| 96 | }; |
| 97 | |
| 98 | struct fixed_mmio_descriptor mc_fixed_resources[] = { |
| 99 | {PCIEXBAR, 0, get_pcie_bar, "PCIEXBAR"}, |
| 100 | {MCHBAR, MCH_BASE_SIZE, get_bar, "MCHBAR"}, |
| 101 | }; |
| 102 | |
| 103 | /* |
| 104 | * Add all known fixed MMIO ranges that hang off the host bridge/memory |
| 105 | * controller device. |
| 106 | */ |
| 107 | static void mc_add_fixed_mmio_resources(device_t dev) |
| 108 | { |
| 109 | int i; |
| 110 | |
| 111 | for (i = 0; i < ARRAY_SIZE(mc_fixed_resources); i++) { |
| 112 | u32 base; |
| 113 | u32 size; |
| 114 | struct resource *resource; |
| 115 | unsigned int index; |
| 116 | |
| 117 | size = mc_fixed_resources[i].size; |
| 118 | index = mc_fixed_resources[i].index; |
| 119 | if (!mc_fixed_resources[i].get_resource(dev, index, &base, |
| 120 | &size)) |
| 121 | continue; |
| 122 | |
| 123 | resource = new_resource(dev, mc_fixed_resources[i].index); |
| 124 | resource->flags = IORESOURCE_MEM | IORESOURCE_FIXED | |
| 125 | IORESOURCE_STORED | IORESOURCE_RESERVE | |
| 126 | IORESOURCE_ASSIGNED; |
| 127 | resource->base = base; |
| 128 | resource->size = size; |
| 129 | printk(BIOS_DEBUG, "%s: Adding %s @ %x 0x%08lx-0x%08lx.\n", |
| 130 | __func__, mc_fixed_resources[i].description, index, |
| 131 | (unsigned long)base, (unsigned long)(base + size - 1)); |
| 132 | } |
| 133 | } |
| 134 | |
| 135 | struct map_entry { |
| 136 | int reg; |
| 137 | int is_64_bit; |
| 138 | int is_limit; |
| 139 | const char *description; |
| 140 | }; |
| 141 | |
| 142 | static void read_map_entry(device_t dev, struct map_entry *entry, |
| 143 | uint64_t *result) |
| 144 | { |
| 145 | uint64_t value; |
| 146 | uint64_t mask; |
| 147 | |
| 148 | /* All registers are on a 1MiB granularity. */ |
| 149 | mask = ((1ULL << 20) - 1); |
| 150 | mask = ~mask; |
| 151 | |
| 152 | value = 0; |
| 153 | |
| 154 | if (entry->is_64_bit) { |
| 155 | value = pci_read_config32(dev, entry->reg + 4); |
| 156 | value <<= 32; |
| 157 | } |
| 158 | |
| 159 | value |= (uint64_t)pci_read_config32(dev, entry->reg); |
| 160 | value &= mask; |
| 161 | |
| 162 | if (entry->is_limit) |
| 163 | value |= ~mask; |
| 164 | |
| 165 | *result = value; |
| 166 | } |
| 167 | |
| 168 | #define MAP_ENTRY(reg_, is_64_, is_limit_, desc_) \ |
| 169 | { \ |
| 170 | .reg = reg_, .is_64_bit = is_64_, .is_limit = is_limit_, \ |
| 171 | .description = desc_, \ |
| 172 | } |
| 173 | |
| 174 | #define MAP_ENTRY_BASE_64(reg_, desc_) MAP_ENTRY(reg_, 1, 0, desc_) |
| 175 | #define MAP_ENTRY_LIMIT_64(reg_, desc_) MAP_ENTRY(reg_, 1, 1, desc_) |
| 176 | #define MAP_ENTRY_BASE_32(reg_, desc_) MAP_ENTRY(reg_, 0, 0, desc_) |
| 177 | |
| 178 | enum { |
| 179 | TOUUD_REG, |
| 180 | TOLUD_REG, |
| 181 | TSEG_REG, |
| 182 | /* Must be last. */ |
| 183 | NUM_MAP_ENTRIES |
| 184 | }; |
| 185 | |
| 186 | static struct map_entry memory_map[NUM_MAP_ENTRIES] = { |
| 187 | [TOUUD_REG] = MAP_ENTRY_BASE_64(TOUUD, "TOUUD"), |
| 188 | [TOLUD_REG] = MAP_ENTRY_BASE_32(TOLUD, "TOLUD"), |
| 189 | [TSEG_REG] = MAP_ENTRY_BASE_32(TSEGMB, "TSEGMB"), |
| 190 | }; |
| 191 | |
| 192 | static void mc_read_map_entries(device_t dev, uint64_t *values) |
| 193 | { |
| 194 | int i; |
| 195 | for (i = 0; i < NUM_MAP_ENTRIES; i++) |
| 196 | read_map_entry(dev, &memory_map[i], &values[i]); |
| 197 | } |
| 198 | |
| 199 | static void mc_report_map_entries(device_t dev, uint64_t *values) |
| 200 | { |
| 201 | int i; |
| 202 | for (i = 0; i < NUM_MAP_ENTRIES; i++) { |
| 203 | printk(BIOS_DEBUG, "MC MAP: %s: 0x%llx\n", |
| 204 | memory_map[i].description, values[i]); |
| 205 | } |
| 206 | } |
| 207 | |
| 208 | static void mc_add_dram_resources(device_t dev) |
| 209 | { |
| 210 | unsigned long base_k, size_k; |
| 211 | unsigned long touud_k; |
| 212 | unsigned long index; |
| 213 | struct resource *resource; |
| 214 | uint64_t mc_values[NUM_MAP_ENTRIES]; |
| 215 | |
| 216 | /* Read in the MAP registers and report their values. */ |
| 217 | mc_read_map_entries(dev, &mc_values[0]); |
| 218 | mc_report_map_entries(dev, &mc_values[0]); |
| 219 | |
| 220 | /* |
| 221 | * These are the host memory ranges that should be added: |
| 222 | * - 0 -> 0xa0000: cacheable |
| 223 | * - 0xc0000 -> 0x100000 : reserved |
| 224 | * - 0x100000 -> top_of_ram : cacheable |
| 225 | * - top_of_ram -> TSEG: uncacheable |
| 226 | * - TESG -> TOLUD: cacheable with standard MTRRs and reserved |
| 227 | * - 4GiB -> TOUUD: cacheable |
| 228 | * |
| 229 | * The default SMRAM space is reserved so that the range doesn't |
| 230 | * have to be saved during S3 Resume. Once marked reserved the OS |
| 231 | * cannot use the memory. This is a bit of an odd place to reserve |
| 232 | * the region, but the CPU devices don't have dev_ops->read_resources() |
| 233 | * called on them. |
| 234 | * |
| 235 | * The range 0xa0000 -> 0xc0000 does not have any resources |
| 236 | * associated with it to handle legacy VGA memory. If this range |
| 237 | * is not omitted the mtrr code will setup the area as cacheable |
| 238 | * causing VGA access to not work. |
| 239 | * |
| 240 | * The TSEG region is mapped as cacheable so that one can perform |
| 241 | * SMRAM relocation faster. Once the SMRR is enabled the SMRR takes |
| 242 | * precedence over the existing MTRRs covering this region. |
| 243 | * |
| 244 | * It should be noted that cacheable entry types need to be added in |
| 245 | * order. The reason is that the current MTRR code assumes this and |
| 246 | * falls over itself if it isn't. |
| 247 | * |
| 248 | * The resource index starts low and should not meet or exceed |
| 249 | * PCI_BASE_ADDRESS_0. |
| 250 | */ |
| 251 | index = 0; |
| 252 | |
| 253 | /* 0 - > 0xa0000 */ |
| 254 | base_k = 0; |
| 255 | size_k = (0xa0000 >> 10) - base_k; |
| 256 | ram_resource(dev, index++, base_k, size_k); |
| 257 | |
| 258 | /* 0x100000 -> top_of_ram */ |
| 259 | base_k = 0x100000 >> 10; |
| 260 | size_k = (top_of_32bit_ram() >> 10) - base_k; |
| 261 | ram_resource(dev, index++, base_k, size_k); |
| 262 | |
| 263 | /* top_of_ram -> TSEG */ |
| 264 | resource = new_resource(dev, index++); |
| 265 | resource->base = top_of_32bit_ram(); |
| 266 | resource->size = mc_values[TSEG_REG] - resource->base; |
| 267 | resource->flags = IORESOURCE_MEM | IORESOURCE_FIXED | |
| 268 | IORESOURCE_STORED | IORESOURCE_RESERVE | |
| 269 | IORESOURCE_ASSIGNED; |
| 270 | |
| 271 | /* TSEG -> TOLUD */ |
| 272 | resource = new_resource(dev, index++); |
| 273 | resource->base = mc_values[TSEG_REG]; |
| 274 | resource->size = mc_values[TOLUD_REG] - resource->base; |
| 275 | resource->flags = IORESOURCE_MEM | IORESOURCE_FIXED | |
| 276 | IORESOURCE_STORED | IORESOURCE_RESERVE | |
| 277 | IORESOURCE_ASSIGNED | IORESOURCE_CACHEABLE; |
| 278 | printk(BIOS_DEBUG, |
| 279 | "SMM memory location: 0x%llx SMM memory size: 0x%llx\n", |
| 280 | resource->base, resource->size); |
| 281 | |
| 282 | /* 4GiB -> TOUUD */ |
| 283 | base_k = 4096 * 1024; /* 4GiB */ |
| 284 | touud_k = mc_values[TOUUD_REG] >> 10; |
| 285 | size_k = touud_k - base_k; |
| 286 | if (touud_k > base_k) |
| 287 | ram_resource(dev, index++, base_k, size_k); |
| 288 | |
| 289 | /* |
| 290 | * Reserve everything between A segment and 1MB: |
| 291 | * |
| 292 | * 0xa0000 - 0xbffff: legacy VGA |
| 293 | * 0xc0000 - 0xfffff: reserved RAM |
| 294 | */ |
| 295 | mmio_resource(dev, index++, (0xa0000 >> 10), (0xc0000 - 0xa0000) >> 10); |
| 296 | reserved_ram_resource(dev, index++, (0xc0000 >> 10), |
| 297 | (0x100000 - 0xc0000) >> 10); |
| 298 | } |
| 299 | |
| 300 | static void systemagent_read_resources(device_t dev) |
| 301 | { |
| 302 | /* Read standard PCI resources. */ |
| 303 | pci_dev_read_resources(dev); |
| 304 | |
| 305 | /* Add all fixed MMIO resources. */ |
| 306 | mc_add_fixed_mmio_resources(dev); |
| 307 | |
| 308 | /* Calculate and add DRAM resources. */ |
| 309 | mc_add_dram_resources(dev); |
| 310 | } |
| 311 | |
| 312 | static void systemagent_init(struct device *dev) |
| 313 | { |
| 314 | struct stopwatch sw; |
| 315 | void *bios_reset_cpl = |
| 316 | (void *)(DEFAULT_MCHBAR + MCH_BAR_BIOS_RESET_CPL); |
| 317 | uint32_t reg = read32(bios_reset_cpl); |
| 318 | |
| 319 | /* Stage0 BIOS Reset Complete (RST_CPL) */ |
| 320 | reg |= RST_CPL_BIT; |
| 321 | write32(bios_reset_cpl, reg); |
| 322 | |
| 323 | /* |
| 324 | * Poll for bit 8 in same reg (RST_CPL). |
| 325 | * We wait here till 1 ms for the bit to get set. |
| 326 | */ |
| 327 | stopwatch_init_msecs_expire(&sw, _1ms); |
| 328 | while (!(read32(bios_reset_cpl) & PCODE_INIT_DONE)) { |
| 329 | if (stopwatch_expired(&sw)) { |
| 330 | printk(BIOS_DEBUG, "Failed to set RST_CPL bit\n"); |
| 331 | return; |
| 332 | } |
| 333 | udelay(WAITING_STEP); |
| 334 | } |
| 335 | printk(BIOS_DEBUG, "Set BIOS_RESET_CPL\n"); |
| 336 | } |
| 337 | |
| 338 | static struct device_operations systemagent_ops = { |
| 339 | .read_resources = &systemagent_read_resources, |
| 340 | .set_resources = &pci_dev_set_resources, |
| 341 | .enable_resources = &pci_dev_enable_resources, |
| 342 | .init = &systemagent_init, |
| 343 | .ops_pci = &soc_pci_ops, |
| 344 | }; |
| 345 | |
| 346 | /* IDs for System Agent device of Intel Denverton SoC */ |
| 347 | static const unsigned short systemagent_ids[] = { |
| 348 | SA_DEVID, /* DVN System Agent */ |
| 349 | 0 |
| 350 | }; |
| 351 | |
| 352 | static const struct pci_driver systemagent_driver __pci_driver = { |
| 353 | .ops = &systemagent_ops, |
| 354 | .vendor = PCI_VENDOR_ID_INTEL, |
| 355 | .devices = systemagent_ids |
| 356 | }; |