| Mariusz Szafranski | a404133 | 2017-08-02 17:28:17 +0200 | [diff] [blame^] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2015 - 2017 Intel Corp. |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or modify |
| 7 | * it under the terms of the GNU General Public License as published by |
| 8 | * the Free Software Foundation; either version 2 of the License, or |
| 9 | * (at your option) any later version. |
| 10 | * |
| 11 | * This program is distributed in the hope that it will be useful, |
| 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 14 | * GNU General Public License for more details. |
| 15 | */ |
| 16 | |
| 17 | #include <device/pci_def.h> |
| 18 | #include <cpu/x86/mtrr.h> |
| 19 | #include <cpu/x86/cache.h> |
| 20 | #include <cpu/x86/cr.h> |
| 21 | #include <cpu/x86/post_code.h> |
| 22 | |
| 23 | #include <../../../arch/x86/walkcbfs.S> |
| 24 | |
| 25 | #define FSP_HDR_OFFSET 0x94 |
| 26 | |
| 27 | .extern temp_ram_init_params |
| 28 | |
| 29 | .global bootblock_pre_c_entry |
| 30 | bootblock_pre_c_entry: |
| 31 | |
| 32 | .global cache_as_ram |
| 33 | cache_as_ram: |
| 34 | post_code(0x2f) |
| 35 | |
| 36 | /* find fsp in cbfs */ |
| 37 | lea fsp_name, %esi |
| 38 | mov $1f, %esp |
| 39 | jmp walkcbfs_asm |
| 40 | 1: |
| 41 | cmp $0, %eax |
| 42 | jz .halt_forever |
| 43 | mov CBFS_FILE_OFFSET(%eax), %ebx |
| 44 | bswap %ebx |
| 45 | add %eax, %ebx |
| 46 | |
| 47 | addl $FSP_HDR_OFFSET, %ebx |
| 48 | |
| 49 | /* |
| 50 | * save mm2 into ebp, because TempRamInit API doesn't preserve |
| 51 | * mm2 register |
| 52 | */ |
| 53 | movd %mm2, %ebp |
| 54 | |
| 55 | /* |
| 56 | * ebx = FSP INFO HEADER |
| 57 | * Calculate entry into FSP |
| 58 | */ |
| 59 | movl 0x30(%ebx), %eax /* Load TempRamInitEntryOffset */ |
| 60 | addl 0x1c(%ebx), %eax /* add the FSP ImageBase */ |
| 61 | |
| 62 | /* |
| 63 | * Pass early init variables on a fake stack (no memory yet) |
| 64 | * as well as the return location |
| 65 | */ |
| 66 | leal CAR_init_stack, %esp |
| 67 | |
| 68 | /* call FSP binary to setup temporary stack */ |
| 69 | jmp *%eax |
| 70 | |
| 71 | /* |
| 72 | * If the TempRamInit API is successful, then when returning, the ECX and |
| 73 | * EDX registers will point to the temporary but writeable memory range |
| 74 | * available to the bootloader where ECX is the start and EDX is the end of |
| 75 | * the range i.e. [ECX,EDX). See Denverton_ns FSP Integration Guide for more |
| 76 | * information. |
| 77 | * |
| 78 | * Return Values: |
| 79 | * EAX | Return Status |
| 80 | * ECX | Temporary Memory Start |
| 81 | * EDX | Temporary Memory End |
| 82 | * EBX, EDI, ESI, EBP, MM0, MM1 | Preserved Through API Call |
| 83 | */ |
| 84 | |
| 85 | CAR_init_done: |
| 86 | cmp $0, %eax |
| 87 | jnz .halt_forever |
| 88 | |
| 89 | /* clear CAR_GLOBAL area as it is not shared */ |
| 90 | cld |
| 91 | xor %eax, %eax |
| 92 | movl $(_car_global_end), %ecx |
| 93 | movl $(_car_global_start), %edi |
| 94 | sub %edi, %ecx |
| 95 | shrl $2, %ecx |
| 96 | rep stosl |
| 97 | |
| 98 | /* Setup bootblock stack */ |
| 99 | movl $(_car_stack_end), %esp |
| 100 | |
| 101 | /* Restore the timestamp from bootblock_crt0.S (ebp:mm1) */ |
| 102 | push %ebp |
| 103 | movd %mm1, %eax |
| 104 | push %eax |
| 105 | |
| 106 | /* We can call into C functions now */ |
| 107 | call bootblock_c_entry |
| 108 | |
| 109 | /* Never reached */ |
| 110 | |
| 111 | .halt_forever: |
| 112 | post_code(POST_DEAD_CODE) |
| 113 | hlt |
| 114 | jmp .halt_forever |
| 115 | |
| 116 | .align 4 |
| 117 | CAR_init_stack: |
| 118 | .long CAR_init_done |
| 119 | .long temp_ram_init_params |
| 120 | |
| 121 | fsp_name: |
| 122 | .ascii "fspt.bin\x00" |