Kerry Sheh | a3f0607 | 2012-02-07 20:32:38 +0800 | [diff] [blame^] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2011 - 2012 Advanced Micro Devices, Inc. |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or modify |
| 7 | * it under the terms of the GNU General Public License as published by |
| 8 | * the Free Software Foundation; version 2 of the License. |
| 9 | * |
| 10 | * This program is distributed in the hope that it will be useful, |
| 11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 13 | * GNU General Public License for more details. |
| 14 | * |
| 15 | * You should have received a copy of the GNU General Public License |
| 16 | * along with this program; if not, write to the Free Software |
| 17 | * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA |
| 18 | */ |
| 19 | |
| 20 | |
| 21 | #include <reset.h> |
| 22 | #include <arch/io.h> /*inb, outb*/ |
| 23 | #include <arch/romcc_io.h> /*pci_read_config32, device_t, PCI_DEV*/ |
| 24 | |
| 25 | #define HT_INIT_CONTROL 0x6C |
| 26 | #define HTIC_BIOSR_Detect (1<<5) |
| 27 | |
| 28 | #if CONFIG_MAX_PHYSICAL_CPUS > 32 |
| 29 | #define NODE_PCI(x, fn) ((x<32)?(PCI_DEV(CONFIG_CBB,(CONFIG_CDB+x),fn)):(PCI_DEV((CONFIG_CBB-1),(CONFIG_CDB+x-32),fn))) |
| 30 | #else |
| 31 | #define NODE_PCI(x, fn) PCI_DEV(CONFIG_CBB,(CONFIG_CDB+x),fn) |
| 32 | #endif |
| 33 | |
| 34 | static inline void set_bios_reset(void) |
| 35 | { |
| 36 | u32 nodes; |
| 37 | u32 htic; |
| 38 | device_t dev; |
| 39 | int i; |
| 40 | |
| 41 | nodes = ((pci_read_config32(PCI_DEV(CONFIG_CBB, CONFIG_CDB, 0), 0x60) >> 4) & 7) + 1; |
| 42 | for(i = 0; i < nodes; i++) { |
| 43 | dev = NODE_PCI(i, 0); |
| 44 | htic = pci_read_config32(dev, HT_INIT_CONTROL); |
| 45 | htic &= ~HTIC_BIOSR_Detect; |
| 46 | pci_write_config32(dev, HT_INIT_CONTROL, htic); |
| 47 | } |
| 48 | } |
| 49 | |
| 50 | void hard_reset(void) |
| 51 | { |
| 52 | set_bios_reset(); |
| 53 | /* Try rebooting through port 0xcf9 */ |
| 54 | /* Actually it is not a real hard_reset --- it only reset coherent link table, but not reset link freq and width */ |
| 55 | outb((0 << 3) | (0 << 2) | (1 << 1), 0xcf9); |
| 56 | outb((0 << 3) | (1 << 2) | (1 << 1), 0xcf9); |
| 57 | } |
| 58 | |
| 59 | //SbReset(); |
| 60 | void soft_reset(void) |
| 61 | { |
| 62 | set_bios_reset(); |
| 63 | /* link reset */ |
| 64 | outb(0x06, 0x0cf9); |
| 65 | } |
| 66 | |