Angel Pons | f5627e8 | 2020-04-05 15:46:52 +0200 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
Lijian Zhao | 2f764f7 | 2017-07-14 11:09:10 -0700 | [diff] [blame] | 2 | |
| 3 | #ifndef _SOC_CHIP_H_ |
| 4 | #define _SOC_CHIP_H_ |
| 5 | |
Kyösti Mälkki | 32d47eb | 2019-09-28 00:00:30 +0300 | [diff] [blame] | 6 | #include <intelblocks/cfg.h> |
Chris Ching | b8dc63b | 2017-12-06 14:26:15 -0700 | [diff] [blame] | 7 | #include <drivers/i2c/designware/dw_i2c.h> |
Michael Niewöhner | c4f8fbd | 2020-12-19 14:11:32 +0100 | [diff] [blame] | 8 | #include <drivers/intel/gma/gma.h> |
Subrata Banik | 76a8f9e | 2019-05-15 21:23:18 +0530 | [diff] [blame] | 9 | #include <intelblocks/gpio.h> |
Lijian Zhao | 3211117 | 2017-08-16 11:40:03 -0700 | [diff] [blame] | 10 | #include <intelblocks/gspi.h> |
Jeremy Soller | 1af482c9 | 2019-02-20 16:39:55 -0700 | [diff] [blame] | 11 | #include <intelblocks/lpc_lib.h> |
Sumeet R Pawnikar | 309ccf7 | 2020-05-09 16:37:30 +0530 | [diff] [blame] | 12 | #include <intelblocks/power_limit.h> |
Lijian Zhao | 2f764f7 | 2017-07-14 11:09:10 -0700 | [diff] [blame] | 13 | #include <stdint.h> |
Lijian Zhao | 580bc41 | 2017-10-04 13:43:47 -0700 | [diff] [blame] | 14 | #include <soc/pch.h> |
Bora Guvendik | d2c6365 | 2017-09-19 14:04:37 -0700 | [diff] [blame] | 15 | #include <soc/pci_devs.h> |
Subrata Banik | 69b18f0 | 2018-11-06 16:59:56 +0530 | [diff] [blame] | 16 | #include <soc/pm.h> |
Lijian Zhao | 031020e | 2017-12-15 12:58:07 -0800 | [diff] [blame] | 17 | #include <soc/pmc.h> |
Jamie Chen | c004857da | 2020-01-15 11:17:21 +0800 | [diff] [blame] | 18 | #include <soc/sata.h> |
Lijian Zhao | 0823183 | 2017-09-05 18:16:21 -0700 | [diff] [blame] | 19 | #include <soc/serialio.h> |
Pratik Prajapati | 0f2f069 | 2017-08-17 16:47:34 -0700 | [diff] [blame] | 20 | #include <soc/usb.h> |
| 21 | #include <soc/vr_config.h> |
Julius Werner | cd49cce | 2019-03-05 16:53:33 -0800 | [diff] [blame] | 22 | #if CONFIG(SOC_INTEL_CANNONLAKE_PCH_H) |
praveen hodagatta pranesh | 521e48c | 2018-09-27 00:00:13 +0800 | [diff] [blame] | 23 | #include <soc/gpio_defs_cnp_h.h> |
| 24 | #else |
| 25 | #include <soc/gpio_defs.h> |
| 26 | #endif |
| 27 | |
Subrata Banik | 41483c9 | 2019-02-02 13:32:49 +0530 | [diff] [blame] | 28 | #define SOC_INTEL_CML_UART_DEV_MAX 3 |
Jamie Chen | c004857da | 2020-01-15 11:17:21 +0800 | [diff] [blame] | 29 | #define SOC_INTEL_CML_SATA_DEV_MAX 8 |
Subrata Banik | 41483c9 | 2019-02-02 13:32:49 +0530 | [diff] [blame] | 30 | |
Patrick Rudolph | 9de8c80 | 2020-05-18 12:03:52 +0200 | [diff] [blame] | 31 | enum chip_pl2_4_cfg { |
| 32 | baseline, |
| 33 | performance, |
| 34 | value_not_set /* vr_config internal use only */ |
| 35 | }; |
| 36 | |
Lijian Zhao | 2f764f7 | 2017-07-14 11:09:10 -0700 | [diff] [blame] | 37 | struct soc_intel_cannonlake_config { |
Subrata Banik | c4986eb | 2018-05-09 14:55:09 +0530 | [diff] [blame] | 38 | |
| 39 | /* Common struct containing soc config data required by common code */ |
| 40 | struct soc_intel_common_config common_soc_config; |
Lijian Zhao | b3dfcb8 | 2017-08-16 22:18:52 -0700 | [diff] [blame] | 41 | |
Sumeet R Pawnikar | 309ccf7 | 2020-05-09 16:37:30 +0530 | [diff] [blame] | 42 | /* Common struct containing power limits configuration information */ |
| 43 | struct soc_power_limits_config power_limits_config; |
| 44 | |
Lijian Zhao | b3dfcb8 | 2017-08-16 22:18:52 -0700 | [diff] [blame] | 45 | /* Gpio group routed to each dword of the GPE0 block. Values are |
| 46 | * of the form GPP_[A:G] or GPD. */ |
| 47 | uint8_t gpe0_dw0; /* GPE0_31_0 STS/EN */ |
| 48 | uint8_t gpe0_dw1; /* GPE0_63_32 STS/EN */ |
| 49 | uint8_t gpe0_dw2; /* GPE0_95_64 STS/EN */ |
| 50 | |
Pratik Prajapati | 0f2f069 | 2017-08-17 16:47:34 -0700 | [diff] [blame] | 51 | /* Generic IO decode ranges */ |
| 52 | uint32_t gen1_dec; |
| 53 | uint32_t gen2_dec; |
| 54 | uint32_t gen3_dec; |
| 55 | uint32_t gen4_dec; |
| 56 | |
Aamir Bohra | 4d9d3f1 | 2019-12-09 16:05:52 +0530 | [diff] [blame] | 57 | /* S0ix configuration */ |
| 58 | |
Pratik Prajapati | 0f2f069 | 2017-08-17 16:47:34 -0700 | [diff] [blame] | 59 | /* Enable S0iX support */ |
| 60 | int s0ix_enable; |
Aamir Bohra | 4d9d3f1 | 2019-12-09 16:05:52 +0530 | [diff] [blame] | 61 | /* Enable Audio DSP oscillator qualification for S0ix */ |
| 62 | uint8_t cppmvric2_adsposcdis; |
| 63 | |
Pratik Prajapati | 0f2f069 | 2017-08-17 16:47:34 -0700 | [diff] [blame] | 64 | /* Enable DPTF support */ |
| 65 | int dptf_enable; |
| 66 | |
| 67 | /* Deep SX enable for both AC and DC */ |
Lijian Zhao | ac87a98 | 2017-08-28 17:46:55 -0700 | [diff] [blame] | 68 | int deep_s3_enable_ac; |
| 69 | int deep_s3_enable_dc; |
| 70 | int deep_s5_enable_ac; |
| 71 | int deep_s5_enable_dc; |
Pratik Prajapati | 0f2f069 | 2017-08-17 16:47:34 -0700 | [diff] [blame] | 72 | |
| 73 | /* Deep Sx Configuration |
| 74 | * DSX_EN_WAKE_PIN - Enable WAKE# pin |
| 75 | * DSX_EN_LAN_WAKE_PIN - Enable LAN_WAKE# pin |
Furquan Shaikh | 02ce837 | 2017-12-03 21:53:52 -0800 | [diff] [blame] | 76 | * DSX_DIS_AC_PRESENT_PD - Disable pull-down on AC_PRESENT pin */ |
Pratik Prajapati | 0f2f069 | 2017-08-17 16:47:34 -0700 | [diff] [blame] | 77 | uint32_t deep_sx_config; |
| 78 | |
| 79 | /* TCC activation offset */ |
| 80 | uint32_t tcc_offset; |
| 81 | |
Pratik Prajapati | 0f2f069 | 2017-08-17 16:47:34 -0700 | [diff] [blame] | 82 | /* System Agent dynamic frequency support. Only effects ULX/ULT CPUs. |
Angel Pons | acb6e13 | 2019-01-25 20:05:38 +0100 | [diff] [blame] | 83 | * For CNL, options are as following |
| 84 | * When enabled, memory will be training at three different frequencies. |
Ronak Kanabar | dc666f5 | 2019-01-14 21:47:56 +0530 | [diff] [blame] | 85 | * 0:Disabled, 1:FixedLow, 2:FixedMid, 3:FixedHigh, 4:Enabled |
Subrata Banik | 41483c9 | 2019-02-02 13:32:49 +0530 | [diff] [blame] | 86 | * For WHL/CFL/CML options are as following |
Angel Pons | acb6e13 | 2019-01-25 20:05:38 +0100 | [diff] [blame] | 87 | * When enabled, memory will be training at two different frequencies. |
Ronak Kanabar | dc666f5 | 2019-01-14 21:47:56 +0530 | [diff] [blame] | 88 | * 0:Disabled, 1:FixedLow, 2:FixedHigh, 3:Enabled*/ |
Lijian Zhao | f5205a3 | 2018-03-12 12:13:15 -0700 | [diff] [blame] | 89 | enum { |
| 90 | SaGv_Disabled, |
| 91 | SaGv_FixedLow, |
Lijian Zhao | f5205a3 | 2018-03-12 12:13:15 -0700 | [diff] [blame] | 92 | SaGv_FixedHigh, |
| 93 | SaGv_Enabled, |
| 94 | } SaGv; |
| 95 | |
Pratik Prajapati | 0f2f069 | 2017-08-17 16:47:34 -0700 | [diff] [blame] | 96 | /* Rank Margin Tool. 1:Enable, 0:Disable */ |
| 97 | uint8_t RMT; |
| 98 | |
Pratik Prajapati | 0f2f069 | 2017-08-17 16:47:34 -0700 | [diff] [blame] | 99 | /* USB related */ |
| 100 | struct usb2_port_config usb2_ports[16]; |
| 101 | struct usb3_port_config usb3_ports[10]; |
Lijian Zhao | 2b074d9 | 2017-08-17 14:25:24 -0700 | [diff] [blame] | 102 | /* Wake Enable Bitmap for USB2 ports */ |
| 103 | uint16_t usb2_wake_enable_bitmap; |
| 104 | /* Wake Enable Bitmap for USB3 ports */ |
| 105 | uint16_t usb3_wake_enable_bitmap; |
Surendranath Gurivireddy | d367503 | 2019-10-31 15:45:39 -0700 | [diff] [blame] | 106 | /* USB2 PHY power gating */ |
| 107 | uint8_t PchUsb2PhySusPgDisable; |
Lijian Zhao | 2b074d9 | 2017-08-17 14:25:24 -0700 | [diff] [blame] | 108 | |
Pratik Prajapati | 0f2f069 | 2017-08-17 16:47:34 -0700 | [diff] [blame] | 109 | /* SATA related */ |
Lijian Zhao | ba82029 | 2018-12-06 15:05:19 -0800 | [diff] [blame] | 110 | enum { |
Felix Singer | 1e3b2ce | 2020-12-07 01:28:59 +0100 | [diff] [blame] | 111 | SATA_AHCI, |
| 112 | SATA_RAID, |
Lijian Zhao | ba82029 | 2018-12-06 15:05:19 -0800 | [diff] [blame] | 113 | } SataMode; |
Aamir Bohra | 87bb5f5 | 2019-09-10 08:39:14 +0530 | [diff] [blame] | 114 | |
| 115 | /* SATA devslp pad reset configuration */ |
| 116 | enum { |
| 117 | SataDevSlpResumeReset = 1, |
| 118 | SataDevSlpHostDeepReset = 3, |
| 119 | SataDevSlpPlatformReset = 5, |
| 120 | SataDevSlpDswReset = 7 |
| 121 | } SataDevSlpRstConfig; |
| 122 | |
Pratik Prajapati | 0f2f069 | 2017-08-17 16:47:34 -0700 | [diff] [blame] | 123 | uint8_t SataSalpSupport; |
| 124 | uint8_t SataPortsEnable[8]; |
| 125 | uint8_t SataPortsDevSlp[8]; |
Aamir Bohra | 87bb5f5 | 2019-09-10 08:39:14 +0530 | [diff] [blame] | 126 | uint8_t SataPortsDevSlpResetConfig[8]; |
Jonas Loeffelholz | d7238eb | 2020-06-25 13:50:58 +0200 | [diff] [blame] | 127 | uint8_t SataPortsHotPlug[8]; |
Pratik Prajapati | 0f2f069 | 2017-08-17 16:47:34 -0700 | [diff] [blame] | 128 | |
Krzysztof Sywula | 9bc9da9d | 2019-03-21 17:11:02 -0700 | [diff] [blame] | 129 | /* Enable/Disable SLP_S0 with GBE Support. 0: disable, 1: enable */ |
| 130 | uint8_t SlpS0WithGbeSupport; |
| 131 | /* SLP_S0 Voltage Margining Policy. 0: disable, 1: enable */ |
| 132 | uint8_t PchPmSlpS0VmRuntimeControl; |
| 133 | /* SLP_S0 Voltage Margining 0.70V Policy. 0: disable, 1: enable */ |
| 134 | uint8_t PchPmSlpS0Vm070VSupport; |
| 135 | /* SLP_S0 Voltage Margining 0.75V Policy. 0: disable, 1: enable */ |
| 136 | uint8_t PchPmSlpS0Vm075VSupport; |
| 137 | |
Pratik Prajapati | 0f2f069 | 2017-08-17 16:47:34 -0700 | [diff] [blame] | 138 | /* Audio related */ |
Pratik Prajapati | 0f2f069 | 2017-08-17 16:47:34 -0700 | [diff] [blame] | 139 | uint8_t PchHdaDspEnable; |
| 140 | |
| 141 | /* Enable/Disable HD Audio Link. Muxed with SSP0/SSP1/SNDW1 */ |
| 142 | uint8_t PchHdaAudioLinkHda; |
Aamir Bohra | b0b9905 | 2019-08-23 09:52:11 -0700 | [diff] [blame] | 143 | uint8_t PchHdaIDispCodecDisconnect; |
Lijian Zhao | 416ded8 | 2018-01-23 21:58:36 -0800 | [diff] [blame] | 144 | uint8_t PchHdaAudioLinkDmic0; |
| 145 | uint8_t PchHdaAudioLinkDmic1; |
| 146 | uint8_t PchHdaAudioLinkSsp0; |
| 147 | uint8_t PchHdaAudioLinkSsp1; |
| 148 | uint8_t PchHdaAudioLinkSsp2; |
| 149 | uint8_t PchHdaAudioLinkSndw1; |
| 150 | uint8_t PchHdaAudioLinkSndw2; |
| 151 | uint8_t PchHdaAudioLinkSndw3; |
| 152 | uint8_t PchHdaAudioLinkSndw4; |
Pratik Prajapati | 0f2f069 | 2017-08-17 16:47:34 -0700 | [diff] [blame] | 153 | |
Lijian Zhao | 580bc41 | 2017-10-04 13:43:47 -0700 | [diff] [blame] | 154 | /* PCIe Root Ports */ |
Pratik Prajapati | 0f2f069 | 2017-08-17 16:47:34 -0700 | [diff] [blame] | 155 | uint8_t PcieRpEnable[CONFIG_MAX_ROOT_PORTS]; |
Elyes HAOUAS | 79ccc69 | 2020-02-24 13:43:39 +0100 | [diff] [blame] | 156 | /* PCIe output clocks type to PCIe devices. |
Lijian Zhao | 580bc41 | 2017-10-04 13:43:47 -0700 | [diff] [blame] | 157 | * 0-23: PCH rootport, 0x70: LAN, 0x80: unspecified but in use, |
| 158 | * 0xFF: not used */ |
Lijian Zhao | d5d89c8 | 2019-05-07 14:05:33 -0700 | [diff] [blame] | 159 | uint8_t PcieClkSrcUsage[CONFIG_MAX_PCIE_CLOCKS]; |
Lijian Zhao | 580bc41 | 2017-10-04 13:43:47 -0700 | [diff] [blame] | 160 | /* PCIe ClkReq-to-ClkSrc mapping, number of clkreq signal assigned to |
| 161 | * clksrc. */ |
Lijian Zhao | d5d89c8 | 2019-05-07 14:05:33 -0700 | [diff] [blame] | 162 | uint8_t PcieClkSrcClkReq[CONFIG_MAX_PCIE_CLOCKS]; |
Lijian Zhao | 79152f3 | 2018-11-14 16:15:46 -0800 | [diff] [blame] | 163 | /* PCIe LTR(Latency Tolerance Reporting) mechanism */ |
| 164 | uint8_t PcieRpLtrEnable[CONFIG_MAX_ROOT_PORTS]; |
Nico Huber | 119ace0 | 2019-10-02 16:02:06 +0200 | [diff] [blame] | 165 | /* Implemented as slot or built-in? */ |
| 166 | uint8_t PcieRpSlotImplemented[CONFIG_MAX_ROOT_PORTS]; |
Jeremy Soller | 4185de5 | 2019-02-20 16:36:13 -0700 | [diff] [blame] | 167 | /* Enable/Disable HotPlug support for Root Port */ |
| 168 | uint8_t PcieRpHotPlug[CONFIG_MAX_ROOT_PORTS]; |
Pratik Prajapati | 0f2f069 | 2017-08-17 16:47:34 -0700 | [diff] [blame] | 169 | |
Christian Walter | 061cd78 | 2020-05-23 15:54:43 +0200 | [diff] [blame] | 170 | /* |
| 171 | * Enable/Disable AER (Advanced Error Reporting) for Root Port |
| 172 | * 0: Disable AER |
| 173 | * 1: Enable AER |
| 174 | */ |
| 175 | uint8_t PcieRpAdvancedErrorReporting[CONFIG_MAX_ROOT_PORTS]; |
| 176 | |
| 177 | /* PCIE RP ASPM, ASPM support for the root port */ |
| 178 | enum { |
| 179 | AspmDefault, |
| 180 | AspmDisabled, |
| 181 | AspmL0s, |
| 182 | AspmL1, |
| 183 | AspmL0sL1, |
| 184 | AspmAutoConfig, |
| 185 | } PcieRpAspm[CONFIG_MAX_ROOT_PORTS]; |
| 186 | |
| 187 | /* PCIE RP Max Payload, Max Payload Size supported */ |
| 188 | enum { |
| 189 | RpMaxPayload_128, |
| 190 | RpMaxPayload_256, |
| 191 | } PcieRpMaxPayload[CONFIG_MAX_ROOT_PORTS]; |
| 192 | |
Pratik Prajapati | 0f2f069 | 2017-08-17 16:47:34 -0700 | [diff] [blame] | 193 | /* eMMC and SD */ |
Pratik Prajapati | 0f2f069 | 2017-08-17 16:47:34 -0700 | [diff] [blame] | 194 | uint8_t ScsEmmcHs400Enabled; |
Lijian Zhao | 93fde11 | 2018-02-05 18:14:11 -0800 | [diff] [blame] | 195 | /* Need to update DLL setting to get Emmc running at HS400 speed */ |
| 196 | uint8_t EmmcHs400DllNeed; |
| 197 | /* 0-39: number of active delay for RX strobe, unit is 125 psec */ |
| 198 | uint8_t EmmcHs400RxStrobeDll1; |
| 199 | /* 0-78: number of active delay for TX data, unit is 125 psec */ |
| 200 | uint8_t EmmcHs400TxDataDll; |
Aamir Bohra | 662c61d | 2019-08-16 11:56:40 +0530 | [diff] [blame] | 201 | /* Enable/disable SD card write protect pin configuration on CML */ |
| 202 | uint8_t ScsSdCardWpPinEnabled; |
Pratik Prajapati | 0f2f069 | 2017-08-17 16:47:34 -0700 | [diff] [blame] | 203 | |
Pratik Prajapati | 0f2f069 | 2017-08-17 16:47:34 -0700 | [diff] [blame] | 204 | /* Heci related */ |
Christian Walter | e01054d | 2020-04-27 18:11:51 +0200 | [diff] [blame] | 205 | uint8_t DisableHeciRetry; |
Pratik Prajapati | 0f2f069 | 2017-08-17 16:47:34 -0700 | [diff] [blame] | 206 | |
| 207 | /* Gfx related */ |
Pratik Prajapati | 0f2f069 | 2017-08-17 16:47:34 -0700 | [diff] [blame] | 208 | uint8_t SkipExtGfxScan; |
| 209 | |
Pratik Prajapati | 0f2f069 | 2017-08-17 16:47:34 -0700 | [diff] [blame] | 210 | uint8_t Device4Enable; |
| 211 | |
Jamie Chen | 3ccae2b | 2019-12-20 17:28:38 +0800 | [diff] [blame] | 212 | /* CPU PL2/4 Config |
| 213 | * Performance: Maximum PLs for maximum performance. |
| 214 | * Baseline: Baseline PLs for balanced performance at lower power. |
| 215 | */ |
Patrick Rudolph | 9de8c80 | 2020-05-18 12:03:52 +0200 | [diff] [blame] | 216 | enum chip_pl2_4_cfg cpu_pl2_4_cfg; |
Jamie Chen | 3ccae2b | 2019-12-20 17:28:38 +0800 | [diff] [blame] | 217 | |
Pratik Prajapati | 0f2f069 | 2017-08-17 16:47:34 -0700 | [diff] [blame] | 218 | /* VrConfig Settings for 5 domains |
| 219 | * 0 = System Agent, 1 = IA Core, 2 = Ring, |
| 220 | * 3 = GT unsliced, 4 = GT sliced */ |
| 221 | struct vr_config domain_vr_config[NUM_VR_DOMAINS]; |
Sumeet Pawnikar | c896e92e | 2019-01-08 19:52:54 +0530 | [diff] [blame] | 222 | |
Edward O'Callaghan | fa043c4 | 2020-02-21 16:08:04 +1100 | [diff] [blame] | 223 | /* Enables support for Teton Glacier hybrid storage device */ |
| 224 | uint8_t TetonGlacierMode; |
| 225 | |
Pratik Prajapati | 0f2f069 | 2017-08-17 16:47:34 -0700 | [diff] [blame] | 226 | /* Enable/Disable EIST. 1b:Enabled, 0b:Disabled */ |
| 227 | uint8_t eist_enable; |
Lijian Zhao | a515849 | 2017-08-29 14:37:17 -0700 | [diff] [blame] | 228 | |
Subrata Banik | 2678cd6 | 2017-08-29 17:25:46 +0530 | [diff] [blame] | 229 | /* Enable C6 DRAM */ |
| 230 | uint8_t enable_c6dram; |
Michael Niewöhner | 7736bfc | 2019-10-22 23:05:06 +0200 | [diff] [blame] | 231 | |
Duncan Laurie | 55012d1 | 2019-01-07 12:06:07 -0800 | [diff] [blame] | 232 | /* |
| 233 | * SLP_S3 Minimum Assertion Width Policy |
| 234 | * 1 = 60us |
| 235 | * 2 = 1ms (default) |
| 236 | * 3 = 50ms |
| 237 | * 4 = 2s |
| 238 | */ |
| 239 | uint8_t PchPmSlpS3MinAssert; |
| 240 | |
| 241 | /* |
| 242 | * SLP_S4 Minimum Assertion Width Policy |
| 243 | * 1 = 1s |
| 244 | * 2 = 2s |
| 245 | * 3 = 3s |
| 246 | * 4 = 4s (default) |
| 247 | */ |
| 248 | uint8_t PchPmSlpS4MinAssert; |
| 249 | |
| 250 | /* |
| 251 | * SLP_SUS Minimum Assertion Width Policy |
| 252 | * 1 = 0ms |
| 253 | * 2 = 500ms |
| 254 | * 3 = 1s (default) |
| 255 | * 4 = 4s |
| 256 | */ |
| 257 | uint8_t PchPmSlpSusMinAssert; |
| 258 | |
| 259 | /* |
| 260 | * SLP_A Minimum Assertion Width Policy |
| 261 | * 1 = 0ms |
| 262 | * 2 = 4s |
| 263 | * 3 = 98ms (default) |
| 264 | * 4 = 2s |
| 265 | */ |
| 266 | uint8_t PchPmSlpAMinAssert; |
| 267 | |
Lijian Zhao | 0823183 | 2017-09-05 18:16:21 -0700 | [diff] [blame] | 268 | /* |
Sridhar Siricilla | e40b948 | 2020-06-17 00:38:20 +0530 | [diff] [blame] | 269 | * PCH PM Reset Power Cycle Duration |
| 270 | * 0 = 4s |
| 271 | * 1 = 1s |
| 272 | * 2 = 2s |
| 273 | * 3 = 3s |
| 274 | * 4 = 4s (default) |
| 275 | * |
| 276 | * NOTE: Duration programmed in the PchPmPwrCycDur should never be smaller than the |
| 277 | * stretch duration programmed in the following registers - |
| 278 | * - GEN_PMCON_A.SLP_S3_MIN_ASST_WDTH (PchPmSlpS3MinAssert) |
| 279 | * - GEN_PMCON_A.S4MAW (PchPmSlpS4MinAssert) |
| 280 | * - PM_CFG.SLP_A_MIN_ASST_WDTH (PchPmSlpAMinAssert) |
| 281 | * - PM_CFG.SLP_LAN_MIN_ASST_WDTH |
| 282 | */ |
| 283 | uint8_t PchPmPwrCycDur; |
| 284 | |
| 285 | /* |
Lijian Zhao | 0823183 | 2017-09-05 18:16:21 -0700 | [diff] [blame] | 286 | * SerialIO device mode selection: |
| 287 | * |
| 288 | * Device index: |
| 289 | * PchSerialIoIndexI2C0 |
| 290 | * PchSerialIoIndexI2C1 |
| 291 | * PchSerialIoIndexI2C2 |
| 292 | * PchSerialIoIndexI2C3 |
| 293 | * PchSerialIoIndexI2C4 |
| 294 | * PchSerialIoIndexI2C5 |
| 295 | * PchSerialIoIndexSPI0 |
| 296 | * PchSerialIoIndexSPI1 |
| 297 | * PchSerialIoIndexSPI2 |
| 298 | * PchSerialIoIndexUART0 |
| 299 | * PchSerialIoIndexUART1 |
| 300 | * PchSerialIoIndexUART2 |
| 301 | * |
| 302 | * Mode select: |
Subrata Banik | 41483c9 | 2019-02-02 13:32:49 +0530 | [diff] [blame] | 303 | * For Cannonlake PCH following values are supported: |
| 304 | * PchSerialIoNotInitialized |
Lijian Zhao | 0823183 | 2017-09-05 18:16:21 -0700 | [diff] [blame] | 305 | * PchSerialIoDisabled |
| 306 | * PchSerialIoPci |
| 307 | * PchSerialIoAcpi |
| 308 | * PchSerialIoHidden |
Subrata Banik | 41483c9 | 2019-02-02 13:32:49 +0530 | [diff] [blame] | 309 | * PchSerialIoMax |
| 310 | * |
| 311 | * For Cometlake following values are supported: |
| 312 | * PchSerialIoNotInitialized |
| 313 | * PchSerialIoDisabled, |
| 314 | * PchSerialIoPci, |
| 315 | * PchSerialIoHidden, |
| 316 | * PchSerialIoLegacyUart, |
| 317 | * PchSerialIoSkipInit, |
| 318 | * PchSerialIoMax |
| 319 | * |
| 320 | * NOTE: |
| 321 | * PchSerialIoNotInitialized is not an option provided by FSP, this |
| 322 | * option is default selected in case devicetree doesn't fill this param |
| 323 | * In case PchSerialIoNotInitialized is selected or an invalid value is |
| 324 | * provided from devicetree, coreboot will configure device into PCI |
| 325 | * mode by default. |
| 326 | * |
Lijian Zhao | 0823183 | 2017-09-05 18:16:21 -0700 | [diff] [blame] | 327 | */ |
| 328 | uint8_t SerialIoDevMode[PchSerialIoIndexMAX]; |
Bora Guvendik | d2c6365 | 2017-09-19 14:04:37 -0700 | [diff] [blame] | 329 | |
Jeremy Soller | 1af482c9 | 2019-02-20 16:39:55 -0700 | [diff] [blame] | 330 | enum serirq_mode serirq_mode; |
| 331 | |
Bora Guvendik | d2c6365 | 2017-09-19 14:04:37 -0700 | [diff] [blame] | 332 | /* GPIO SD card detect pin */ |
| 333 | unsigned int sdcard_cd_gpio; |
Lijian Zhao | 9bb684a | 2017-10-30 17:03:06 -0700 | [diff] [blame] | 334 | |
Lijian Zhao | 1b64ae1 | 2018-01-22 20:08:15 -0800 | [diff] [blame] | 335 | /* Enable Pch iSCLK */ |
| 336 | uint8_t pch_isclk; |
Lijian Zhao | 91c8e23 | 2018-03-12 18:05:53 -0700 | [diff] [blame] | 337 | |
Lijian Zhao | ae75400 | 2018-12-12 11:19:46 -0800 | [diff] [blame] | 338 | /* |
| 339 | * Acoustic Noise Mitigation |
| 340 | * 0b - Disable |
| 341 | * 1b - Enable noise mitigation |
| 342 | */ |
| 343 | uint8_t AcousticNoiseMitigation; |
| 344 | |
| 345 | /* |
| 346 | * Disable Fast Package C-state ramping |
| 347 | * Need to set AcousticNoiseMitigation = '1' first |
| 348 | * 0b - Enabled |
| 349 | * 1b - Disabled |
| 350 | */ |
| 351 | uint8_t FastPkgCRampDisableIa; |
| 352 | uint8_t FastPkgCRampDisableGt; |
| 353 | uint8_t FastPkgCRampDisableSa; |
| 354 | uint8_t FastPkgCRampDisableFivr; |
| 355 | |
| 356 | /* |
| 357 | * Adjust the VR slew rates |
| 358 | * Need to set AcousticNoiseMitigation = '1' first |
| 359 | * 000b - Fast/2 |
| 360 | * 001b - Fast/4 |
| 361 | * 010b - Fast/8 |
| 362 | * 011b - Fast/16 |
| 363 | */ |
| 364 | uint8_t SlowSlewRateForIa; |
| 365 | uint8_t SlowSlewRateForGt; |
| 366 | uint8_t SlowSlewRateForSa; |
| 367 | uint8_t SlowSlewRateForFivr; |
Lijian Zhao | 9bf1d8f | 2018-12-13 09:12:34 -0800 | [diff] [blame] | 368 | |
Lijian Zhao | 9bf1d8f | 2018-12-13 09:12:34 -0800 | [diff] [blame] | 369 | /* SATA Power Optimizer */ |
| 370 | uint8_t satapwroptimize; |
Krishna Prasad Bhat | caa85f2 | 2019-02-20 15:05:33 +0530 | [diff] [blame] | 371 | |
Jamie Chen | c004857da | 2020-01-15 11:17:21 +0800 | [diff] [blame] | 372 | /* SATA Gen3 Strength */ |
| 373 | struct sata_port_config sata_port[SOC_INTEL_CML_SATA_DEV_MAX]; |
| 374 | |
Krishna Prasad Bhat | caa85f2 | 2019-02-20 15:05:33 +0530 | [diff] [blame] | 375 | /* Enable or disable eDP device */ |
| 376 | uint8_t DdiPortEdp; |
| 377 | |
| 378 | /* Enable or disable HPD of DDI port B/C/D/F */ |
| 379 | uint8_t DdiPortBHpd; |
| 380 | uint8_t DdiPortCHpd; |
| 381 | uint8_t DdiPortDHpd; |
| 382 | uint8_t DdiPortFHpd; |
| 383 | |
| 384 | /* Enable or disable DDC of DDI port B/C/D/F */ |
| 385 | uint8_t DdiPortBDdc; |
| 386 | uint8_t DdiPortCDdc; |
| 387 | uint8_t DdiPortDDdc; |
| 388 | uint8_t DdiPortFDdc; |
Krishna Prasad Bhat | dffa8d0 | 2019-03-28 21:51:58 +0530 | [diff] [blame] | 389 | |
| 390 | /* Unlock all GPIO Pads */ |
| 391 | uint8_t PchUnlockGpioPads; |
Eric Lai | 43a3c51 | 2019-04-29 16:25:01 +0800 | [diff] [blame] | 392 | |
| 393 | /* Enable GBE wakeup */ |
| 394 | uint8_t LanWakeFromDeepSx; |
| 395 | uint8_t WolEnableOverride; |
Subrata Banik | 76a8f9e | 2019-05-15 21:23:18 +0530 | [diff] [blame] | 396 | |
Christian Walter | e6e9fa6 | 2020-05-06 09:18:37 +0200 | [diff] [blame] | 397 | #if !CONFIG(SOC_INTEL_COMETLAKE) |
| 398 | uint32_t VrPowerDeliveryDesign; |
| 399 | #endif |
| 400 | |
Subrata Banik | 76a8f9e | 2019-05-15 21:23:18 +0530 | [diff] [blame] | 401 | /* |
| 402 | * Override GPIO PM configuration: |
| 403 | * 0: Use FSP default GPIO PM program, |
| 404 | * 1: coreboot to override GPIO PM program |
| 405 | */ |
| 406 | uint8_t gpio_override_pm; |
| 407 | /* |
| 408 | * GPIO PM configuration: 0 to disable, 1 to enable power gating |
| 409 | * Bit 6-7: Reserved |
| 410 | * Bit 5: MISCCFG_GPSIDEDPCGEN |
| 411 | * Bit 4: MISCCFG_GPRCOMPCDLCGEN |
| 412 | * Bit 3: MISCCFG_GPRTCDLCGEN |
| 413 | * Bit 2: MISCCFG_GSXLCGEN |
| 414 | * Bit 1: MISCCFG_GPDPCGEN |
| 415 | * Bit 0: MISCCFG_GPDLCGEN |
| 416 | */ |
| 417 | uint8_t gpio_pm[TOTAL_GPIO_COMM]; |
Subrata Banik | e1470ea | 2019-11-18 14:08:08 +0530 | [diff] [blame] | 418 | |
| 419 | /* |
| 420 | * Override CPU flex ratio value: |
| 421 | * CPU ratio value controls the maximum processor non-turbo ratio. |
| 422 | * Valid Range 0 to 63. |
| 423 | * |
| 424 | * In general descriptor provides option to set default cpu flex ratio. |
| 425 | * Default cpu flex ratio is 0 ensures booting with non-turbo max frequency. |
| 426 | * Thats the reason FSP skips cpu_ratio override if cpu_ratio is 0. |
| 427 | * |
| 428 | * Only override CPU flex ratio if don't want to boot with non-turbo max. |
| 429 | */ |
| 430 | uint8_t cpu_ratio_override; |
Michael Niewöhner | c4f8fbd | 2020-12-19 14:11:32 +0100 | [diff] [blame] | 431 | |
| 432 | struct i915_gpu_panel_config panel_cfg; |
| 433 | |
| 434 | struct i915_gpu_controller_info gfx; |
Patrick Rudolph | e9b0830 | 2021-02-16 11:52:38 +0100 | [diff] [blame] | 435 | |
| 436 | /* Disable CPU Turbo in IA32_MISC_ENABLE */ |
| 437 | bool cpu_turbo_disable; |
Lijian Zhao | 2f764f7 | 2017-07-14 11:09:10 -0700 | [diff] [blame] | 438 | }; |
| 439 | |
| 440 | typedef struct soc_intel_cannonlake_config config_t; |
| 441 | |
| 442 | #endif |