Angel Pons | d28443e | 2020-04-05 13:22:44 +0200 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
Matt DeVillier | c12e5ae | 2016-11-27 02:19:02 -0600 | [diff] [blame] | 2 | |
Matt DeVillier | c12e5ae | 2016-11-27 02:19:02 -0600 | [diff] [blame] | 3 | #include <string.h> |
| 4 | #include <cbfs.h> |
| 5 | #include <console/console.h> |
| 6 | #include <cpu/intel/haswell/haswell.h> |
| 7 | #include "ec/google/chromeec/ec.h" |
| 8 | #include <northbridge/intel/haswell/haswell.h> |
| 9 | #include <northbridge/intel/haswell/raminit.h> |
| 10 | #include <southbridge/intel/lynxpoint/pch.h> |
| 11 | #include <southbridge/intel/lynxpoint/lp_gpio.h> |
Matt DeVillier | c12e5ae | 2016-11-27 02:19:02 -0600 | [diff] [blame] | 12 | #include "../../variant.h" |
| 13 | |
Matt DeVillier | c12e5ae | 2016-11-27 02:19:02 -0600 | [diff] [blame] | 14 | /* Copy SPD data for on-board memory */ |
Angel Pons | 6eea191 | 2020-07-03 14:14:30 +0200 | [diff] [blame] | 15 | void copy_spd(struct pei_data *peid) |
Matt DeVillier | c12e5ae | 2016-11-27 02:19:02 -0600 | [diff] [blame] | 16 | { |
| 17 | const int gpio_vector[] = {13, 9, 47, -1}; |
| 18 | int spd_index = get_gpios(gpio_vector); |
| 19 | char *spd_file; |
| 20 | size_t spd_file_len; |
Matt DeVillier | cadd7c7 | 2017-05-29 19:10:57 -0500 | [diff] [blame] | 21 | size_t spd_len = sizeof(peid->spd_data[0]); |
Matt DeVillier | c12e5ae | 2016-11-27 02:19:02 -0600 | [diff] [blame] | 22 | |
| 23 | printk(BIOS_DEBUG, "SPD index %d\n", spd_index); |
Julius Werner | 834b3ec | 2020-03-04 16:52:08 -0800 | [diff] [blame] | 24 | spd_file = cbfs_map("spd.bin", &spd_file_len); |
Matt DeVillier | c12e5ae | 2016-11-27 02:19:02 -0600 | [diff] [blame] | 25 | if (!spd_file) |
| 26 | die("SPD data not found."); |
| 27 | |
Matt DeVillier | cadd7c7 | 2017-05-29 19:10:57 -0500 | [diff] [blame] | 28 | if (spd_file_len < ((spd_index + 1) * spd_len)) { |
Matt DeVillier | c12e5ae | 2016-11-27 02:19:02 -0600 | [diff] [blame] | 29 | printk(BIOS_ERR, "SPD index override to 0 - old hardware?\n"); |
| 30 | spd_index = 0; |
| 31 | } |
| 32 | |
Matt DeVillier | cadd7c7 | 2017-05-29 19:10:57 -0500 | [diff] [blame] | 33 | if (spd_file_len < spd_len) |
Matt DeVillier | c12e5ae | 2016-11-27 02:19:02 -0600 | [diff] [blame] | 34 | die("Missing SPD data."); |
| 35 | |
Matt DeVillier | cadd7c7 | 2017-05-29 19:10:57 -0500 | [diff] [blame] | 36 | memcpy(peid->spd_data[0], spd_file + (spd_index * spd_len), spd_len); |
| 37 | |
Matt DeVillier | c12e5ae | 2016-11-27 02:19:02 -0600 | [diff] [blame] | 38 | /* Index 0-2, are 4GB config with both CH0 and CH1 |
| 39 | * Index 3-5, are 2GB config with CH0 only |
| 40 | */ |
| 41 | switch (spd_index) { |
Matt DeVillier | cadd7c7 | 2017-05-29 19:10:57 -0500 | [diff] [blame] | 42 | case 0: case 1: case 2: |
| 43 | memcpy(peid->spd_data[1], |
| 44 | spd_file + (spd_index * spd_len), spd_len); |
| 45 | break; |
Matt DeVillier | c12e5ae | 2016-11-27 02:19:02 -0600 | [diff] [blame] | 46 | case 3: case 4: case 5: |
| 47 | peid->dimm_channel1_disabled = 3; |
| 48 | } |
Matt DeVillier | c12e5ae | 2016-11-27 02:19:02 -0600 | [diff] [blame] | 49 | } |
| 50 | |
Angel Pons | a3c6ed0 | 2021-02-11 13:59:12 +0100 | [diff] [blame^] | 51 | const struct usb2_port_setting mainboard_usb2_ports[MAX_USB2_PORTS] = { |
| 52 | /* Length, Enable, OCn#, Location */ |
| 53 | { 0x0040, 1, 0, /* P0: Port A, CN10 */ |
| 54 | USB_PORT_BACK_PANEL }, |
| 55 | { 0x0040, 1, 2, /* P1: Port B, CN11 */ |
| 56 | USB_PORT_BACK_PANEL }, |
| 57 | { 0x0080, 1, USB_OC_PIN_SKIP, /* P2: CCD */ |
| 58 | USB_PORT_INTERNAL }, |
| 59 | { 0x0040, 1, USB_OC_PIN_SKIP, /* P3: BT */ |
| 60 | USB_PORT_MINI_PCIE }, |
| 61 | { 0x0040, 1, USB_OC_PIN_SKIP, /* P4: LTE */ |
| 62 | USB_PORT_INTERNAL }, |
| 63 | { 0x0000, 1, USB_OC_PIN_SKIP, /* P5: EMPTY */ |
| 64 | USB_PORT_SKIP }, |
| 65 | { 0x0040, 1, USB_OC_PIN_SKIP, /* P6: SD Card */ |
| 66 | USB_PORT_INTERNAL }, |
| 67 | { 0x0000, 0, USB_OC_PIN_SKIP, /* P7: EMPTY */ |
| 68 | USB_PORT_SKIP }, |
| 69 | }; |
Matt DeVillier | c12e5ae | 2016-11-27 02:19:02 -0600 | [diff] [blame] | 70 | |
Angel Pons | a3c6ed0 | 2021-02-11 13:59:12 +0100 | [diff] [blame^] | 71 | const struct usb3_port_setting mainboard_usb3_ports[MAX_USB3_PORTS] = { |
| 72 | /* Enable, OCn# */ |
| 73 | { 1, 0 }, /* P1; Port A, CN10 */ |
| 74 | { 1, 2 }, /* P2; Port B, CN11 */ |
| 75 | { 0, USB_OC_PIN_SKIP }, /* P3; */ |
| 76 | { 0, USB_OC_PIN_SKIP }, /* P4; */ |
| 77 | }; |