blob: b664c35ebf05d95a7a7816287500237946c853c8 [file] [log] [blame]
Ronald G. Minnich2a66d6b2013-03-28 17:01:43 -07001/*
2 * This file is part of the coreboot project.
3 *
4 * Copyright 2013 Google Inc.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; version 2 of the License.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
18 */
19
20#include <types.h>
21#include <string.h>
22#include <stdlib.h>
23#include <device/device.h>
24#include <device/device.h>
25#include <device/pci_def.h>
26#include <device/pci_ops.h>
27#include <console/console.h>
28#include <delay.h>
29#include <pc80/mc146818rtc.h>
30#include <arch/acpi.h>
31#include <arch/io.h>
32#include <arch/interrupt.h>
Ronald G. Minnich4f78b182013-04-17 16:57:30 -070033#include <boot/coreboot_tables.h>
Ronald G. Minnich2a66d6b2013-03-28 17:01:43 -070034#include "hda_verb.h"
35#include <smbios.h>
36#include <device/pci.h>
37#include <ec/google/chromeec/ec.h>
38#include <cbfs_core.h>
39
40#include <cpu/x86/tsc.h>
41#include <cpu/x86/cache.h>
42#include <cpu/x86/mtrr.h>
Ronald G. Minnich2a66d6b2013-03-28 17:01:43 -070043#include <cpu/x86/msr.h>
44#include <edid.h>
Ronald G. Minnich78c3e332013-04-24 09:50:56 -070045#include <device/i915.h>
46
47/* how many bytes do we need for the framebuffer?
48 * Well, this gets messy. To get an exact answer, we have
49 * to ask the panel, but we'd rather zero the memory
50 * and set up the gtt while the panel powers up. So,
51 * we take a reasonable guess, secure in the knowledge that the
52 * MRC has to overestimate the number of bytes used.
53 * 8 MiB is a very safe guess. There may be a better way later, but
54 * fact is, the initial framebuffer is only very temporary. And taking
55 * a little long is ok; this is done much faster than the AUX
56 * channel is ready for IO.
57 */
58#define FRAME_BUFFER_BYTES (8*MiB)
59/* how many 4096-byte pages do we need for the framebuffer?
60 * There are hard ways to get this, and easy ways:
61 * there are FRAME_BUFFER_BYTES/4096 pages, since pages are 4096
62 * on this chip (and in fact every Intel graphics chip we've seen).
63 */
64#define FRAME_BUFFER_PAGES (FRAME_BUFFER_BYTES/(4096))
Ronald G. Minnich2a66d6b2013-03-28 17:01:43 -070065
Ronald G. Minnich2a66d6b2013-03-28 17:01:43 -070066static int verbose = 0;
67
68static unsigned int *mmio;
69static unsigned int graphics;
70static unsigned short addrport;
71static unsigned short dataport;
72static unsigned int physbase;
73extern int oprom_is_loaded;
Ronald G. Minnich2a66d6b2013-03-28 17:01:43 -070074
75const u32 link_edid_data[] = {
76 0xffffff00, 0x00ffffff, 0x0379e430, 0x00000000,
77 0x04011500, 0x96121ba5, 0xa2d54f02, 0x26935259,
78 0x00545017, 0x01010000, 0x01010101, 0x01010101,
79 0x01010101, 0x6f6d0101, 0xa4a0a000, 0x20306031,
80 0xb510003a, 0x19000010, 0x00000000, 0x00000000,
81 0x00000000, 0x00000000, 0x00000000, 0x4c00fe00,
82 0x69442047, 0x616c7073, 0x20200a79, 0xfe000000,
83 0x31504c00, 0x45513932, 0x50532d31, 0x24003141,
84};
85
Ronald G. Minnich4f78b182013-04-17 16:57:30 -070086static int ioread = 0, iowrite = 0;
Ronald G. Minnich2a66d6b2013-03-28 17:01:43 -070087
88static char *regname(unsigned long addr)
89{
90 static char name[16];
Vladimir Serbinenkoa37383d2013-11-26 02:41:26 +010091 snprintf(name, sizeof (name), "0x%lx", addr);
Ronald G. Minnich2a66d6b2013-03-28 17:01:43 -070092 return name;
93}
94
Ronald G. Minnich4f78b182013-04-17 16:57:30 -070095unsigned long io_i915_read32(unsigned long addr)
Ronald G. Minnich2a66d6b2013-03-28 17:01:43 -070096{
97 unsigned long val;
98 outl(addr, addrport);
99 val = inl(dataport);
Ronald G. Minnich4f78b182013-04-17 16:57:30 -0700100 ioread += 2;
Ronald G. Minnich2a66d6b2013-03-28 17:01:43 -0700101 if (verbose & vio)printk(BIOS_SPEW, "%s: Got %08lx\n", regname(addr), val);
102 return val;
103}
104
Ronald G. Minnich4f78b182013-04-17 16:57:30 -0700105void io_i915_write32(unsigned long val, unsigned long addr)
Ronald G. Minnich2a66d6b2013-03-28 17:01:43 -0700106{
107 if (verbose & vio)printk(BIOS_SPEW, "%s: outl %08lx\n", regname(addr), val);
108 outl(addr, addrport);
109 outl(val, dataport);
Ronald G. Minnich4f78b182013-04-17 16:57:30 -0700110 iowrite += 2;
Ronald G. Minnich2a66d6b2013-03-28 17:01:43 -0700111}
112
Ronald G. Minnich4f78b182013-04-17 16:57:30 -0700113/* GTT is the Global Translation Table for the graphics pipeline.
114 * It is used to translate graphics addresses to physical
115 * memory addresses. As in the CPU, GTTs map 4K pages.
116 * The setgtt function adds a further bit of flexibility:
117 * it allows you to set a range (the first two parameters) to point
118 * to a physical address (third parameter);the physical address is
119 * incremented by a count (fourth parameter) for each GTT in the
120 * range.
121 * Why do it this way? For ultrafast startup,
122 * we can point all the GTT entries to point to one page,
123 * and set that page to 0s:
124 * memset(physbase, 0, 4096);
125 * setgtt(0, 4250, physbase, 0);
126 * this takes about 2 ms, and is a win because zeroing
127 * the page takes a up to 200 ms.
128 * This call sets the GTT to point to a linear range of pages
129 * starting at physbase.
130 */
Ronald G. Minnich2a66d6b2013-03-28 17:01:43 -0700131
Ronald G. Minnich2a66d6b2013-03-28 17:01:43 -0700132static void
133setgtt(int start, int end, unsigned long base, int inc)
134{
135 int i;
136
137 for(i = start; i < end; i++){
138 u32 word = base + i*inc;
Ronald G. Minnich4f78b182013-04-17 16:57:30 -0700139 io_i915_write32(word|1,(i*4)|1);
Ronald G. Minnich2a66d6b2013-03-28 17:01:43 -0700140 }
141}
142
143static unsigned long tickspermicrosecond = 1795;
144static unsigned long long globalstart;
145
146static unsigned long
147microseconds(unsigned long long start, unsigned long long end)
148{
149 unsigned long ret;
150 ret = ((end - start)/tickspermicrosecond);
151 return ret;
152}
153
154static unsigned long globalmicroseconds(void)
155{
156 return microseconds(globalstart, rdtscll());
157}
158
Ronald G. Minnich2a66d6b2013-03-28 17:01:43 -0700159static int i915_init_done = 0;
160
Ronald G. Minnichb2893a012013-04-23 10:59:11 -0700161int i915lightup(unsigned int physbase, unsigned int iobase, unsigned int mmio,
Ronald G. Minnich2a66d6b2013-03-28 17:01:43 -0700162 unsigned int gfx);
163
164int i915lightup(unsigned int pphysbase, unsigned int piobase,
165 unsigned int pmmio, unsigned int pgfx)
166{
Ronald G. Minnich4f78b182013-04-17 16:57:30 -0700167 int must_cycle_power = 0;
Ronald G. Minnich2a66d6b2013-03-28 17:01:43 -0700168
Ronald G. Minnich4f78b182013-04-17 16:57:30 -0700169 /* frame buffer pointer */
170 u32 *l;
171 int i;
172 unsigned long before_gtt, after_gtt;
173
Ronald G. Minnich2a66d6b2013-03-28 17:01:43 -0700174 mmio = (void *)pmmio;
175 addrport = piobase;
176 dataport = addrport + 4;
177 physbase = pphysbase;
178 graphics = pgfx;
179 printk(BIOS_SPEW,
180 "i915lightup: graphics %p mmio %p"
181 "addrport %04x physbase %08x\n",
182 (void *)graphics, mmio, addrport, physbase);
183 globalstart = rdtscll();
184
Ronald G. Minnich4f78b182013-04-17 16:57:30 -0700185 /* turn it on. The VBIOS does it this way, so we hope that's ok. */
Ronald G. Minnich2a66d6b2013-03-28 17:01:43 -0700186 verbose = 0;
Ronald G. Minnich4f78b182013-04-17 16:57:30 -0700187 io_i915_write32(0xabcd000f, PCH_PP_CONTROL);
188
189 /* the AUX channel needs a small amount of time to spin up.
190 * Rather than udelay, do some useful work:
191 * Zero out the frame buffer memory,
192 * and set the global translation table (GTT)
Ronald G. Minnich2a66d6b2013-03-28 17:01:43 -0700193 */
Ronald G. Minnich4f78b182013-04-17 16:57:30 -0700194 printk(BIOS_SPEW, "Set not-White (%08x) for %d pixels\n", 0xffffff,
195 FRAME_BUFFER_BYTES/sizeof(u32));
196 for(l = (u32 *)graphics, i = 0;
197 i < FRAME_BUFFER_BYTES/sizeof(u32); i++){
198 l[i] = 0x1122ff;
199 }
200 printk(BIOS_SPEW, "GTT: set %d pages starting at %p\n",
201 FRAME_BUFFER_PAGES, (void *)physbase);
202 before_gtt = globalmicroseconds();
Ronald G. Minnich2a66d6b2013-03-28 17:01:43 -0700203 setgtt(0, FRAME_BUFFER_PAGES, physbase, 4096);
Ronald G. Minnich4f78b182013-04-17 16:57:30 -0700204 after_gtt = globalmicroseconds();
205
206 /* The reset is basically harmless, and can be
207 * repeated by the VBIOS in any event.
208 */
209
210 graphics_register_reset(DPA_AUX_CH_CTL, DPA_AUX_CH_DATA1, verbose);
211
212 /* failures after this point can return without
213 * powering off the panel.
214 */
215
216 if (1)
217 goto fail;
218 /* failures after this point MUST power off the panel
219 * and wait 600 ms.
220 */
221
Ronald G. Minnich2a66d6b2013-03-28 17:01:43 -0700222 i915_init_done = 1;
223 oprom_is_loaded = 1;
Ronald G. Minnich4f78b182013-04-17 16:57:30 -0700224 return 1;
225
226fail:
227 printk(BIOS_SPEW, "Graphics could not be started;");
228 if (must_cycle_power){
229 printk(BIOS_SPEW, "Turn off power and wait ...");
230 io_i915_write32(0xabcd0000, PCH_PP_CONTROL);
231 udelay(600000);
232 }
233 printk(BIOS_SPEW, "Returning.\n");
Ronald G. Minnich2a66d6b2013-03-28 17:01:43 -0700234 return 0;
Ronald G. Minnich4f78b182013-04-17 16:57:30 -0700235
Ronald G. Minnich2a66d6b2013-03-28 17:01:43 -0700236}