Subrata Banik | b3ced6a | 2020-08-04 13:34:03 +0530 | [diff] [blame] | 1 | config SOC_INTEL_ALDERLAKE |
| 2 | bool |
| 3 | help |
| 4 | Intel Alderlake support |
| 5 | |
| 6 | if SOC_INTEL_ALDERLAKE |
| 7 | |
| 8 | config CPU_SPECIFIC_OPTIONS |
| 9 | def_bool y |
| 10 | select ARCH_BOOTBLOCK_X86_32 |
Subrata Banik | 292afef | 2020-09-09 13:34:18 +0530 | [diff] [blame] | 11 | select ARCH_ROMSTAGE_X86_32 |
| 12 | select ARCH_VERSTAGE_X86_32 |
Subrata Banik | b3ced6a | 2020-08-04 13:34:03 +0530 | [diff] [blame] | 13 | select BOOT_DEVICE_SPI_FLASH_RW_NOMMAP_EARLY if BOOT_DEVICE_SPI_FLASH |
| 14 | select BOOT_DEVICE_SUPPORTS_WRITES |
Subrata Banik | 292afef | 2020-09-09 13:34:18 +0530 | [diff] [blame] | 15 | select CACHE_MRC_SETTINGS |
| 16 | select CPU_INTEL_COMMON |
| 17 | select FSP_M_XIP |
Subrata Banik | b3ced6a | 2020-08-04 13:34:03 +0530 | [diff] [blame] | 18 | select INTEL_DESCRIPTOR_MODE_CAPABLE |
| 19 | select IDT_IN_EVERY_STAGE |
| 20 | select INTEL_CAR_NEM #TODO - Enable INTEL_CAR_NEM_ENHANCED |
Subrata Banik | 292afef | 2020-09-09 13:34:18 +0530 | [diff] [blame] | 21 | select MRC_SETTINGS_PROTECT |
Subrata Banik | b3ced6a | 2020-08-04 13:34:03 +0530 | [diff] [blame] | 22 | select MICROCODE_BLOB_UNDISCLOSED |
Subrata Banik | ee73594 | 2020-09-07 17:52:23 +0530 | [diff] [blame] | 23 | select PLATFORM_USES_FSP2_2 |
Subrata Banik | b3ced6a | 2020-08-04 13:34:03 +0530 | [diff] [blame] | 24 | select SOC_INTEL_COMMON |
| 25 | select SOC_INTEL_COMMON_BLOCK |
Subrata Banik | 292afef | 2020-09-09 13:34:18 +0530 | [diff] [blame] | 26 | select SOC_INTEL_COMMON_BLOCK_CHIP_CONFIG |
Subrata Banik | b3ced6a | 2020-08-04 13:34:03 +0530 | [diff] [blame] | 27 | select SOC_INTEL_COMMON_BLOCK_CPU |
| 28 | select SOC_INTEL_COMMON_BLOCK_GSPI_VERSION_2 |
| 29 | select SOC_INTEL_COMMON_BLOCK_SA |
| 30 | select SOC_INTEL_COMMON_PCH_BASE |
| 31 | select SOC_INTEL_COMMON_RESET |
| 32 | select SOC_INTEL_COMMON_BLOCK_CAR |
| 33 | select SSE2 |
| 34 | select SUPPORT_CPU_UCODE_IN_CBFS |
| 35 | select TSC_MONOTONIC_TIMER |
| 36 | select UDELAY_TSC |
Subrata Banik | ee73594 | 2020-09-07 17:52:23 +0530 | [diff] [blame] | 37 | select UDK_202005_BINDING |
Subrata Banik | b3ced6a | 2020-08-04 13:34:03 +0530 | [diff] [blame] | 38 | |
| 39 | config DCACHE_RAM_BASE |
| 40 | default 0xfef00000 |
| 41 | |
| 42 | config DCACHE_RAM_SIZE |
| 43 | default 0x80000 |
| 44 | help |
| 45 | The size of the cache-as-ram region required during bootblock |
| 46 | and/or romstage. |
| 47 | |
| 48 | config DCACHE_BSP_STACK_SIZE |
| 49 | hex |
| 50 | default 0x40400 |
| 51 | help |
| 52 | The amount of anticipated stack usage in CAR by bootblock and |
| 53 | other stages. In the case of FSP_USES_CB_STACK default value will be |
| 54 | sum of FSP-M stack requirement(256KiB) and CB romstage stack requirement |
| 55 | (~1KiB). |
| 56 | |
| 57 | config FSP_TEMP_RAM_SIZE |
| 58 | hex |
| 59 | default 0x20000 |
| 60 | help |
| 61 | The amount of anticipated heap usage in CAR by FSP. |
| 62 | Refer to Platform FSP integration guide document to know |
| 63 | the exact FSP requirement for Heap setup. |
| 64 | |
| 65 | config IFD_CHIPSET |
| 66 | string |
| 67 | default "adl" |
| 68 | |
| 69 | config IED_REGION_SIZE |
| 70 | hex |
| 71 | default 0x400000 |
| 72 | |
| 73 | config HEAP_SIZE |
| 74 | hex |
| 75 | default 0x10000 |
| 76 | |
| 77 | config PCR_BASE_ADDRESS |
| 78 | hex |
| 79 | default 0xfd000000 |
| 80 | help |
| 81 | This option allows you to select MMIO Base Address of sideband bus. |
| 82 | |
| 83 | config MMCONF_BASE_ADDRESS |
| 84 | hex |
| 85 | default 0xc0000000 |
| 86 | |
| 87 | config CPU_BCLK_MHZ |
| 88 | int |
| 89 | default 100 |
| 90 | |
| 91 | config SOC_INTEL_COMMON_BLOCK_GSPI_CLOCK_MHZ |
| 92 | int |
| 93 | default 120 |
| 94 | |
| 95 | config DRIVERS_I2C_DESIGNWARE_CLOCK_MHZ |
| 96 | int |
| 97 | default 133 |
| 98 | |
| 99 | config SOC_INTEL_COMMON_BLOCK_GSPI_MAX |
| 100 | int |
| 101 | default 7 |
| 102 | |
| 103 | config SOC_INTEL_I2C_DEV_MAX |
| 104 | int |
| 105 | default 6 |
| 106 | |
| 107 | config SOC_INTEL_UART_DEV_MAX |
| 108 | int |
| 109 | default 7 |
| 110 | |
| 111 | config CONSOLE_UART_BASE_ADDRESS |
| 112 | hex |
| 113 | default 0xfe032000 |
| 114 | depends on INTEL_LPSS_UART_FOR_CONSOLE |
| 115 | |
| 116 | # Clock divider parameters for 115200 baud rate |
| 117 | # Baudrate = (UART source clcok * M) /(N *16) |
| 118 | # ADL UART source clock: 120MHz |
| 119 | config SOC_INTEL_COMMON_LPSS_UART_CLK_M_VAL |
| 120 | hex |
| 121 | default 0x25a |
| 122 | |
| 123 | config SOC_INTEL_COMMON_LPSS_UART_CLK_N_VAL |
| 124 | hex |
| 125 | default 0x7fff |
| 126 | |
| 127 | config CHROMEOS |
| 128 | select CHROMEOS_RAMOOPS_DYNAMIC |
| 129 | |
Subrata Banik | 292afef | 2020-09-09 13:34:18 +0530 | [diff] [blame] | 130 | config VBOOT |
| 131 | select VBOOT_SEPARATE_VERSTAGE |
| 132 | select VBOOT_MUST_REQUEST_DISPLAY |
| 133 | select VBOOT_STARTS_IN_BOOTBLOCK |
| 134 | select VBOOT_VBNV_CMOS |
| 135 | select VBOOT_VBNV_CMOS_BACKUP_TO_FLASH |
| 136 | |
Subrata Banik | b3ced6a | 2020-08-04 13:34:03 +0530 | [diff] [blame] | 137 | config C_ENV_BOOTBLOCK_SIZE |
| 138 | hex |
| 139 | default 0xC000 |
| 140 | |
| 141 | config CBFS_SIZE |
| 142 | hex |
| 143 | default 0x200000 |
| 144 | |
| 145 | config PRERAM_CBMEM_CONSOLE_SIZE |
| 146 | hex |
| 147 | default 0x1400 |
Subrata Banik | ee73594 | 2020-09-07 17:52:23 +0530 | [diff] [blame] | 148 | config FSP_HEADER_PATH |
| 149 | string "Location of FSP headers" |
| 150 | default "src/vendorcode/intel/fsp/fsp2_0/alderlake/" |
| 151 | |
| 152 | config FSP_FD_PATH |
| 153 | string |
| 154 | depends on FSP_USE_REPO |
| 155 | default "3rdparty/fsp/AlderLakeFspBinPkg/Fsp.fd" |
Subrata Banik | 292afef | 2020-09-09 13:34:18 +0530 | [diff] [blame] | 156 | |
| 157 | config SOC_INTEL_ALDERLAKE_DEBUG_CONSENT |
| 158 | int "Debug Consent for ADL" |
| 159 | # USB DBC is more common for developers so make this default to 3 if |
| 160 | # SOC_INTEL_DEBUG_CONSENT=y |
| 161 | default 3 if SOC_INTEL_DEBUG_CONSENT |
| 162 | default 0 |
| 163 | help |
| 164 | This is to control debug interface on SOC. |
| 165 | Setting non-zero value will allow to use DBC or DCI to debug SOC. |
| 166 | PlatformDebugConsent in FspmUpd.h has the details. |
| 167 | |
| 168 | Desired platform debug type are |
| 169 | 0:Disabled, 1:Enabled (DCI OOB+[DbC]), 2:Enabled (DCI OOB), |
| 170 | 3:Enabled (USB3 DbC), 4:Enabled (XDP/MIPI60), 5:Enabled (USB2 DbC), |
| 171 | 6:Enable (2-wire DCI OOB), 7:Manual |
Subrata Banik | b3ced6a | 2020-08-04 13:34:03 +0530 | [diff] [blame] | 172 | endif |