Harsha B R | 500da54 | 2022-12-13 13:53:45 +0530 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-or-later */ |
| 2 | |
| 3 | #include <baseboard/gpio.h> |
Harsha B R | bd91aa7 | 2022-11-22 21:17:14 +0530 | [diff] [blame] | 4 | #include <baseboard/variants.h> |
| 5 | #include <console/console.h> |
| 6 | #include <ec/intel/board_id.h> |
| 7 | #include <soc/soc_info.h> |
Harsha B R | 500da54 | 2022-12-13 13:53:45 +0530 | [diff] [blame] | 8 | #include <vendorcode/google/chromeos/chromeos.h> |
| 9 | |
Harsha B R | a256bd6 | 2022-11-09 19:47:40 +0530 | [diff] [blame^] | 10 | /* Pad configuration in ramstage*/ |
| 11 | static const struct pad_config mtl_p_rvp_gpio_table[] = { |
| 12 | /* GPP_A */ |
| 13 | /* GPP_A00 : GPP_A00 ==> ESPI_SOC_IO0_R configured on reset, do not touch */ |
| 14 | /* GPP_A01 : GPP_A01 ==> ESPI_SOC_IO1_R configured on reset, do not touch */ |
| 15 | /* GPP_A02 : GPP_A02 ==> ESPI_SOC_IO2_R configured on reset, do not touch */ |
| 16 | /* GPP_A03 : GPP_A03 ==> ESPI_SOC_IO3_R configured on reset, do not touch */ |
| 17 | /* GPP_A04 : GPP_A04 ==> ESPI_SOC_CS0_L configured on reset, do not touch */ |
| 18 | /* GPP_A05 : GPP_A05 ==> ESPI_SOC_CLK_R configured on reset, do not touch */ |
| 19 | /* GPP_A06 : GPP_A06 ==> ESPI_SOC_RESET_L configured on reset, do not touch */ |
| 20 | /* GPP_A11: PEG_SLOT_DGPU_SEL_N */ |
| 21 | PAD_CFG_GPO(GPP_A11, 1, DEEP), |
| 22 | /* GPP_A12: WIFI_WAKE_N */ |
| 23 | PAD_CFG_GPI_SCI(GPP_A12, NONE, DEEP, LEVEL, INVERT), |
| 24 | /* GPP_A13: M2_SSD2_RST_N */ |
| 25 | PAD_CFG_GPO(GPP_A13, 1, DEEP), |
| 26 | /* GPP_A14: M2_CPU_SSD4_RESET_N */ |
| 27 | PAD_CFG_GPO(GPP_A14, 1, DEEP), |
| 28 | |
| 29 | /* WWAN: GPP_A15: M.2_WWAN_RST_N */ |
| 30 | PAD_CFG_GPO(GPP_A15, 1, DEEP), |
| 31 | |
| 32 | /* GPP_A16: NC */ |
| 33 | PAD_NC(GPP_A16, NONE), |
| 34 | /* Camera: GPP_A17: CRD2_PWREN */ |
| 35 | PAD_CFG_GPO(GPP_A17, 1, DEEP), |
| 36 | /* GPP_A18: X1_PCIE_SLOT3_PWR_EN */ |
| 37 | PAD_CFG_GPO(GPP_A18, 1, DEEP), |
| 38 | /* GPP_A19: X1_DT_PCIE_RST_N */ |
| 39 | PAD_CFG_GPO(GPP_A19, 1, DEEP), |
| 40 | /* GPP_A20: M2_CPU_SSD3_RESET_N */ |
| 41 | PAD_CFG_GPO(GPP_A20, 1, DEEP), |
| 42 | /* GPP_A21: I2C_PMC_PD_INT_N */ |
| 43 | PAD_CFG_NF(GPP_A21, NONE, DEEP, NF1), |
| 44 | |
| 45 | /* GPP_B */ |
| 46 | /* GPP_B00: TCH_PAD_INT_N */ |
| 47 | PAD_CFG_GPI_APIC(GPP_B00, NONE, DEEP, EDGE_SINGLE, INVERT), |
| 48 | /* GPP_B01: CRD_CAM_STROBE */ |
| 49 | PAD_CFG_GPO(GPP_B01, 0, DEEP), |
| 50 | /* GPP_B02: ISH_I2C0_SDA_ISH_I3C0_SDA_MCF_CRD */ |
| 51 | PAD_CFG_NF(GPP_B02, NONE, DEEP, NF3), |
| 52 | /* GPP_B03: ISH_I2C0_SCL_ISH_I3C0_SCL_MCF_CRD */ |
| 53 | PAD_CFG_NF(GPP_B03, NONE, DEEP, NF3), |
| 54 | /* GPP_B04: ISH_INT_GP4_MCF */ |
| 55 | PAD_CFG_NF(GPP_B04, NONE, DEEP, NF4), |
| 56 | /* ISH: GPP_B5: ISH_GP_0_SNSR_HDR */ |
| 57 | PAD_CFG_NF(GPP_B05, NONE, DEEP, NF4), |
| 58 | /* GPP_B06: ISH_GP_1_SNSR_HDR */ |
| 59 | PAD_CFG_NF(GPP_B06, NONE, DEEP, NF4), |
| 60 | /* GPP_B7: ISH_GP_2_SNSR_HDR */ |
| 61 | PAD_CFG_NF(GPP_B07, NONE, DEEP, NF4), |
| 62 | /* GPP_B8: ISH_GP_3_SNSR_HDR */ |
| 63 | PAD_CFG_NF(GPP_B08, NONE, DEEP, NF4), |
| 64 | /* GPP_B09: PEG_SLOT_RST_N */ |
| 65 | PAD_CFG_GPO(GPP_B09, 1, DEEP), |
| 66 | /* GPP_B10: TCP1_DP_HPD */ |
| 67 | PAD_CFG_NF(GPP_B10, NONE, DEEP, NF2), |
| 68 | /* GPP_B11: HDMI_HPD_CONN */ |
| 69 | PAD_CFG_NF(GPP_B11, NONE, DEEP, NF2), |
| 70 | /* GPP_B12: PM_SLP_S0_N */ |
| 71 | PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1), |
| 72 | /* GPP_B13: PLT_RST_N */ |
| 73 | PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1), |
| 74 | /* GPP_B14: TCP3_DP2_RD_HPD_OUT */ |
| 75 | PAD_CFG_NF(GPP_B14, NONE, DEEP, NF2), |
| 76 | /* GPP_B15: M.2_CPU_SSD3_PWREN */ |
| 77 | PAD_CFG_GPO(GPP_B15, 1, DEEP), |
| 78 | /* GPP_B16: DDIB_DP_CON_HPD */ |
| 79 | PAD_CFG_NF(GPP_B16, NONE, DEEP, NF2), |
| 80 | /* GPP_B18: BT_RF_KILL_N */ |
| 81 | PAD_CFG_GPO(GPP_B18, 1, DEEP), |
| 82 | /* GPP_B19: WIFI_RF_KILL_N */ |
| 83 | PAD_CFG_GPO(GPP_B19, 1, DEEP), |
| 84 | /* GPP_B20: PEG_RTD3_COLD_MOD */ |
| 85 | PAD_CFG_GPO(GPP_B20, 1, DEEP), |
| 86 | /* GPP_B21: TCP_RETIMER_FORCE_PWR */ |
| 87 | PAD_CFG_GPO(GPP_B21, 0, DEEP), |
| 88 | /* GPP_B22: ISH_GP_5_SNSR_HDR */ |
| 89 | PAD_CFG_NF(GPP_B22, NONE, DEEP, NF4), |
| 90 | /* GPP_B23: ISH_GP_6_SNSR_HDR */ |
| 91 | PAD_CFG_NF(GPP_B23, NONE, DEEP, NF4), |
| 92 | |
| 93 | /* GPP_C */ |
| 94 | /* GPP_C2: X1_PCIE_SLOT3_WAKE_N */ |
| 95 | PAD_CFG_GPI_SCI(GPP_C02, NONE, DEEP, LEVEL, INVERT), |
| 96 | /* GPP_C3: TCP_SMBUS_SCL_R */ |
| 97 | PAD_CFG_NF(GPP_C03, NONE, DEEP, NF1), |
| 98 | /* GPP_C4: TCP_SMBUS_SDA_R */ |
| 99 | PAD_CFG_NF(GPP_C04, NONE, DEEP, NF1), |
| 100 | /* WWAN: GPP_C5: M.2_WWAN_PERST_GPIO_N */ |
| 101 | PAD_CFG_GPO(GPP_C05, 1, DEEP), |
| 102 | /* GPP_C6: SML1CLK */ |
| 103 | PAD_CFG_NF(GPP_C06, NONE, DEEP, NF1), |
| 104 | /* GPP_C7: SML1DATA */ |
| 105 | PAD_CFG_NF(GPP_C07, NONE, DEEP, NF1), |
| 106 | /* Camera: GPP_C8: CRD1_PWREN_MCF_IRQ */ |
| 107 | PAD_CFG_GPO(GPP_C08, 1, DEEP), |
| 108 | /* SRCCLKREQ: GPP_C9: SRCCLKREQ0_M.2_SSD1_GEN3_N */ |
| 109 | PAD_CFG_NF(GPP_C09, NONE, DEEP, NF1), |
| 110 | /* SRCCLKREQ: GPP_C10: SRCCLKREQ1_M.2_WWAN_N */ |
| 111 | PAD_CFG_NF(GPP_C10, NONE, DEEP, NF1), |
| 112 | /* SRCCLKREQ: GPP_C11: SRCCLKREQ2_LAN_N */ |
| 113 | PAD_CFG_NF(GPP_C11, NONE, DEEP, NF1), |
| 114 | /* SRCCLKREQ: GPP_C12: SRCCLKREQ3_GEN4_X1_DT_SLOT3_N */ |
| 115 | PAD_CFG_NF(GPP_C12, NONE, DEEP, NF1), |
| 116 | /* SRCCLKREQ: GPP_C13: SRCCLKREQ4_GEN4_M2_PCH_SSD2_N */ |
| 117 | PAD_CFG_NF(GPP_C13, NONE, DEEP, NF1), |
| 118 | /* GPP_C14: NC */ |
| 119 | PAD_NC(GPP_C14, NONE), |
| 120 | /* GPP_C15: PEG_SLOT_DGPU_PWR_OK */ |
| 121 | PAD_CFG_GPI(GPP_C15, NONE, DEEP), |
| 122 | /* GPP_C16: TBT_LSX0_TXD */ |
| 123 | PAD_CFG_NF(GPP_C16, NONE, DEEP, NF1), |
| 124 | /* GPP_C17: TBT_LSX0_RXD */ |
| 125 | PAD_CFG_NF(GPP_C17, NONE, DEEP, NF1), |
| 126 | /* GPP_C18: TBT_LSX1_TXD */ |
| 127 | PAD_CFG_NF(GPP_C18, NONE, DEEP, NF1), |
| 128 | /* GPP_C19: TBT_LSX1_RXD */ |
| 129 | PAD_CFG_NF(GPP_C19, NONE, DEEP, NF1), |
| 130 | /* GPP_C20: TBT_LSX2_TXD */ |
| 131 | PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1), |
| 132 | /* GPP_C21: TBT_LSX2_RXD */ |
| 133 | PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1), |
| 134 | /* GPP_C22: TBT_LSX3_TXD */ |
| 135 | PAD_CFG_NF(GPP_C22, NONE, DEEP, NF1), |
| 136 | /* GPP_C23: TBT_LSX3_RXD */ |
| 137 | PAD_CFG_NF(GPP_C23, NONE, DEEP, NF1), |
| 138 | |
| 139 | /* GPP_D */ |
| 140 | /* GPP_D00: IMGCLKOUT_1 */ |
| 141 | PAD_CFG_NF(GPP_D00, NONE, DEEP, NF1), |
| 142 | /* GPP_D1: M2_PCH_SSD2_PWREN */ |
| 143 | PAD_CFG_GPO(GPP_D01, 1, DEEP), |
| 144 | /* GPP_D2: M2_SSD1_RST_N */ |
| 145 | PAD_CFG_GPO(GPP_D02, 1, DEEP), |
| 146 | /* GPP_D3: PEG_SLOT_DGPU_PWR_EN_N */ |
| 147 | PAD_CFG_GPO(GPP_D03, 0, DEEP), |
| 148 | /* Camera: GPP_D4: IMGCLKOUT0 */ |
| 149 | PAD_CFG_NF(GPP_D04, NONE, DEEP, NF1), |
| 150 | /* M.2: GPP_D5: M2_PCH_SSD1_PWREN */ |
| 151 | PAD_CFG_GPO(GPP_D05, 1, DEEP), |
| 152 | /* M.2: GPP_D6: M.2_CPU_SSD4_PWREN */ |
| 153 | PAD_CFG_GPO(GPP_D06, 1, DEEP), |
| 154 | /* GPP_D8: SAR_DPR_PCH */ |
| 155 | PAD_CFG_GPI_SCI(GPP_D08, NONE, DEEP, LEVEL, INVERT), |
| 156 | /* Audio: GPP_D9:GPP_D17 */ |
| 157 | /* SRCCLKREQ: GPP_D18: SRCCLKREQ6_X8_GEN5_DT_SLOT3_N */ |
| 158 | PAD_CFG_NF(GPP_D18, NONE, DEEP, NF1), |
| 159 | /* SRCCLKREQ: GPP_D19: SRCCLKREQ7_SSD4_N */ |
| 160 | PAD_CFG_NF(GPP_D19, NONE, DEEP, NF1), |
| 161 | /* SRCCLKREQ: GPP_D20: SRCCLKREQ8_SSD3_N */ |
| 162 | PAD_CFG_NF(GPP_D20, NONE, DEEP, NF1), |
| 163 | /* SRCCLKREQ: GPP_D21: SRCCLKREQ5_M.2_WLAN_CLKREQ5_N */ |
| 164 | PAD_CFG_NF(GPP_D21, NONE, DEEP, NF2), |
| 165 | /* GPP_D22: BPKI3C_SDA */ |
| 166 | PAD_CFG_NF(GPP_D22, NONE, DEEP, NF1), |
| 167 | /* GPP_D23: BPKI3C_SCL */ |
| 168 | PAD_CFG_NF(GPP_D23, NONE, DEEP, NF1), |
| 169 | |
| 170 | /* GPP_E */ |
| 171 | /* GPP_E0: M.2_SSD1_PEDET_R */ |
| 172 | PAD_CFG_NF(GPP_E00, NONE, DEEP, NF1), |
| 173 | /* GPP_E1: THC0_SPI1_IO_2_TCH_PNL1 */ |
| 174 | PAD_CFG_NF(GPP_E01, NONE, DEEP, NF2), |
| 175 | /* GPP_E2: THC0_SPI1_IO_3_TCH_PNL1 */ |
| 176 | PAD_CFG_NF(GPP_E02, NONE, DEEP, NF2), |
| 177 | /* GPP_E4: M2_SSD1_DEVSLP */ |
| 178 | PAD_CFG_NF(GPP_E04, NONE, DEEP, NF1), |
| 179 | /* GPP_E5: SATA_DIRECT_DEVSLP */ |
| 180 | PAD_CFG_NF(GPP_E05, NONE, DEEP, NF1), |
| 181 | /* GPP_E6: THC0_SPI1_RST_N_TCH_PNL1 */ |
| 182 | PAD_CFG_NF(GPP_E06, NONE, DEEP, NF2), |
| 183 | /* GPP_E8: CRD_PRIVACY_LED */ |
| 184 | PAD_CFG_GPO(GPP_E08, 1, DEEP), |
| 185 | /* GPP_E9: USB_CONN_TYPEA_12_TYPEC_01_FP_P7_P8_P9_P10_OC0_N */ |
| 186 | PAD_CFG_NF(GPP_E09, NONE, DEEP, NF1), |
| 187 | /* GPP_E10: THC0_SPI1_CS0_N_TCH_PNL1 */ |
| 188 | PAD_CFG_NF(GPP_E10, NONE, DEEP, NF2), |
| 189 | /* GPP_E11: THC0_SPI1_CLK_TCH_PNL1 */ |
| 190 | PAD_CFG_NF(GPP_E11, NONE, DEEP, NF2), |
| 191 | /* GPP_E12: THC0_SPI1_IO_1_I2C4_SDA_TCH_PNL1 */ |
| 192 | PAD_CFG_NF(GPP_E12, NONE, DEEP, NF2), |
| 193 | /* GPP_E13: THC0_SPI1_IO_0_I2C4_SCL_TCH_PNL1 */ |
| 194 | PAD_CFG_NF(GPP_E13, NONE, DEEP, NF2), |
| 195 | /* GPP_E14: DDIA_EDP_HPD */ |
| 196 | PAD_CFG_NF(GPP_E14, NONE, DEEP, NF1), |
| 197 | /* GPP_E15: PM_SLP_DRAM_N */ |
| 198 | PAD_CFG_NF(GPP_E15, NONE, DEEP, NF2), |
| 199 | /* GPP_E16: GPP_E16_BC_PROCHOT_N */ |
| 200 | PAD_CFG_NF(GPP_E16, NONE, DEEP, NF2), |
| 201 | /* GPP_E17: THC0_SPI1_INT_N_TCH_PNL1 */ |
| 202 | PAD_CFG_NF(GPP_E17, NONE, DEEP, NF2), |
| 203 | /* GPP_E22: GPP_E22_DNX_FORCE_RELOAD */ |
| 204 | PAD_CFG_NF(GPP_E22, NONE, DEEP, NF2), |
| 205 | |
| 206 | /* GPP_F */ |
| 207 | /* GPP_F0: M.2_CNV_BRI_DT_BT_UART2_RTS_N */ |
| 208 | PAD_CFG_NF(GPP_F00, NONE, DEEP, NF1), |
| 209 | /* GPP_F1: M.2_CNV_BRI_RSP_BT_UART2_RXD */ |
| 210 | PAD_CFG_NF(GPP_F01, NONE, DEEP, NF1), |
| 211 | /* GPP_F2: M.2_CNV_RGI_DT_BT_UART2_TXD */ |
| 212 | PAD_CFG_NF(GPP_F02, NONE, DEEP, NF1), |
| 213 | /* GPP_F3: M.2_CNV_RGI_RSP_BT_UART2_CTS_N */ |
| 214 | PAD_CFG_NF(GPP_F03, NONE, DEEP, NF1), |
| 215 | /* GPP_F4: CNV_RF_RESET_R_N */ |
| 216 | PAD_CFG_NF(GPP_F04, NONE, DEEP, NF1), |
| 217 | /* GPP_F5: CRF_CLKREQ */ |
| 218 | PAD_CFG_NF(GPP_F05, NONE, DEEP, NF3), |
| 219 | /* GPP_F6: WLAN_WWAN_COEX3 */ |
| 220 | PAD_CFG_GPI(GPP_F06, NONE, DEEP), |
| 221 | /* Camera: GPP_F7: IMGCLKOUT2 */ |
| 222 | PAD_CFG_NF(GPP_F07, NONE, DEEP, NF2), |
| 223 | /* GPP_F8: IMGCLKOUT_3 */ |
| 224 | PAD_CFG_NF(GPP_F08, NONE, DEEP, NF2), |
| 225 | /* GPP_F9: CODEC_INT_N */ |
| 226 | PAD_CFG_GPI_APIC(GPP_F09, NONE, DEEP, LEVEL, INVERT), |
| 227 | /* TPM: GPP_F11:GPP_F13, GPP_F17 */ |
| 228 | /* GPP_F14: THC1_SPI2_IO_2_TCH_PNL2 */ |
| 229 | PAD_CFG_NF(GPP_F14, NONE, DEEP, NF3), |
| 230 | /* GPP_F15: THC1_SPI2_IO_3_TCH_PNL2 */ |
| 231 | PAD_CFG_NF(GPP_F15, NONE, DEEP, NF3), |
| 232 | /* GPP_F16: THC1_SPI2_RST_N_TCH_PNL2 */ |
| 233 | PAD_CFG_NF(GPP_F16, NONE, DEEP, NF3), |
| 234 | /* GPP_F18: THC1_SPI2_INT_N_TCH_PNL2 */ |
| 235 | PAD_CFG_NF(GPP_F18, NONE, DEEP, NF3), |
| 236 | /* GPP_F19: X4_PCIE_SLOT2_WAKE_N_R */ |
| 237 | PAD_CFG_GPI_SCI(GPP_F19, NONE, DEEP, LEVEL, INVERT), |
| 238 | /* GPP_F20: PEG_SLOT_WAKE_R_N */ |
| 239 | PAD_CFG_GPI_SCI(GPP_F20, NONE, DEEP, LEVEL, INVERT), |
| 240 | /* GPP_F22: TCH_PNL2_PWR_EN */ |
| 241 | PAD_CFG_GPO(GPP_F22, 1, DEEP), |
| 242 | /* GPP_F23: TCH_PNL1_PWR_EN */ |
| 243 | PAD_CFG_GPO(GPP_F23, 1, DEEP), |
| 244 | |
| 245 | /* GPP_H */ |
| 246 | /* Camera: GPP_H0: GPP2_RST */ |
| 247 | PAD_CFG_GPO(GPP_H00, 1, DEEP), |
| 248 | /* GPP_H1: TCH_PAD_TCH_PNL2_LS_EN */ |
| 249 | PAD_CFG_GPO(GPP_H01, 1, DEEP), |
| 250 | /* GPP_H2: WLAN_RST_N */ |
| 251 | PAD_CFG_GPO(GPP_H02, 1, DEEP), |
| 252 | /* GPP_H4: CNV_MFUART2_RXD */ |
| 253 | PAD_CFG_NF(GPP_H04, NONE, DEEP, NF2), |
| 254 | /* GPP_H5: CNV_MFUART2_TXD */ |
| 255 | PAD_CFG_NF(GPP_H05, NONE, DEEP, NF2), |
| 256 | /* GPP_H6: I2C3_SDA_TCH_PAD */ |
| 257 | PAD_CFG_NF(GPP_H06, NONE, DEEP, NF1), |
| 258 | /* GPP_H7: I2C3_SCL_TCH_PAD */ |
| 259 | PAD_CFG_NF(GPP_H07, NONE, DEEP, NF1), |
| 260 | /* GPP_H13: CPU_C10_GATE_N_R */ |
| 261 | PAD_CFG_NF(GPP_H13, NONE, DEEP, NF1), |
| 262 | /* ISH: GPP_H14: ISH_I2C1_SDA */ |
| 263 | PAD_CFG_NF(GPP_H14, NONE, DEEP, NF3), |
| 264 | /* ISH: GPP_H15: ISH_I2C1_SCL */ |
| 265 | PAD_CFG_NF(GPP_H15, NONE, DEEP, NF3), |
| 266 | /* GPP_H16: DDPB_HDMI_CRLS_CTRLCLK */ |
| 267 | PAD_CFG_NF(GPP_H16, NONE, DEEP, NF1), |
| 268 | /* GPP_H17: DDPB_HDMI_CRLS_CTRLDATA */ |
| 269 | PAD_CFG_NF(GPP_H17, NONE, DEEP, NF1), |
| 270 | /* GPP_H19: I2C0_SDA_I3C0_SDA_CSI */ |
| 271 | PAD_CFG_NF(GPP_H19, NONE, DEEP, NF1), |
| 272 | /* GPP_H20: I2C0_SCL_I3C0_SCL_CSI */ |
| 273 | PAD_CFG_NF(GPP_H20, NONE, DEEP, NF1), |
| 274 | /* GPP_H21: I2C1_SDA_I3C1_SDA_CSI */ |
| 275 | PAD_CFG_NF(GPP_H21, NONE, DEEP, NF1), |
| 276 | /* GPP_H22: I2C1_SCL_I3C1_SCL_CSI */ |
| 277 | PAD_CFG_NF(GPP_H22, NONE, DEEP, NF1), |
| 278 | |
| 279 | /* GPP_V */ |
| 280 | /* GPP_V0: PM_BATLOW_N */ |
| 281 | PAD_CFG_NF(GPP_V00, NONE, DEEP, NF1), |
| 282 | /* GPP_V1: BC_ACOK_MCP */ |
| 283 | PAD_CFG_NF(GPP_V01, NONE, DEEP, NF1), |
| 284 | /* GPP_V2: LANWAKE_N_R */ |
| 285 | PAD_CFG_NF(GPP_V02, NONE, DEEP, NF1), |
| 286 | /* GPP_V3: PWRBTN_MCP_N */ |
| 287 | PAD_CFG_NF(GPP_V03, NONE, DEEP, NF1), |
| 288 | /* GPP_V4: PM_SLP_S3_N */ |
| 289 | PAD_CFG_NF(GPP_V04, NONE, DEEP, NF1), |
| 290 | /* GPP_V5: PM_SLP_S4_N */ |
| 291 | PAD_CFG_NF(GPP_V05, NONE, DEEP, NF1), |
| 292 | /* GPP_V6: PM_SLP_A_N */ |
| 293 | PAD_CFG_NF(GPP_V06, NONE, DEEP, NF1), |
| 294 | /* GPP_V8: SUS_CLK_MCF */ |
| 295 | PAD_CFG_NF(GPP_V08, NONE, DEEP, NF1), |
| 296 | /* GPP_V9: SLP_WLAN_N */ |
| 297 | PAD_CFG_NF(GPP_V09, NONE, DEEP, NF1), |
| 298 | /* GPP_V10: PM_SLP_S5_N */ |
| 299 | PAD_CFG_NF(GPP_V10, NONE, DEEP, NF1), |
| 300 | /* GPP_V11: LANPHYPC_R_N */ |
| 301 | PAD_CFG_NF(GPP_V11, NONE, DEEP, NF1), |
| 302 | /* GPP_V12: PM_SLP_LAN_N */ |
| 303 | PAD_CFG_NF(GPP_V12, NONE, DEEP, NF1), |
| 304 | /* GPP_V14: WAKE_N */ |
| 305 | PAD_CFG_NF(GPP_V14, NONE, DEEP, NF1), |
| 306 | /* GPP_V15: */ |
| 307 | PAD_CFG_GPO(GPP_V15, 1, DEEP), |
| 308 | /* GPP_V19: caterr_b */ |
| 309 | PAD_CFG_NF(GPP_V19, NONE, DEEP, NF1), |
| 310 | /* GPP_V20: H_PROCHOT_N */ |
| 311 | PAD_CFG_NF(GPP_V20, NONE, DEEP, NF1), |
| 312 | /* GPP_V21: thermtrip_b */ |
| 313 | PAD_CFG_NF(GPP_V21, NONE, DEEP, NF1), |
| 314 | /* GPP_V22: CRD1_CLK_EN */ |
| 315 | PAD_CFG_GPO(GPP_V22, 1, DEEP), |
| 316 | /* Camera: GPP_V23: CRD1_CAM1_RST_N */ |
| 317 | PAD_CFG_GPO(GPP_V23, 1, DEEP), |
| 318 | }; |
| 319 | |
Harsha B R | bd91aa7 | 2022-11-22 21:17:14 +0530 | [diff] [blame] | 320 | /* Early pad configuration in bootblock */ |
| 321 | static const struct pad_config mtl_p_rvp_early_gpio_table[] = { |
| 322 | /* Audio */ |
| 323 | PAD_NC(GPP_D14, NONE), /* M.2_BT_I2S2_PCMCLK/NONE */ |
| 324 | PAD_NC(GPP_D15, NONE), /* M.2_BT_I2S2_PCMFRM/NONE */ |
| 325 | PAD_CFG_GPO(GPP_S04, 1, DEEP), /* EN_SPKR_PA */ |
| 326 | PAD_CFG_GPI_INT(GPP_S05, NONE, PLTRST, EDGE_BOTH), |
| 327 | |
| 328 | /* SMBUS */ |
| 329 | PAD_CFG_NF(GPP_C00, NONE, DEEP, NF1), /* GPP_C0_SMBCLK */ |
| 330 | PAD_CFG_NF(GPP_C01, NONE, DEEP, NF1), /* GPP_C1_SMBDATA */ |
| 331 | |
| 332 | /* SSD */ |
| 333 | PAD_CFG_GPO(GPP_B15, 0, DEEP), /* M.2_CPU_SSD3_PWREN */ |
| 334 | PAD_CFG_GPO(GPP_D06, 0, DEEP), /* M.2_CPU_SSD4_PWREN */ |
| 335 | }; |
| 336 | |
| 337 | static const struct pad_config early_uart_gpio_table[] = { |
| 338 | /* UART0 */ |
| 339 | PAD_CFG_NF(GPP_H08, NONE, DEEP, NF1), /* UART0_RXD */ |
| 340 | PAD_CFG_NF(GPP_H09, NONE, DEEP, NF1), /* UART0_TXD */ |
| 341 | }; |
| 342 | |
| 343 | static const struct pad_config early_wwan_on_gpio_table[] = { |
| 344 | /* M.2 WWAN */ |
| 345 | PAD_CFG_GPO(GPP_B17, 1, DEEP), /* WWAN_PWREN */ |
| 346 | PAD_CFG_GPO(GPP_E07, 1, DEEP), /* M.2_WWAN_FCP_OFF_N */ |
| 347 | PAD_CFG_GPO(GPP_A15, 0, DEEP), /* M.2_WWAN_RST_N */ |
| 348 | PAD_CFG_GPO(GPP_C05, 0, DEEP), /* M.2_WWAN_PERST_GPIO_N */ |
| 349 | PAD_CFG_GPI_SCI(GPP_F10, NONE, DEEP, LEVEL, INVERT), /* M.2_WWAN_WAKE_GPIO_N */ |
| 350 | }; |
| 351 | |
| 352 | void configure_early_gpio_pads(void) |
| 353 | { |
| 354 | uint8_t board_id = get_rvp_board_id(); |
| 355 | |
| 356 | if (CONFIG(INTEL_LPSS_UART_FOR_CONSOLE)) |
| 357 | gpio_configure_pads(early_uart_gpio_table, ARRAY_SIZE(early_uart_gpio_table)); |
| 358 | |
| 359 | switch (board_id) { |
| 360 | case MTLP_DDR5_RVP: |
| 361 | case MTLP_LP5_T3_RVP: |
| 362 | case MTLP_LP5_T4_RVP: |
| 363 | gpio_configure_pads(mtl_p_rvp_early_gpio_table, |
| 364 | ARRAY_SIZE(mtl_p_rvp_early_gpio_table)); |
| 365 | gpio_configure_pads(early_wwan_on_gpio_table, |
| 366 | ARRAY_SIZE(early_wwan_on_gpio_table)); |
| 367 | break; |
| 368 | default: |
| 369 | printk(BIOS_WARNING, "Invalid board_id 0x%x." |
| 370 | "Skipping early gpio configuration\n", board_id); |
| 371 | break; |
| 372 | } |
| 373 | } |
| 374 | |
Harsha B R | a256bd6 | 2022-11-09 19:47:40 +0530 | [diff] [blame^] | 375 | void configure_gpio_pads(void) |
| 376 | { |
| 377 | uint8_t board_id = get_rvp_board_id(); |
| 378 | |
| 379 | switch (board_id) { |
| 380 | case MTLP_DDR5_RVP: |
| 381 | case MTLP_LP5_T3_RVP: |
| 382 | case MTLP_LP5_T4_RVP: |
| 383 | gpio_configure_pads(mtl_p_rvp_gpio_table, ARRAY_SIZE(mtl_p_rvp_gpio_table)); |
| 384 | break; |
| 385 | default: |
| 386 | printk(BIOS_WARNING, "Invalid board_id 0x%x." |
| 387 | "Skipping ramstage gpio configuration\n", board_id); |
| 388 | break; |
| 389 | } |
| 390 | } |
| 391 | |
Harsha B R | 500da54 | 2022-12-13 13:53:45 +0530 | [diff] [blame] | 392 | static const struct cros_gpio cros_gpios[] = { |
| 393 | CROS_GPIO_REC_AL(CROS_GPIO_VIRTUAL, CROS_GPIO_DEVICE_NAME), |
| 394 | }; |
| 395 | DECLARE_CROS_GPIOS(cros_gpios); |