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Martin Roth7d86f342024-02-16 11:04:02 -07001## SPDX-License-Identifier: GPL-2.0-only
2
Xi Chene8c681c2021-03-03 17:58:07 +08003config SOC_MEDIATEK_COMMON
4 bool
Jianjun Wang270b0b62021-07-14 15:38:19 +08005 select NO_ECAM_MMCONF_SUPPORT if PCI
Xi Chene8c681c2021-03-03 17:58:07 +08006 help
7 common code blocks for Mediatek SOCs
8
9if SOC_MEDIATEK_COMMON
10
Yidi Lina0617552024-02-21 18:52:05 +080011config MEDIATEK_DRAM_ADAPTIVE
12 bool
13 default n if SOC_MEDIATEK_MT8173
14 default n if SOC_MEDIATEK_MT8183
15 default n if SOC_MEDIATEK_MT8192
16 default y
17 help
18 Starting from MT8195, MediaTek platform supports "dram adaptive" to
19 automatically detect dram information, including channel, rank, die
20 size..., and can automatically configure EMI settings. So we can just
21 pass a placeholder param blob to `mt_mem_init_run` by enabling this
22 option.
23 Platforms (MT8173, MT8183, MT8192) which do not support "dram adaptive"
24 need to implement `get_sdram_config` to get the DRAM configuration info.
25
Xi Chene8c681c2021-03-03 17:58:07 +080026config MEDIATEK_DRAM_DVFS
27 bool
28 default n
29 help
30 This option enables DRAM calibration with multiple frequencies (low,
31 medium and high frequency groups, with total 7 frequencies) for DVFS
32 feature. All supported data rates are: 800, 1200, 1600, 1866, 2400,
33 3200, 4266.
34
35config MEDIATEK_DRAM_DVFS_LIMIT_FREQ_CNT
36 bool
37 default y
Rex-BC Chen909f2d02021-08-10 16:17:09 +080038 depends on MEDIATEK_DRAM_DVFS
Xi Chene8c681c2021-03-03 17:58:07 +080039 help
40 This options limit DRAM frequency calibration count from total 7 to 3,
41 other frequency will directly use the low frequency shu result.
42
Yu-Ping Wuc0716522023-02-21 17:24:54 +080043config MEDIATEK_DRAM_BLOB_FAST_INIT
Xi Chen5c7a9232022-01-04 19:00:44 +080044 bool "Enable running fast calibration by blob"
45 default n
46 help
47 This option allows performing fast calibration through different
48 open-source policy.
49
Xi Chena6378732023-02-21 14:31:58 +080050config MEDIATEK_DRAM_SCRAMBLE
Xi Chen3ea02022023-06-14 10:38:19 +080051 bool "Enable DRAM scramble feature"
Yidi Lin37e832502023-06-01 12:15:17 +080052 default n
Xi Chena6378732023-02-21 14:31:58 +080053 help
54 This option enables DRAM data scramble, which can prevent DRAM data from
55 being hacked.
56
Xi Chene8c681c2021-03-03 17:58:07 +080057config MEMORY_TEST
58 bool
59 default y
60 help
61 This option enables memory basic compare test to verify the DRAM read
62 or write is as expected.
63
Ryan Chuangd41a5ae2021-06-18 19:47:39 +080064config DPM_FOUR_CHANNEL
65 bool
66 default n
67 help
68 This option enables four channel configuration for DPM.
69
Rex-BC Chen716320b2021-08-10 12:28:09 +080070config MTK_DFD
Rex-BC Chen561a2af2021-11-25 12:16:51 +080071 bool "Enable MediaTek DFD (Design For Debug) settings"
Rex-BC Chen716320b2021-08-10 12:28:09 +080072 help
Rex-BC Chen561a2af2021-11-25 12:16:51 +080073 DFD (Design for Debug) is a debugging tool, which scans flip-flops
74 and dumps to internal RAM on the WDT reset. We reserve 1MB on DRAM
75 to store logs of DFD.
Rex-BC Chen716320b2021-08-10 12:28:09 +080076
Rex-BC Chenc69ea242022-03-25 15:53:22 +080077config USE_CBMEM_DRAM_INFO
78 bool "Support filling dram information to cbmem"
79 help
80 The DRAM initialization will keep and return DRAM information (size,
81 geometry and other DDR info) so we can fill that into the CBMEM.
82
Rex-BC Chen7a0ca5b2022-06-13 19:01:51 +080083config FLASH_DUAL_IO_READ
84 bool
85 default n
86 help
87 When this option is enabled, the flash controller provides the ability
88 to dual IO read mode.
89
Rex-BC Chen6d449e02022-10-19 18:51:39 +080090config PWRAP_WITH_PMIF_SPMI
91 bool
92 default n
93 help
94 When this option is enabled, the PMIC interface only supports PWRAP
95 and PMIF_SPMI.
96
Rex-BC Chen15432522022-10-19 19:00:22 +080097config PMIF_SPMI_IOCFG_DEFAULT_SETTING
98 bool
99 default n
100 help
101 For SoCs where IO pins default to PMIF_SPMI mode, enable this option
102 to skip software PMIF_SPMI IO pins configuration.
103
Yidi Lin63d26b82022-12-20 16:42:53 +0800104config DEVAPC_DEBUG
105 bool
106 default n
107 help
108 When this option is enabled, the DEVAPC driver prints the settings after
109 initialization.
110
Yidi Linc68176c2024-01-16 15:08:41 +0800111config EARLY_MMU_INIT
112 bool
113 default n
114 help
115 When this option is enabled, `mtk_mmu_init()` will be done in
116 `bootblock_soc_early_init()` to reduce the boot time.
117
Xi Chene8c681c2021-03-03 17:58:07 +0800118endif