Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2015 Damien Zammit <damien@zamaudio.com> |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or |
| 7 | * modify it under the terms of the GNU General Public License as |
| 8 | * published by the Free Software Foundation; either version 2 of |
| 9 | * the License, or (at your option) any later version. |
| 10 | * |
| 11 | * This program is distributed in the hope that it will be useful, |
| 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 14 | * GNU General Public License for more details. |
| 15 | */ |
| 16 | |
| 17 | #include <stdint.h> |
| 18 | #include <arch/io.h> |
| 19 | #include <arch/cpu.h> |
| 20 | #include <console/console.h> |
| 21 | #include <commonlib/helpers.h> |
| 22 | #include <delay.h> |
Martin Roth | cbe3892 | 2016-01-05 19:40:41 -0700 | [diff] [blame] | 23 | #include "iomap.h" |
| 24 | #include "x4x.h" |
Damien Zammit | 4b513a6 | 2015-08-20 00:37:05 +1000 | [diff] [blame] | 25 | |
| 26 | static inline void barrier(void) |
| 27 | { |
| 28 | asm volatile("mfence":::); |
| 29 | } |
| 30 | |
| 31 | static u32 fsb2mhz(u32 speed) |
| 32 | { |
| 33 | return (speed * 267) + 800; |
| 34 | } |
| 35 | |
| 36 | static u32 ddr2mhz(u32 speed) |
| 37 | { |
| 38 | static const u16 mhz[] = { 0, 0, 667, 800, 1067, 1333 }; |
| 39 | |
| 40 | if (speed >= ARRAY_SIZE(mhz)) |
| 41 | return 0; |
| 42 | |
| 43 | return mhz[speed]; |
| 44 | } |
| 45 | |
| 46 | static u8 msbpos(u8 val) //Reverse |
| 47 | { |
| 48 | u8 i; |
| 49 | for (i = 7; i >= 0; i--) { |
| 50 | if ((val & (1 << i)) == 0) |
| 51 | break; |
| 52 | } |
| 53 | return i; |
| 54 | } |
| 55 | |
| 56 | static void sdram_detect_smallest_params2(struct sysinfo *s) |
| 57 | { |
| 58 | u16 mult[6] = { |
| 59 | 5000, // 400 |
| 60 | 3750, // 533 |
| 61 | 3000, // 667 |
| 62 | 2500, // 800 |
| 63 | 1875, // 1066 |
| 64 | 1500, // 1333 |
| 65 | }; |
| 66 | |
| 67 | u8 i; |
| 68 | u32 tmp; |
| 69 | u32 maxtras = 0; |
| 70 | u32 maxtrp = 0; |
| 71 | u32 maxtrcd = 0; |
| 72 | u32 maxtwr = 0; |
| 73 | u32 maxtrfc = 0; |
| 74 | u32 maxtwtr = 0; |
| 75 | u32 maxtrrd = 0; |
| 76 | u32 maxtrtp = 0; |
| 77 | |
| 78 | FOR_EACH_POPULATED_DIMM(s->dimms, i) { |
| 79 | maxtras = MAX(maxtras, s->dimms[i].spd_data[30] * 1000); |
| 80 | maxtrp = MAX(maxtrp, (s->dimms[i].spd_data[27] * 1000) >> 2); |
| 81 | maxtrcd = MAX(maxtrcd, (s->dimms[i].spd_data[29] * 1000) >> 2); |
| 82 | maxtwr = MAX(maxtwr, (s->dimms[i].spd_data[36] * 1000) >> 2); |
| 83 | maxtrfc = MAX(maxtrfc, s->dimms[i].spd_data[42] * 1000 + |
| 84 | (s->dimms[i].spd_data[40] & 0xf)); |
| 85 | maxtwtr = MAX(maxtwtr, (s->dimms[i].spd_data[37] * 1000) >> 2); |
| 86 | maxtrrd = MAX(maxtrrd, (s->dimms[i].spd_data[28] * 1000) >> 2); |
| 87 | maxtrtp = MAX(maxtrtp, (s->dimms[i].spd_data[38] * 1000) >> 2); |
| 88 | } |
| 89 | for (i = 9; i < 24; i++) { |
| 90 | tmp = mult[s->selected_timings.mem_clk] * i; |
| 91 | if (tmp >= maxtras) { |
| 92 | s->selected_timings.tRAS = i; |
| 93 | break; |
| 94 | } |
| 95 | } |
| 96 | for (i = 3; i < 10; i++) { |
| 97 | tmp = mult[s->selected_timings.mem_clk] * i; |
| 98 | if (tmp >= maxtrp) { |
| 99 | s->selected_timings.tRP = i; |
| 100 | break; |
| 101 | } |
| 102 | } |
| 103 | for (i = 3; i < 10; i++) { |
| 104 | tmp = mult[s->selected_timings.mem_clk] * i; |
| 105 | if (tmp >= maxtrcd) { |
| 106 | s->selected_timings.tRCD = i; |
| 107 | break; |
| 108 | } |
| 109 | } |
| 110 | for (i = 3; i < 15; i++) { |
| 111 | tmp = mult[s->selected_timings.mem_clk] * i; |
| 112 | if (tmp >= maxtwr) { |
| 113 | s->selected_timings.tWR = i; |
| 114 | break; |
| 115 | } |
| 116 | } |
| 117 | for (i = 15; i < 78; i++) { |
| 118 | tmp = mult[s->selected_timings.mem_clk] * i; |
| 119 | if (tmp >= maxtrfc) { |
| 120 | s->selected_timings.tRFC = ((i + 16) & 0xfe) - 15; |
| 121 | break; |
| 122 | } |
| 123 | } |
| 124 | for (i = 4; i < 15; i++) { |
| 125 | tmp = mult[s->selected_timings.mem_clk] * i; |
| 126 | if (tmp >= maxtwtr) { |
| 127 | s->selected_timings.tWTR = i; |
| 128 | break; |
| 129 | } |
| 130 | } |
| 131 | for (i = 2; i < 15; i++) { |
| 132 | tmp = mult[s->selected_timings.mem_clk] * i; |
| 133 | if (tmp >= maxtrrd) { |
| 134 | s->selected_timings.tRRD = i; |
| 135 | break; |
| 136 | } |
| 137 | } |
| 138 | for (i = 4; i < 15; i++) { |
| 139 | tmp = mult[s->selected_timings.mem_clk] * i; |
| 140 | if (tmp >= maxtrtp) { |
| 141 | s->selected_timings.tRTP = i; |
| 142 | break; |
| 143 | } |
| 144 | } |
| 145 | |
| 146 | s->selected_timings.fsb_clk = s->max_fsb; |
| 147 | |
| 148 | printk(BIOS_DEBUG, "Selected timings:\n"); |
| 149 | printk(BIOS_DEBUG, "\tFSB: %dMHz\n", fsb2mhz(s->selected_timings.fsb_clk)); |
| 150 | printk(BIOS_DEBUG, "\tDDR: %dMHz\n", ddr2mhz(s->selected_timings.mem_clk)); |
| 151 | |
| 152 | printk(BIOS_DEBUG, "\tCAS: %d\n", s->selected_timings.CAS); |
| 153 | printk(BIOS_DEBUG, "\ttRAS: %d\n", s->selected_timings.tRAS); |
| 154 | printk(BIOS_DEBUG, "\ttRP: %d\n", s->selected_timings.tRP); |
| 155 | printk(BIOS_DEBUG, "\ttRCD: %d\n", s->selected_timings.tRCD); |
| 156 | printk(BIOS_DEBUG, "\ttWR: %d\n", s->selected_timings.tWR); |
| 157 | printk(BIOS_DEBUG, "\ttRFC: %d\n", s->selected_timings.tRFC); |
| 158 | printk(BIOS_DEBUG, "\ttWTR: %d\n", s->selected_timings.tWTR); |
| 159 | printk(BIOS_DEBUG, "\ttRRD: %d\n", s->selected_timings.tRRD); |
| 160 | printk(BIOS_DEBUG, "\ttRTP: %d\n", s->selected_timings.tRTP); |
| 161 | } |
| 162 | |
| 163 | static void clkcross_ddr2(struct sysinfo *s) |
| 164 | { |
| 165 | u8 i, j; |
| 166 | MCHBAR16(0xc1c) = MCHBAR16(0xc1c) | (1 << 15); |
| 167 | |
| 168 | #define TAB_M667F800 {0x1f1f1f1f, 0x1a07070b, 0x0, 0x10000000, 0x20010208, \ |
| 169 | 0x04080000, 0x10010002, 0x0, 0x0, 0x02000000, \ |
| 170 | 0x04000100, 0x08000000, 0x10200204} |
| 171 | #define TAB_M800F800 {0xffffffff, 0x05030305, 0x0000ffff, 0x0, 0x08010204, \ |
| 172 | 0x0, 0x08010204, 0x0, 0x0, 0x0, 0x00020001, 0x0, 0x04080102} |
| 173 | #define TAB_M667F1067 {0x6d5b1f1f, 0x0f0f0f0f, 0x0, 0x20000000, 0x80020410, \ |
| 174 | 0x02040008, 0x10000100, 0x0, 0x0, 0x04000000, \ |
| 175 | 0x08000102, 0x20000000, 0x40010208} |
| 176 | #define TAB_M800F1067 {0x07070707, 0x06030303, 0x0, 0x0, 0x08010200, \ |
| 177 | 0x0, 0x04000102, 0x0, 0x0, 0x0, 0x00020001, \ |
| 178 | 0x0, 0x02040801} |
| 179 | #define TAB_M1067F1067 {0xffffffff, 0x05030305, 0x0000ffff, 0x0, 0x04080102, \ |
| 180 | 0x0, 0x08010204, 0x0, 0x0, 0x0, 0x00020001, \ |
| 181 | 0x0, 0x02040801} |
| 182 | #define TAB_M667F1333 {0x05050303, 0xffffffff, 0xffff0000, 0x0, 0x08020000, \ |
| 183 | 0x0, 0x00020001, 0x0, 0x0, 0x0, 0x08010204, \ |
| 184 | 0x0, 0x04010000} |
| 185 | #define TAB_M800F1333 {0x0d0b0707, 0x3e1f1f2f, 0x01010000, 0x0, 0x10020400, \ |
| 186 | 0x02000000, 0x00040100, 0x0, 0x0, 0x04080000, \ |
| 187 | 0x00100102, 0x0, 0x08100200} |
| 188 | #define TAB_M1067F1333 {0x0f0f0f0f, 0x5b1f1f6d, 0x0, 0x0, 0x08010204, \ |
| 189 | 0x04000000, 0x00080102, 0x0, 0x0, 0x02000408, \ |
| 190 | 0x00100001, 0x0, 0x04080102} |
| 191 | #define TAB_M1333F1333 {0xffffffff, 0x05030305, 0x0000ffff, 0x0, 0x04080102, \ |
| 192 | 0x0, 0x04080102, 0x0, 0x0, 0x0, 0x0, 0x0, 0x02040801} |
| 193 | |
| 194 | static const u32 clkxtab[6][3][13] = { |
| 195 | {{}, {}, {}}, // MEMCLK 400 N/A |
| 196 | {{}, {}, {}}, // MEMCLK 533 N/A |
| 197 | {TAB_M667F800, TAB_M667F1067, TAB_M667F1333, }, |
| 198 | {TAB_M800F800, TAB_M800F1067, TAB_M800F1333, }, |
| 199 | {{}, TAB_M1067F1067, TAB_M1067F1333, }, |
| 200 | {{}, {}, TAB_M1333F1333, }, |
| 201 | }; |
| 202 | |
| 203 | i = (u8)s->selected_timings.mem_clk; |
| 204 | j = (u8)s->selected_timings.fsb_clk; |
| 205 | |
| 206 | MCHBAR32(0xc04) = clkxtab[i][j][0]; |
| 207 | MCHBAR32(0xc50) = clkxtab[i][j][1]; |
| 208 | MCHBAR32(0xc54) = clkxtab[i][j][2]; |
| 209 | MCHBAR8(0xc08) = MCHBAR8(0xc08) | (1 << 7); |
| 210 | MCHBAR32(0x6d8) = clkxtab[i][j][3]; |
| 211 | MCHBAR32(0x6e0) = clkxtab[i][j][3]; |
| 212 | MCHBAR32(0x6dc) = clkxtab[i][j][4]; |
| 213 | MCHBAR32(0x6e4) = clkxtab[i][j][4]; |
| 214 | MCHBAR32(0x6e8) = clkxtab[i][j][5]; |
| 215 | MCHBAR32(0x6f0) = clkxtab[i][j][5]; |
| 216 | MCHBAR32(0x6ec) = clkxtab[i][j][6]; |
| 217 | MCHBAR32(0x6f4) = clkxtab[i][j][6]; |
| 218 | MCHBAR32(0x6f8) = clkxtab[i][j][7]; |
| 219 | MCHBAR32(0x6fc) = clkxtab[i][j][8]; |
| 220 | MCHBAR32(0x708) = clkxtab[i][j][11]; |
| 221 | MCHBAR32(0x70c) = clkxtab[i][j][12]; |
| 222 | } |
| 223 | |
| 224 | static void checkreset_ddr2(struct sysinfo *s) |
| 225 | { |
| 226 | u8 pmcon2; |
| 227 | u8 reset = 0; |
| 228 | |
| 229 | pmcon2 = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xa2); |
| 230 | if (!(pmcon2 & 0x80)) { |
| 231 | pmcon2 |= 0x80; |
| 232 | pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xa2, pmcon2); |
| 233 | reset = 1; |
| 234 | |
| 235 | /* do magic 0xf0 thing. */ |
| 236 | u8 reg8 = pci_read_config8(PCI_DEV(0, 0, 0), 0xf0); |
| 237 | pci_write_config8(PCI_DEV(0, 0, 0), 0xf0, reg8 & ~(1 << 2)); |
| 238 | reg8 = pci_read_config8(PCI_DEV(0, 0, 0), 0xf0); |
| 239 | pci_write_config8(PCI_DEV(0, 0, 0), 0xf0, reg8 | (1 << 2)); |
| 240 | } |
| 241 | if (reset) { |
| 242 | printk(BIOS_DEBUG, "Reset...\n"); |
| 243 | outb(0xe, 0xcf9); |
| 244 | asm ("hlt"); |
| 245 | } |
| 246 | pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xa2, pmcon2 | 0x80); |
| 247 | } |
| 248 | |
| 249 | static void setioclk_ddr2(struct sysinfo *s) |
| 250 | { |
| 251 | MCHBAR32(0x1bc) = 0x08060402; |
| 252 | MCHBAR16(0x1c0) = MCHBAR16(0x1c0) | 0x200; |
| 253 | MCHBAR16(0x1c0) = MCHBAR16(0x1c0) | 0x100; |
| 254 | MCHBAR16(0x1c0) = MCHBAR16(0x1c0) | 0x20; |
| 255 | MCHBAR16(0x1c0) = MCHBAR16(0x1c0) & ~1; |
| 256 | switch (s->selected_timings.mem_clk) { |
| 257 | default: |
| 258 | case MEM_CLOCK_800MHz: |
| 259 | case MEM_CLOCK_1066MHz: |
| 260 | MCHBAR8(0x5d9) = (MCHBAR8(0x5d9) & ~0x2) | 0x2; |
| 261 | MCHBAR8(0x9d9) = (MCHBAR8(0x9d9) & ~0x2) | 0x2; |
| 262 | MCHBAR8(0x189) = (MCHBAR8(0x189) & ~0xf0) | 0xc0; |
| 263 | MCHBAR8(0x189) = (MCHBAR8(0x189) & ~0xf0) | 0xe0; |
| 264 | MCHBAR8(0x189) = (MCHBAR8(0x189) & ~0xf0) | 0xa0; |
| 265 | break; |
| 266 | case MEM_CLOCK_667MHz: |
| 267 | case MEM_CLOCK_1333MHz: |
| 268 | MCHBAR8(0x5d9) = MCHBAR8(0x5d9) & ~0x2; |
| 269 | MCHBAR8(0x9d9) = MCHBAR8(0x9d9) & ~0x2; |
| 270 | MCHBAR8(0x189) = (MCHBAR8(0x189) & ~0xf0) | 0x40; |
| 271 | break; |
| 272 | } |
| 273 | MCHBAR32(0x594) = MCHBAR32(0x594) | (1 << 31); |
| 274 | MCHBAR32(0x994) = MCHBAR32(0x994) | (1 << 31); |
| 275 | } |
| 276 | |
| 277 | static void launch_ddr2(struct sysinfo *s) |
| 278 | { |
| 279 | u8 i; |
| 280 | u32 launch1 = 0x58001117; |
| 281 | u32 launch2 = 0; |
| 282 | u32 launch3 = 0; |
| 283 | |
| 284 | if (s->selected_timings.CAS == 5) { |
| 285 | launch2 = 0x00220201; |
| 286 | } else if ((s->selected_timings.mem_clk == MEM_CLOCK_800MHz) && |
| 287 | (s->selected_timings.CAS == 6)) { |
| 288 | launch2 = 0x00230302; |
| 289 | } else { |
| 290 | die("Unsupported CAS & Frequency combination detected\n"); |
| 291 | } |
| 292 | |
| 293 | FOR_EACH_POPULATED_CHANNEL(s->dimms, i) { |
| 294 | MCHBAR32(0x400*i + 0x220) = launch1; |
| 295 | MCHBAR32(0x400*i + 0x224) = launch2; |
| 296 | MCHBAR32(0x400*i + 0x21c) = launch3; |
| 297 | MCHBAR32(0x400*i + 0x248) = MCHBAR32(0x400*i + 0x248) | (1 << 23); |
| 298 | } |
| 299 | |
| 300 | MCHBAR32(0x2c0) = (MCHBAR32(0x2c0) & ~0x58000000) | 0x48000000; |
| 301 | MCHBAR32(0x2c0) = MCHBAR32(0x2c0) | 0x1e0; |
| 302 | MCHBAR32(0x2c4) = (MCHBAR32(0x2c4) & ~0xf) | 0xc; |
| 303 | } |
| 304 | |
| 305 | static void clkset0(u8 ch, u8 setting[5]) |
| 306 | { |
| 307 | MCHBAR16(0x400*ch + 0x5a0) = (MCHBAR16(0x400*ch + 0x5a0) & ~0xc440) | |
| 308 | (setting[4] << 14) | |
| 309 | (setting[3] << 6) | |
| 310 | (setting[2] << 10); |
| 311 | MCHBAR8(0x400*ch + 0x581) = (MCHBAR8(0x400*ch + 0x581) & ~0x70) | |
| 312 | (setting[1] << 4); |
| 313 | MCHBAR8(0x400*ch + 0x581) = (MCHBAR8(0x400*ch + 0x581) & ~0xf) | |
| 314 | setting[0]; |
| 315 | } |
| 316 | |
| 317 | static void clkset1(u8 ch, u8 setting[5]) |
| 318 | { |
| 319 | MCHBAR32(0x400*ch + 0x5a0) = (MCHBAR32(0x400*ch + 0x5a0) & ~0x30880) | |
| 320 | (setting[4] << 16) | |
| 321 | (setting[3] << 7) | |
| 322 | (setting[2] << 11); |
| 323 | MCHBAR8(0x400*ch + 0x582) = (MCHBAR8(0x400*ch + 0x582) & ~0x70) | |
| 324 | (setting[1] << 4); |
| 325 | MCHBAR8(0x400*ch + 0x582) = (MCHBAR8(0x400*ch + 0x582) & ~0xf) | |
| 326 | setting[0]; |
| 327 | } |
| 328 | |
| 329 | static void ctrlset0(u8 ch, u8 setting[5]) |
| 330 | { |
| 331 | MCHBAR32(0x400*ch + 0x59c) = (MCHBAR32(0x400*ch + 0x59c) & ~0x3300000) | |
| 332 | (setting[4] << 24) | |
| 333 | (setting[3] << 20) | |
| 334 | (setting[2] << 21); |
| 335 | MCHBAR8(0x400*ch + 0x584) = (MCHBAR8(0x400*ch + 0x584) & ~0x70) | |
| 336 | (setting[1] << 4); |
| 337 | MCHBAR8(0x400*ch + 0x584) = (MCHBAR8(0x400*ch + 0x584) & ~0xf) | |
| 338 | setting[0]; |
| 339 | } |
| 340 | |
| 341 | static void ctrlset1(u8 ch, u8 setting[5]) |
| 342 | { |
| 343 | MCHBAR32(0x400*ch + 0x59c) = (MCHBAR32(0x400*ch + 0x59c) & ~0x18c00000) | |
| 344 | (setting[4] << 27) | |
| 345 | (setting[3] << 22) | |
| 346 | (setting[2] << 23); |
| 347 | MCHBAR8(0x400*ch + 0x585) = (MCHBAR8(0x400*ch + 0x585) & ~0x70) | |
| 348 | (setting[1] << 4); |
| 349 | MCHBAR8(0x400*ch + 0x585) = (MCHBAR8(0x400*ch + 0x585) & ~0xf) | |
| 350 | setting[0]; |
| 351 | } |
| 352 | |
| 353 | static void ctrlset2(u8 ch, u8 setting[5]) |
| 354 | { |
| 355 | MCHBAR32(0x400*ch + 0x598) = (MCHBAR32(0x400*ch + 0x598) & ~0x18c00000) | |
| 356 | (setting[4] << 14) | |
| 357 | (setting[3] << 12) | |
| 358 | (setting[2] << 13); |
| 359 | MCHBAR8(0x400*ch + 0x586) = (MCHBAR8(0x400*ch + 0x586) & ~0x70) | |
| 360 | (setting[1] << 4); |
| 361 | MCHBAR8(0x400*ch + 0x586) = (MCHBAR8(0x400*ch + 0x586) & ~0xf) | |
| 362 | setting[0]; |
| 363 | } |
| 364 | |
| 365 | static void ctrlset3(u8 ch, u8 setting[5]) |
| 366 | { |
| 367 | MCHBAR32(0x400*ch + 0x598) = (MCHBAR32(0x400*ch + 0x598) & ~0x18c00000) | |
| 368 | (setting[4] << 10) | |
| 369 | (setting[3] << 8) | |
| 370 | (setting[2] << 9); |
| 371 | MCHBAR8(0x400*ch + 0x587) = (MCHBAR8(0x400*ch + 0x587) & ~0x70) | |
| 372 | (setting[1] << 4); |
| 373 | MCHBAR8(0x400*ch + 0x587) = (MCHBAR8(0x400*ch + 0x587) & ~0xf) | |
| 374 | setting[0]; |
| 375 | } |
| 376 | |
| 377 | static void cmdset(u8 ch, u8 setting[5]) |
| 378 | { |
| 379 | MCHBAR8(0x400*ch + 0x598) = (MCHBAR8(0x400*ch + 0x598) & ~0x30) | |
| 380 | (setting[4] << 4); |
| 381 | MCHBAR8(0x400*ch + 0x594) = (MCHBAR8(0x400*ch + 0x594) & ~0x60) | |
| 382 | (setting[3] << 5) | |
| 383 | (setting[2] << 6); |
| 384 | MCHBAR8(0x400*ch + 0x580) = (MCHBAR8(0x400*ch + 0x580) & ~0x70) | |
| 385 | (setting[1] << 4); |
| 386 | MCHBAR8(0x400*ch + 0x580) = (MCHBAR8(0x400*ch + 0x580) & ~0xf) | |
| 387 | setting[0]; |
| 388 | } |
| 389 | |
| 390 | static void dqsset(u8 ch, u8 lane, u8 setting[5]) |
| 391 | { |
| 392 | MCHBAR32(0x400*ch + 0x5fc) = MCHBAR32(0x400*ch + 0x5fc) & ~(2 << (lane*4)); |
| 393 | |
| 394 | MCHBAR32(0x400*ch + 0x5b4) = (MCHBAR32(0x400*ch + 0x5b4) & ~(0x201 << lane)) | |
| 395 | (setting[2] << (9 + lane)) | |
| 396 | (setting[3] << lane); |
| 397 | MCHBAR32(0x400*ch + 0x5b8) = (MCHBAR32(0x400*ch + 0x5b8) & ~(0x201 << lane)) | |
| 398 | (setting[2] << (9 + lane)) | |
| 399 | (setting[3] << lane); |
| 400 | MCHBAR32(0x400*ch + 0x5bc) = (MCHBAR32(0x400*ch + 0x5bc) & ~(0x201 << lane)) | |
| 401 | (setting[2] << (9 + lane)) | |
| 402 | (setting[3] << lane); |
| 403 | MCHBAR32(0x400*ch + 0x5c0) = (MCHBAR32(0x400*ch + 0x5c0) & ~(0x201 << lane)) | |
| 404 | (setting[2] << (9 + lane)) | |
| 405 | (setting[3] << lane); |
| 406 | |
| 407 | MCHBAR32(0x400*ch + 0x5c8) = (MCHBAR32(0x400*ch + 0x5c8) & ~(0x3 << (16+lane*2))) | |
| 408 | (setting[4] << (16+lane*2)); |
| 409 | MCHBAR32(0x400*ch + 0x5cc) = (MCHBAR32(0x400*ch + 0x5cc) & ~(0x3 << (16+lane*2))) | |
| 410 | (setting[4] << (16+lane*2)); |
| 411 | MCHBAR32(0x400*ch + 0x5d0) = (MCHBAR32(0x400*ch + 0x5d0) & ~(0x3 << (16+lane*2))) | |
| 412 | (setting[4] << (16+lane*2)); |
| 413 | MCHBAR32(0x400*ch + 0x5d4) = (MCHBAR32(0x400*ch + 0x5d4) & ~(0x3 << (16+lane*2))) | |
| 414 | (setting[4] << (16+lane*2)); |
| 415 | |
| 416 | MCHBAR8(0x400*ch + 0x520 + lane*4) = (MCHBAR8(0x400*ch + 0x520 + lane*4) & ~0x70) | |
| 417 | (setting[1] << 4); |
| 418 | MCHBAR8(0x400*ch + 0x520 + lane*4) = (MCHBAR8(0x400*ch + 0x520 + lane*4) & ~0xf) | |
| 419 | setting[0]; |
| 420 | MCHBAR8(0x400*ch + 0x521 + lane*4) = (MCHBAR8(0x400*ch + 0x521 + lane*4) & ~0x70) | |
| 421 | (setting[1] << 4); |
| 422 | MCHBAR8(0x400*ch + 0x521 + lane*4) = (MCHBAR8(0x400*ch + 0x521 + lane*4) & ~0xf) | |
| 423 | setting[0]; |
| 424 | MCHBAR8(0x400*ch + 0x522 + lane*4) = (MCHBAR8(0x400*ch + 0x522 + lane*4) & ~0x70) | |
| 425 | (setting[1] << 4); |
| 426 | MCHBAR8(0x400*ch + 0x522 + lane*4) = (MCHBAR8(0x400*ch + 0x522 + lane*4) & ~0xf) | |
| 427 | setting[0]; |
| 428 | MCHBAR8(0x400*ch + 0x523 + lane*4) = (MCHBAR8(0x400*ch + 0x523 + lane*4) & ~0x70) | |
| 429 | (setting[1] << 4); |
| 430 | MCHBAR8(0x400*ch + 0x523 + lane*4) = (MCHBAR8(0x400*ch + 0x523 + lane*4) & ~0xf) | |
| 431 | setting[0]; |
| 432 | } |
| 433 | |
| 434 | static void dqset(u8 ch, u8 lane, u8 setting[5]) |
| 435 | { |
| 436 | MCHBAR32(0x400*ch + 0x5fc) = MCHBAR32(0x400*ch + 0x5fc) & ~(1 << (lane*4)); |
| 437 | |
| 438 | MCHBAR32(0x400*ch + 0x5a4) = (MCHBAR32(0x400*ch + 0x5a4) & ~(0x201 << lane)) | |
| 439 | (setting[2] << (9+lane)) | |
| 440 | (setting[3] << lane); |
| 441 | MCHBAR32(0x400*ch + 0x5a8) = (MCHBAR32(0x400*ch + 0x5a8) & ~(0x201 << lane)) | |
| 442 | (setting[2] << (9+lane)) | |
| 443 | (setting[3] << lane); |
| 444 | MCHBAR32(0x400*ch + 0x5ac) = (MCHBAR32(0x400*ch + 0x5ac) & ~(0x201 << lane)) | |
| 445 | (setting[2] << (9+lane)) | |
| 446 | (setting[3] << lane); |
| 447 | MCHBAR32(0x400*ch + 0x5b0) = (MCHBAR32(0x400*ch + 0x5b0) & ~(0x201 << lane)) | |
| 448 | (setting[2] << (9+lane)) | |
| 449 | (setting[3] << lane); |
| 450 | |
| 451 | MCHBAR32(0x400*ch + 0x5c8) = (MCHBAR32(0x400*ch + 0x5c8) & ~(0x3 << (lane*2))) | |
| 452 | (setting[4] << (2*lane)); |
| 453 | MCHBAR32(0x400*ch + 0x5cc) = (MCHBAR32(0x400*ch + 0x5cc) & ~(0x3 << (lane*2))) | |
| 454 | (setting[4] << (2*lane)); |
| 455 | MCHBAR32(0x400*ch + 0x5d0) = (MCHBAR32(0x400*ch + 0x5d0) & ~(0x3 << (lane*2))) | |
| 456 | (setting[4] << (2*lane)); |
| 457 | MCHBAR32(0x400*ch + 0x5d4) = (MCHBAR32(0x400*ch + 0x5d4) & ~(0x3 << (lane*2))) | |
| 458 | (setting[4] << (2*lane)); |
| 459 | |
| 460 | MCHBAR8(0x400*ch + 0x500 + lane*4) = (MCHBAR8(0x400*ch + 0x500 + lane*4) & ~0x70) | |
| 461 | (setting[1] << 4); |
| 462 | MCHBAR8(0x400*ch + 0x500 + lane*4) = (MCHBAR8(0x400*ch + 0x500 + lane*4) & ~0xf) | |
| 463 | setting[0]; |
| 464 | MCHBAR8(0x400*ch + 0x501 + lane*4) = (MCHBAR8(0x400*ch + 0x501 + lane*4) & ~0x70) | |
| 465 | (setting[1] << 4); |
| 466 | MCHBAR8(0x400*ch + 0x501 + lane*4) = (MCHBAR8(0x400*ch + 0x501 + lane*4) & ~0xf) | |
| 467 | setting[0]; |
| 468 | MCHBAR8(0x400*ch + 0x502 + lane*4) = (MCHBAR8(0x400*ch + 0x502 + lane*4) & ~0x70) | |
| 469 | (setting[1] << 4); |
| 470 | MCHBAR8(0x400*ch + 0x502 + lane*4) = (MCHBAR8(0x400*ch + 0x502 + lane*4) & ~0xf) | |
| 471 | setting[0]; |
| 472 | MCHBAR8(0x400*ch + 0x503 + lane*4) = (MCHBAR8(0x400*ch + 0x503 + lane*4) & ~0x70) | |
| 473 | (setting[1] << 4); |
| 474 | MCHBAR8(0x400*ch + 0x503 + lane*4) = (MCHBAR8(0x400*ch + 0x503 + lane*4) & ~0xf) | |
| 475 | setting[0]; |
| 476 | } |
| 477 | |
| 478 | static void timings_ddr2(struct sysinfo *s) |
| 479 | { |
| 480 | u8 i; |
| 481 | u8 twl, ta1, ta2, ta3, ta4; |
| 482 | u8 reg8; |
| 483 | u8 flag1 = 0; |
| 484 | u8 flag2 = 0; |
| 485 | u16 reg16; |
| 486 | u32 reg32; |
| 487 | u16 ddr, fsb; |
| 488 | u8 trpmod = 0; |
| 489 | u8 bankmod = 1; |
| 490 | u8 pagemod = 0; |
| 491 | |
| 492 | u16 fsb2ps[3] = { |
| 493 | 5000, // 800 |
| 494 | 3750, // 1067 |
| 495 | 3000 // 1333 |
| 496 | }; |
| 497 | |
| 498 | u16 ddr2ps[6] = { |
| 499 | 5000, // 400 |
| 500 | 3750, // 533 |
| 501 | 3000, // 667 |
| 502 | 2500, // 800 |
| 503 | 1875, // 1067 |
| 504 | 1500 // 1333 |
| 505 | }; |
| 506 | |
| 507 | u16 lut1[6] = { |
| 508 | 0, |
| 509 | 0, |
| 510 | 2600, |
| 511 | 3120, |
| 512 | 4171, |
| 513 | 5200 |
| 514 | }; |
| 515 | |
| 516 | ta1 = 6; |
| 517 | ta2 = 6; |
| 518 | ta3 = 5; |
| 519 | ta4 = 8; |
| 520 | |
| 521 | twl = s->selected_timings.CAS - 1; |
| 522 | |
| 523 | FOR_EACH_POPULATED_DIMM(s->dimms, i) { |
| 524 | if (s->dimms[i].banks == 1) { // 8 banks |
| 525 | trpmod = 1; |
| 526 | bankmod = 0; |
| 527 | } |
| 528 | if (s->dimms[i].page_size == 2048) { |
| 529 | pagemod = 1; |
| 530 | } |
| 531 | } |
| 532 | |
| 533 | FOR_EACH_POPULATED_CHANNEL(s->dimms, i) { |
| 534 | MCHBAR8(0x400*i + 0x2f6) = MCHBAR8(0x400*i + 0x2f6) | 0x3; |
| 535 | MCHBAR8(0x400*i + 0x228) = (MCHBAR8(0x400*i + 0x228) & ~0x7) | 0x2; |
| 536 | MCHBAR8(0x400*i + 0x240) = (MCHBAR8(0x400*i + 0x240) & ~0xf0) | (twl << 4); |
| 537 | MCHBAR8(0x400*i + 0x240) = (MCHBAR8(0x400*i + 0x240) & ~0xf) | |
| 538 | s->selected_timings.CAS; |
| 539 | MCHBAR16(0x400*i + 0x265) = (MCHBAR16(0x400*i + 0x265) & ~0x3f00) | |
| 540 | ((s->selected_timings.CAS + 9) << 8); |
| 541 | |
| 542 | reg16 = (s->selected_timings.tRAS << 11) | |
| 543 | ((twl + 4 + s->selected_timings.tWR) << 6) | |
| 544 | ((2 + MAX(s->selected_timings.tRTP, 2)) << 2) | 1; |
| 545 | MCHBAR16(0x400*i + 0x250) = reg16; |
| 546 | |
| 547 | reg32 = (bankmod << 21) | |
| 548 | (s->selected_timings.tRRD << 17) | |
| 549 | (s->selected_timings.tRP << 13) | |
| 550 | ((s->selected_timings.tRP + trpmod) << 9) | |
| 551 | s->selected_timings.tRFC; |
| 552 | reg8 = (MCHBAR8(0x400*i + 0x26f) >> 1) & 1; |
| 553 | if (bankmod) { |
| 554 | switch (s->selected_timings.mem_clk) { |
| 555 | default: |
| 556 | case MEM_CLOCK_667MHz: |
| 557 | if (reg8) { |
| 558 | if (pagemod) { |
| 559 | reg32 |= 16 << 22; |
| 560 | } else { |
| 561 | reg32 |= 12 << 22; |
| 562 | } |
| 563 | } else { |
| 564 | if (pagemod) { |
| 565 | reg32 |= 18 << 22; |
| 566 | } else { |
| 567 | reg32 |= 14 << 22; |
| 568 | } |
| 569 | } |
| 570 | break; |
| 571 | case MEM_CLOCK_800MHz: |
| 572 | if (reg8) { |
| 573 | if (pagemod) { |
| 574 | reg32 |= 18 << 22; |
| 575 | } else { |
| 576 | reg32 |= 14 << 22; |
| 577 | } |
| 578 | } else { |
| 579 | if (pagemod) { |
| 580 | reg32 |= 20 << 22; |
| 581 | } else { |
| 582 | reg32 |= 16 << 22; |
| 583 | } |
| 584 | } |
| 585 | break; |
| 586 | } |
| 587 | } |
| 588 | MCHBAR32(0x400*i + 0x252) = reg32; |
| 589 | |
| 590 | MCHBAR16(0x400*i + 0x256) = (s->selected_timings.tRCD << 12) | |
| 591 | (0x4 << 8) | (ta2 << 4) | ta4; |
| 592 | |
| 593 | MCHBAR32(0x400*i + 0x258) = (s->selected_timings.tRCD << 17) | |
| 594 | ((twl + 4 + s->selected_timings.tWTR) << 12) | |
| 595 | (ta3 << 8) | (4 << 4) | ta1; |
| 596 | |
| 597 | MCHBAR16(0x400*i + 0x25b) = ((s->selected_timings.tRP + trpmod) << 9) | |
| 598 | s->selected_timings.tRFC; |
| 599 | |
| 600 | MCHBAR16(0x400*i + 0x260) = (MCHBAR16(0x400*i + 0x260) & ~0x3fe) | (100 << 1); |
| 601 | MCHBAR8(0x400*i + 0x264) = 0xff; |
| 602 | MCHBAR8(0x400*i + 0x25d) = (MCHBAR8(0x400*i + 0x25d) & ~0x3f) | |
| 603 | s->selected_timings.tRAS; |
| 604 | MCHBAR16(0x400*i + 0x244) = 0x2310; |
| 605 | |
| 606 | switch (s->selected_timings.mem_clk) { |
| 607 | case MEM_CLOCK_667MHz: |
| 608 | reg8 = 0; |
| 609 | break; |
| 610 | default: |
| 611 | reg8 = 1; |
| 612 | break; |
| 613 | } |
| 614 | |
| 615 | MCHBAR8(0x400*i + 0x246) = (MCHBAR8(0x400*i + 0x246) & ~0x1f) | |
| 616 | (reg8 << 2) | 1; |
| 617 | |
| 618 | fsb = fsb2ps[s->selected_timings.fsb_clk]; |
| 619 | ddr = ddr2ps[s->selected_timings.mem_clk]; |
| 620 | reg32 = (u32)((s->selected_timings.CAS + 7 + reg8) * ddr); |
| 621 | reg32 = (u32)((reg32 / fsb) << 8); |
| 622 | reg32 |= 0x0e000000; |
| 623 | if ((fsb2mhz(s->selected_timings.fsb_clk) / |
| 624 | ddr2mhz(s->selected_timings.mem_clk)) > 2) { |
| 625 | reg32 |= 1 << 24; |
| 626 | } |
| 627 | MCHBAR32(0x400*i + 0x248) = (MCHBAR32(0x400*i + 0x248) & ~0x0f001f00) | |
| 628 | reg32; |
| 629 | |
| 630 | if (twl > 2) { |
| 631 | flag1 = 1; |
| 632 | } |
| 633 | if (s->selected_timings.mem_clk >= MEM_CLOCK_800MHz) { |
| 634 | flag2 = 1; |
| 635 | } |
| 636 | reg16 = (u8)(twl - 1 - flag1 - flag2); |
| 637 | reg16 |= reg16 << 4; |
| 638 | if (s->selected_timings.mem_clk == MEM_CLOCK_1333MHz) { |
| 639 | if (reg16) { |
| 640 | reg16--; |
| 641 | } |
| 642 | } |
| 643 | reg16 |= flag1 << 8; |
| 644 | reg16 |= flag2 << 9; |
| 645 | MCHBAR16(0x400*i + 0x24d) = (MCHBAR16(0x400*i + 0x24d) & ~0x1ff) | reg16; |
| 646 | MCHBAR16(0x400*i + 0x25e) = 0x15a5; |
| 647 | MCHBAR32(0x400*i + 0x265) = MCHBAR32(0x400*i + 0x265) & ~0x1f; |
| 648 | MCHBAR32(0x400*i + 0x269) = (MCHBAR32(0x400*i + 0x269) & ~0x000fffff) | |
| 649 | (0x3f << 14) | lut1[s->selected_timings.mem_clk]; |
| 650 | MCHBAR8(0x400*i + 0x274) = MCHBAR8(0x400*i + 0x274) | 1; |
| 651 | MCHBAR8(0x400*i + 0x24c) = MCHBAR8(0x400*i + 0x24c) & ~0x3; |
| 652 | |
| 653 | reg16 = 0; |
| 654 | switch (s->selected_timings.mem_clk) { |
| 655 | default: |
| 656 | case MEM_CLOCK_667MHz: |
| 657 | reg16 = 0x99; |
| 658 | break; |
| 659 | case MEM_CLOCK_800MHz: |
| 660 | if (s->selected_timings.CAS == 5) { |
| 661 | reg16 = 0x19a; |
| 662 | } else if (s->selected_timings.CAS == 6) { |
| 663 | reg16 = 0x9a; |
| 664 | } |
| 665 | break; |
| 666 | } |
| 667 | reg16 &= 0x7; |
| 668 | reg16 += twl + 9; |
| 669 | reg16 <<= 10; |
| 670 | MCHBAR16(0x400*i + 0x24d) = (MCHBAR16(0x400*i + 0x24d) & ~0x7c00) | reg16; |
| 671 | MCHBAR8(0x400*i + 0x267) = (MCHBAR8(0x400*i + 0x267) & ~0x3f) | 0x13; |
| 672 | MCHBAR8(0x400*i + 0x268) = (MCHBAR8(0x400*i + 0x268) & ~0xff) | 0x4a; |
| 673 | |
| 674 | reg16 = (MCHBAR16(0x400*i + 0x269) & 0xc000) >> 2; |
| 675 | reg16 += 2 << 12; |
| 676 | reg16 |= (0x15 << 6) | 0x1f; |
| 677 | MCHBAR16(0x400*i + 0x26d) = (MCHBAR16(0x400*i + 0x26d) & ~0x7fff) | reg16; |
| 678 | |
| 679 | reg32 = (1 << 25) | (6 << 27); |
| 680 | MCHBAR32(0x400*i + 0x269) = (MCHBAR32(0x400*i + 0x269) & ~0xfa300000) | reg32; |
| 681 | MCHBAR8(0x400*i + 0x271) = MCHBAR8(0x400*i + 0x271) & ~0x80; |
| 682 | MCHBAR8(0x400*i + 0x274) = MCHBAR8(0x400*i + 0x274) & ~0x6; |
| 683 | } // END EACH POPULATED CHANNEL |
| 684 | |
| 685 | reg16 = 0x1f << 5; |
| 686 | reg16 |= 0xe << 10; |
| 687 | MCHBAR16(0x125) = (MCHBAR16(0x125) & ~0x3fe0) | reg16; |
| 688 | MCHBAR16(0x127) = (MCHBAR16(0x127) & ~0x7ff) | 0x540; |
| 689 | MCHBAR8(0x129) = MCHBAR8(0x129) | 0x1f; |
| 690 | MCHBAR8(0x12c) = MCHBAR8(0x12c) | 0xa0; |
| 691 | MCHBAR32(0x241) = (MCHBAR32(0x241) & ~0x1ffff) | 0x11; |
| 692 | MCHBAR32(0x641) = (MCHBAR32(0x641) & ~0x1ffff) | 0x11; |
| 693 | MCHBAR8(0x246) = MCHBAR8(0x246) & ~0x10; |
| 694 | MCHBAR8(0x646) = MCHBAR8(0x646) & ~0x10; |
| 695 | MCHBAR32(0x120) = (2 << 29) | (1 << 28) | (1 << 23) | 0xd7f5f; |
| 696 | reg8 = (u8)((MCHBAR32(0x252) & 0x1e000) >> 13); |
| 697 | MCHBAR8(0x12d) = (MCHBAR8(0x12d) & ~0xf0) | (reg8 << 4); |
| 698 | reg8 = (u8)((MCHBAR32(0x258) & ~0x1e0000) >> 17); |
| 699 | MCHBAR8(0x12d) = (MCHBAR8(0x12d) & ~0xf) | reg8; |
| 700 | MCHBAR8(0x12f) = 0x4c; |
| 701 | reg32 = (1 << 31) | (0x80 << 14) | (1 << 13) | (0xa << 9); |
| 702 | MCHBAR32(0x6c0) = (MCHBAR32(0x6c0) & ~0xffffff00) | reg32; |
| 703 | MCHBAR8(0x6c4) = (MCHBAR8(0x6c4) & ~0x7) | 0x2; |
| 704 | } |
| 705 | |
| 706 | static void dll_ddr2(struct sysinfo *s) |
| 707 | { |
| 708 | u8 i, j, r, reg8, clk, async; |
| 709 | u16 reg16 = 0; |
| 710 | u32 reg32 = 0; |
| 711 | u8 lane; |
| 712 | |
| 713 | MCHBAR16(0x180) = (MCHBAR16(0x180) & ~0x7e06) | 0xc04; |
| 714 | MCHBAR16(0x182) = (MCHBAR16(0x182) & ~0x3ff) | 0xc8; |
| 715 | MCHBAR16(0x18a) = (MCHBAR16(0x18a) & ~0x1f1f) | 0x0f0f; |
| 716 | MCHBAR16(0x1b4) = (MCHBAR16(0x1b4) & ~0x8020) | 0x100; |
| 717 | MCHBAR8(0x194) = (MCHBAR8(0x194) & ~0x77) | 0x33; |
| 718 | switch (s->selected_timings.mem_clk) { |
| 719 | default: |
| 720 | case MEM_CLOCK_667MHz: |
| 721 | reg16 = (0xa << 9) | 0xa; |
| 722 | break; |
| 723 | case MEM_CLOCK_800MHz: |
| 724 | reg16 = (0x9 << 9) | 0x9; |
| 725 | break; |
| 726 | } |
| 727 | MCHBAR16(0x19c) = (MCHBAR16(0x19c) & ~0x1e0f) | reg16; |
| 728 | MCHBAR16(0x19c) = (MCHBAR16(0x19c) & ~0x2030) | 0x2010; |
| 729 | udelay(1); |
| 730 | MCHBAR16(0x198) = MCHBAR16(0x198) & ~0x100; |
| 731 | |
| 732 | MCHBAR16(0x1c8) = (MCHBAR16(0x1c8) & ~0x1f) | 0xd; |
| 733 | |
| 734 | udelay(1); |
| 735 | MCHBAR8(0x190) = MCHBAR8(0x190) & ~1; |
| 736 | udelay(1); // 533ns |
| 737 | MCHBAR32(0x198) = MCHBAR32(0x198) & ~0x11554000; |
| 738 | udelay(1); |
| 739 | MCHBAR32(0x198) = MCHBAR32(0x198) & ~0x1455; |
| 740 | udelay(1); |
| 741 | MCHBAR8(0x583) = MCHBAR8(0x583) & ~0x1c; |
| 742 | MCHBAR8(0x983) = MCHBAR8(0x983) & ~0x1c; |
| 743 | udelay(1); // 533ns |
| 744 | MCHBAR8(0x583) = MCHBAR8(0x583) & ~0x3; |
| 745 | MCHBAR8(0x983) = MCHBAR8(0x983) & ~0x3; |
| 746 | udelay(1); // 533ns |
| 747 | |
| 748 | // ME related |
| 749 | MCHBAR32(0x1a0) = (MCHBAR32(0x1a0) & ~0x7ffffff) | 0x551803; |
| 750 | |
| 751 | MCHBAR16(0x1b4) = MCHBAR16(0x1b4) & ~0x800; |
| 752 | MCHBAR8(0x1a8) = MCHBAR8(0x1a8) | 0xf0; |
| 753 | |
| 754 | FOR_EACH_CHANNEL(i) { |
| 755 | reg16 = 0; |
| 756 | MCHBAR16(0x400*i + 0x59c) = MCHBAR16(0x400*i + 0x59c) & ~0x3000; |
| 757 | |
| 758 | reg32 = 0; |
| 759 | FOR_EACH_RANK_IN_CHANNEL(r) if (!RANK_IS_POPULATED(s->dimms, i, r)) { |
| 760 | reg32 |= 0x111 << r; |
| 761 | } |
| 762 | MCHBAR32(0x400*i + 0x59c) = (MCHBAR32(0x400*i + 0x59c) & ~0xfff) | reg32; |
| 763 | MCHBAR8(0x400*i + 0x594) = MCHBAR8(0x400*i + 0x594) & ~1; |
| 764 | |
| 765 | if (!CHANNEL_IS_POPULATED(s->dimms, i)) { |
| 766 | printk(BIOS_DEBUG, "No dimms in channel %d\n", i); |
| 767 | reg8 = 0x3f; |
| 768 | } else if(ONLY_DIMMA_IS_POPULATED(s->dimms, i)) { |
| 769 | printk(BIOS_DEBUG, "DimmA populated only in channel %d\n", i); |
| 770 | reg8 = 0x38; |
| 771 | } else if(ONLY_DIMMB_IS_POPULATED(s->dimms, i)) { |
| 772 | printk(BIOS_DEBUG, "DimmB populated only in channel %d\n", i); |
| 773 | reg8 = 0x7; |
| 774 | } else if(BOTH_DIMMS_ARE_POPULATED(s->dimms, i)) { |
| 775 | printk(BIOS_DEBUG, "Both dimms populated in channel %d\n", i); |
| 776 | reg8 = 0; |
| 777 | } else { |
| 778 | die("Unhandled case\n"); |
| 779 | } |
| 780 | |
| 781 | //reg8 = 0x00; // FIXME dont switch on all clocks anyway |
| 782 | |
| 783 | MCHBAR32(0x400*i + 0x5a0) = (MCHBAR32(0x400*i + 0x5a0) & ~0x3f000000) | |
| 784 | ((u32)(reg8 << 24)); |
| 785 | } // END EACH CHANNEL |
| 786 | |
| 787 | MCHBAR8(0x1a8) = MCHBAR8(0x1a8) | 1; |
| 788 | MCHBAR8(0x1a8) = MCHBAR8(0x1a8) & ~0x4; |
| 789 | |
| 790 | // Update DLL timing |
| 791 | MCHBAR8(0x1a4) = MCHBAR8(0x1a4) & ~0x80; |
| 792 | MCHBAR8(0x1a4) = MCHBAR8(0x1a4) | 0x40; |
| 793 | MCHBAR16(0x5f0) = (MCHBAR16(0x5f0) & ~0x400) | 0x400; |
| 794 | |
| 795 | u8 dll_setting_667[23][5] = { |
| 796 | // tap pi db delay |
| 797 | {13, 0, 1,0, 0}, |
| 798 | {4, 1, 0,0, 0}, |
| 799 | {13, 0, 1,0, 0}, |
| 800 | {4, 5, 0,0, 0}, |
| 801 | {4, 1, 0,0, 0}, |
| 802 | {4, 1, 0,0, 0}, |
| 803 | {4, 1, 0,0, 0}, |
| 804 | {1, 5, 1,1, 1}, |
| 805 | {1, 6, 1,1, 1}, |
| 806 | {2, 0, 1,1, 1}, |
| 807 | {2, 1, 1,1, 1}, |
| 808 | {2, 1, 1,1, 1}, |
| 809 | {14, 6, 1,0, 0}, |
| 810 | {14, 3, 1,0, 0}, |
| 811 | {14, 0, 1,0, 0}, |
| 812 | {9, 0, 0,0, 1}, |
| 813 | {9, 1, 0,0, 1}, |
| 814 | {9, 2, 0,0, 1}, |
| 815 | {9, 2, 0,0, 1}, |
| 816 | {9, 1, 0,0, 1}, |
| 817 | {6, 4, 0,0, 1}, |
| 818 | {6, 2, 0,0, 1}, |
| 819 | {5, 4, 0,0, 1} |
| 820 | }; |
| 821 | |
| 822 | u8 dll_setting_800[23][5] = { |
| 823 | // tap pi db delay |
| 824 | {11, 5, 1,0, 0}, |
| 825 | {0, 5, 1,1, 0}, |
| 826 | {11, 5, 1,0, 0}, |
| 827 | {1, 4, 1,1, 0}, |
| 828 | {0, 5, 1,1, 0}, |
| 829 | {0, 5, 1,1, 0}, |
| 830 | {0, 5, 1,1, 0}, |
| 831 | {2, 5, 1,1, 1}, |
| 832 | {2, 6, 1,1, 1}, |
| 833 | {3, 0, 1,1, 1}, |
| 834 | {3, 0, 1,1, 1}, |
| 835 | {3, 3, 1,1, 1}, |
| 836 | {2, 0, 1,1, 1}, |
| 837 | {1, 3, 1,1, 1}, |
| 838 | {0, 3, 1,1, 1}, |
| 839 | {9, 3, 0,0, 1}, |
| 840 | {9, 4, 0,0, 1}, |
| 841 | {9, 5, 0,0, 1}, |
| 842 | {9, 6, 0,0, 1}, |
| 843 | {10, 0, 0,0, 1}, |
| 844 | {8, 1, 0,0, 1}, |
| 845 | {7, 5, 0,0, 1}, |
| 846 | {6, 2, 0,0, 1} |
| 847 | }; |
| 848 | |
| 849 | FOR_EACH_POPULATED_CHANNEL(s->dimms, i) { |
| 850 | MCHBAR16(0x400*i + 0x5f0) = (MCHBAR16(0x400*i + 0x5f0) & ~0x3fc) | 0x3fc; |
| 851 | MCHBAR32(0x400*i + 0x5fc) = MCHBAR32(0x400*i + 0x5fc) & ~0xcccccccc; |
| 852 | MCHBAR8(0x400*i + 0x5d9) = (MCHBAR8(0x400*i + 0x5d9) & ~0xf0) | 0x70; |
| 853 | MCHBAR16(0x400*i + 0x590) = (MCHBAR16(0x400*i + 0x590) & ~0xffff) | 0x5555; |
| 854 | } |
| 855 | |
| 856 | FOR_EACH_POPULATED_CHANNEL(s->dimms, i) { |
| 857 | if (s->selected_timings.mem_clk == MEM_CLOCK_667MHz) { |
| 858 | clkset0(i, &dll_setting_667[CLKSET0][0]); |
| 859 | clkset1(i, &dll_setting_667[CLKSET1][0]); |
| 860 | ctrlset0(i, &dll_setting_667[CTRL0][0]); |
| 861 | ctrlset1(i, &dll_setting_667[CTRL1][0]); |
| 862 | ctrlset2(i, &dll_setting_667[CTRL2][0]); |
| 863 | ctrlset3(i, &dll_setting_667[CTRL3][0]); |
| 864 | cmdset(i, &dll_setting_667[CMD][0]); |
| 865 | } else { |
| 866 | clkset0(i, &dll_setting_800[CLKSET0][0]); |
| 867 | clkset1(i, &dll_setting_800[CLKSET1][0]); |
| 868 | ctrlset0(i, &dll_setting_800[CTRL0][0]); |
| 869 | ctrlset1(i, &dll_setting_800[CTRL1][0]); |
| 870 | ctrlset2(i, &dll_setting_800[CTRL2][0]); |
| 871 | ctrlset3(i, &dll_setting_800[CTRL3][0]); |
| 872 | cmdset(i, &dll_setting_800[CMD][0]); |
| 873 | } |
| 874 | } |
| 875 | |
| 876 | // XXX if not async mode |
| 877 | MCHBAR16(0x180) = MCHBAR16(0x180) & ~0x8200; |
| 878 | MCHBAR8(0x180) = MCHBAR8(0x180) | 0x4; |
| 879 | j = 0; |
| 880 | for (i = 0; i < 16; i++) { |
| 881 | MCHBAR8(0x1c8) = (MCHBAR8(0x1c8) & ~0x1f) | i; |
| 882 | MCHBAR8(0x180) = MCHBAR8(0x180) | 0x10; |
| 883 | while (MCHBAR8(0x180) & 0x10); |
| 884 | if (MCHBAR32(0x184) == 0xffffffff) { |
| 885 | j++; |
| 886 | if (j >= 2) |
| 887 | break; |
| 888 | |
| 889 | if (s->selected_timings.mem_clk == MEM_CLOCK_667MHz) { |
| 890 | j = 2; |
| 891 | break; |
| 892 | } |
| 893 | } else { |
| 894 | j = 0; |
| 895 | } |
| 896 | } |
| 897 | if (i == 1 || ((i == 0) && s->selected_timings.mem_clk == MEM_CLOCK_667MHz)) { |
| 898 | j = 0; |
| 899 | i++; |
| 900 | for (; i < 16; i++) { |
| 901 | MCHBAR8(0x1c8) = (MCHBAR8(0x1c8) & ~0x1f) | i; |
| 902 | MCHBAR8(0x180) = MCHBAR8(0x180) | 0x4; |
| 903 | while (MCHBAR8(0x180) & 0x10); |
| 904 | if (MCHBAR32(0x184) == 0) { |
| 905 | i++; |
| 906 | break; |
| 907 | } |
| 908 | } |
| 909 | for (; i < 16; i++) { |
| 910 | MCHBAR8(0x1c8) = (MCHBAR8(0x1c8) & ~0x1f) | i; |
| 911 | MCHBAR8(0x180) = MCHBAR8(0x180) | 0x10; |
| 912 | while (MCHBAR8(0x180) & 0x10); |
| 913 | if (MCHBAR32(0x184) == 0xffffffff) { |
| 914 | j++; |
| 915 | if (j >= 2) |
| 916 | break; |
| 917 | } else { |
| 918 | j = 0; |
| 919 | } |
| 920 | } |
| 921 | if (j < 2) { |
| 922 | MCHBAR8(0x1c8) = MCHBAR8(0x1c8) & ~0x1f; |
| 923 | MCHBAR8(0x180) = MCHBAR8(0x180) | 0x10; |
| 924 | while (MCHBAR8(0x180) & 0x10); |
| 925 | j = 2; |
| 926 | } |
| 927 | } |
| 928 | |
| 929 | if (j < 2) { |
| 930 | MCHBAR8(0x1c8) = MCHBAR8(0x1c8) & ~0x1f; |
| 931 | async = 1; |
| 932 | } |
| 933 | |
| 934 | clk = 0x1a; |
| 935 | if (async != 1) { |
| 936 | reg8 = MCHBAR8(0x188) & 0x1e; |
| 937 | if (s->selected_timings.mem_clk == MEM_CLOCK_667MHz && |
| 938 | s->selected_timings.fsb_clk == FSB_CLOCK_800MHz) { |
| 939 | clk = 0x10; |
| 940 | } else if (s->selected_timings.mem_clk == MEM_CLOCK_800MHz) { |
| 941 | clk = 0x10; |
| 942 | } else { |
| 943 | clk = 0x1a; |
| 944 | } |
| 945 | } |
| 946 | MCHBAR8(0x180) = MCHBAR8(0x180) & ~0x80; |
| 947 | |
| 948 | if ((s->selected_timings.fsb_clk == FSB_CLOCK_800MHz) && |
| 949 | (s->selected_timings.mem_clk == MEM_CLOCK_667MHz)) { |
| 950 | i = MCHBAR8(0x180) & 0xf; |
| 951 | i = (i + 10) % 14; |
| 952 | MCHBAR8(0x1c8) = (MCHBAR8(0x1c8) & ~0x1f) | i; |
| 953 | MCHBAR8(0x180) = MCHBAR8(0x180) | 0x10; |
| 954 | while(MCHBAR8(0x180) & 0x10); |
| 955 | } |
| 956 | |
| 957 | reg8 = MCHBAR8(0x188) & ~1; |
| 958 | MCHBAR8(0x188) = reg8; |
| 959 | reg8 &= ~0x3e; |
| 960 | reg8 |= clk; |
| 961 | MCHBAR8(0x188) = reg8; |
| 962 | reg8 |= 1; |
| 963 | MCHBAR8(0x188) = reg8; |
| 964 | |
| 965 | if (s->selected_timings.mem_clk == MEM_CLOCK_1333MHz) { |
| 966 | MCHBAR8(0x18c) = MCHBAR8(0x18c) | 1; |
| 967 | } |
| 968 | |
| 969 | // Program DQ/DQS dll settings |
| 970 | reg32 = 0; |
| 971 | FOR_EACH_POPULATED_CHANNEL(s->dimms, i) { |
| 972 | for (lane = 0; lane < 8; lane++) { |
| 973 | if (s->selected_timings.mem_clk == MEM_CLOCK_667MHz) { |
| 974 | reg32 = 0x06db7777; |
| 975 | } else if (s->selected_timings.mem_clk == MEM_CLOCK_800MHz) { |
| 976 | reg32 = 0x00007777; |
| 977 | } |
| 978 | MCHBAR32(0x400*i + 0x540 + lane*4) = |
| 979 | (MCHBAR32(0x400*i + 0x540 + lane*4) & 0x0fffffff) | |
| 980 | reg32; |
| 981 | } |
| 982 | } |
| 983 | |
| 984 | FOR_EACH_POPULATED_CHANNEL(s->dimms, i) { |
| 985 | if (s->selected_timings.mem_clk == MEM_CLOCK_667MHz) { |
| 986 | for (lane = 0; lane < 8; lane++) { |
| 987 | dqsset(i, lane, &dll_setting_667[DQS1+lane][0]); |
| 988 | } |
| 989 | for (lane = 0; lane < 8; lane++) { |
| 990 | dqset(i, lane, &dll_setting_667[DQ1+lane][0]); |
| 991 | } |
| 992 | } else { |
| 993 | for (lane = 0; lane < 8; lane++) { |
| 994 | dqsset(i, lane, &dll_setting_800[DQS1+lane][0]); |
| 995 | } |
| 996 | for (lane = 0; lane < 8; lane++) { |
| 997 | dqset(i, lane, &dll_setting_800[DQ1+lane][0]); |
| 998 | } |
| 999 | } |
| 1000 | } |
| 1001 | } |
| 1002 | |
| 1003 | static void rcomp_ddr2(struct sysinfo *s) |
| 1004 | { |
| 1005 | u8 i, j, k; |
| 1006 | u32 x32a[8] = { 0x04040404, 0x06050505, 0x09090807, 0x0D0C0B0A, 0x04040404, 0x08070605, 0x0C0B0A09, 0x100F0E0D }; |
| 1007 | u16 x378[6] = { 0, 0xAAAA, 0x7777, 0x7777, 0x7777, 0x7777 }; |
| 1008 | u32 x382[6] = { 0, 0x02020202, 0x02020202, 0x02020202, 0x04030303, 0x04030303 }; |
| 1009 | u32 x386[6] = { 0, 0x03020202, 0x03020202, 0x03020202, 0x05040404, 0x05040404 }; |
| 1010 | u32 x38a[6] = { 0, 0x04040303, 0x04040303, 0x04040303, 0x07070605, 0x07070605 }; |
| 1011 | u32 x38e[6] = { 0, 0x06060505, 0x06060505, 0x06060505, 0x09090808, 0x09090808 }; |
| 1012 | u32 x392[6] = { 0, 0x02020202, 0x02020202, 0x02020202, 0x03030202, 0x03030202 }; |
| 1013 | u32 x396[6] = { 0, 0x03030202, 0x03030202, 0x03030202, 0x05040303, 0x05040303 }; |
| 1014 | u32 x39a[6] = { 0, 0x04040403, 0x04040403, 0x04040403, 0x07070605, 0x07070605 }; |
| 1015 | u32 x39e[6] = { 0, 0x06060505, 0x06060505, 0x06060505, 0x08080808, 0x08080808 }; |
| 1016 | u16 addr[6] = { 0x31c, 0x374, 0x3a2, 0x3d0, 0x3fe, 0x42c }; |
| 1017 | u8 bit[6] = { 0, 0, 1, 1, 0, 0 }; |
| 1018 | |
| 1019 | FOR_EACH_POPULATED_CHANNEL(s->dimms, i) { |
| 1020 | for (j = 0; j < 6; j++) { |
| 1021 | if (j == 0) { |
| 1022 | MCHBAR32(0x400*i + addr[j]) = |
| 1023 | (MCHBAR32(0x400*i + addr[j]) & ~0xff000) | 0xaa000; |
| 1024 | MCHBAR16(0x400*i + 0x320) = (MCHBAR16(0x400*i + 0x320) & ~0xffff) | 0x6666; |
| 1025 | for (k = 0; k < 8; k++) { |
| 1026 | MCHBAR32(0x400*i + addr[j] + 0xe + (k << 2)) = |
| 1027 | (MCHBAR32(0x400*i + addr[j] + 0xe + (k << 2)) & ~0x3f3f3f3f) | x32a[k]; |
| 1028 | MCHBAR32(0x400*i + addr[j] + 0x2e + (k << 2)) = |
| 1029 | (MCHBAR32(0x400*i + addr[j] + 0x2e + (k << 2)) & ~0x3f3f3f3f) | x32a[k]; |
| 1030 | } |
| 1031 | } else { |
| 1032 | MCHBAR16(0x400*i + addr[j]) = (MCHBAR16(0x400*i + addr[j]) & ~0xf000) | 0xa000; |
| 1033 | MCHBAR16(0x400*i + addr[j] + 4) = (MCHBAR16(0x400*i + addr[j] + 4) & ~0xffff) | |
| 1034 | x378[j]; |
| 1035 | MCHBAR32(0x400*i + addr[j] + 0xe) = |
| 1036 | (MCHBAR32(0x400*i + addr[j] + 0xe) & ~0x3f3f3f3f) | x382[j]; |
| 1037 | MCHBAR32(0x400*i + addr[j] + 0x12) = |
| 1038 | (MCHBAR32(0x400*i + addr[j] + 0x12) & ~0x3f3f3f3f) | x386[j]; |
| 1039 | MCHBAR32(0x400*i + addr[j] + 0x16) = |
| 1040 | (MCHBAR32(0x400*i + addr[j] + 0x16) & ~0x3f3f3f3f) | x38a[j]; |
| 1041 | MCHBAR32(0x400*i + addr[j] + 0x1a) = |
| 1042 | (MCHBAR32(0x400*i + addr[j] + 0x1a) & ~0x3f3f3f3f) | x38e[j]; |
| 1043 | MCHBAR32(0x400*i + addr[j] + 0x1e) = |
| 1044 | (MCHBAR32(0x400*i + addr[j] + 0x1e) & ~0x3f3f3f3f) | x392[j]; |
| 1045 | MCHBAR32(0x400*i + addr[j] + 0x22) = |
| 1046 | (MCHBAR32(0x400*i + addr[j] + 0x22) & ~0x3f3f3f3f) | x396[j]; |
| 1047 | MCHBAR32(0x400*i + addr[j] + 0x26) = |
| 1048 | (MCHBAR32(0x400*i + addr[j] + 0x26) & ~0x3f3f3f3f) | x39a[j]; |
| 1049 | MCHBAR32(0x400*i + addr[j] + 0x2a) = |
| 1050 | (MCHBAR32(0x400*i + addr[j] + 0x2a) & ~0x3f3f3f3f) | x39e[j]; |
| 1051 | } |
| 1052 | MCHBAR8(0x400*i + addr[j]) = (MCHBAR8(0x400*i + addr[j]) & ~1) | bit[j]; |
| 1053 | } |
| 1054 | MCHBAR8(0x400*i + 0x45a) = (MCHBAR8(0x400*i + 0x45a) & ~0x3f) | 0x12; |
| 1055 | MCHBAR8(0x400*i + 0x45e) = (MCHBAR8(0x400*i + 0x45e) & ~0x3f) | 0x12; |
| 1056 | MCHBAR8(0x400*i + 0x462) = (MCHBAR8(0x400*i + 0x462) & ~0x3f) | 0x12; |
| 1057 | MCHBAR8(0x400*i + 0x466) = (MCHBAR8(0x400*i + 0x466) & ~0x3f) | 0x12; |
| 1058 | } // END EACH POPULATED CHANNEL |
| 1059 | |
| 1060 | MCHBAR32(0x134) = (MCHBAR32(0x134) & ~0x63c00) | 0x63c00; |
| 1061 | MCHBAR16(0x174) = (MCHBAR16(0x174) & ~0x63ff) | 0x63ff; |
| 1062 | MCHBAR16(0x178) = 0x0135; |
| 1063 | MCHBAR32(0x130) = (MCHBAR32(0x130) & ~0x7bdffe0) | 0x7a9ffa0; |
| 1064 | |
| 1065 | if (!CHANNEL_IS_POPULATED(s->dimms, 0)) { |
| 1066 | MCHBAR32(0x130) = MCHBAR32(0x130) & ~(1 << 27); |
| 1067 | } |
| 1068 | if (!CHANNEL_IS_POPULATED(s->dimms, 1)) { |
| 1069 | MCHBAR32(0x130) = MCHBAR32(0x130) & ~(1 << 28); |
| 1070 | } |
| 1071 | |
| 1072 | MCHBAR8(0x130) = MCHBAR8(0x130) | 1; |
| 1073 | } |
| 1074 | |
| 1075 | static void odt_ddr2(struct sysinfo *s) |
| 1076 | { |
| 1077 | u8 i; |
| 1078 | u16 odt[16][2] = { |
| 1079 | { 0x0000,0x0000 }, // NC_NC |
| 1080 | { 0x0000,0x0001 }, // x8SS_NC |
| 1081 | { 0x0000,0x0011 }, // x8DS_NC |
| 1082 | { 0x0000,0x0001 }, // x16SS_NC |
| 1083 | { 0x0004,0x0000 }, // NC_x8SS |
| 1084 | { 0x0101,0x0404 }, // x8SS_x8SS |
| 1085 | { 0x0101,0x4444 }, // x8DS_x8SS |
| 1086 | { 0x0101,0x0404 }, // x16SS_x8SS |
| 1087 | { 0x0044,0x0000 }, // NC_x8DS |
| 1088 | { 0x1111,0x0404 }, // x8SS_x8DS |
| 1089 | { 0x1111,0x4444 }, // x8DS_x8DS |
| 1090 | { 0x1111,0x0404 }, // x16SS_x8DS |
| 1091 | { 0x0004,0x0000 }, // NC_x16SS |
| 1092 | { 0x0101,0x0404 }, // x8SS_x16SS |
| 1093 | { 0x0101,0x4444 }, // x8DS_x16SS |
| 1094 | { 0x0101,0x0404 }, // x16SS_x16SS |
| 1095 | }; |
| 1096 | |
| 1097 | FOR_EACH_POPULATED_CHANNEL(s->dimms, i) { |
| 1098 | MCHBAR16(0x400*i + 0x298) = odt[s->dimm_config[i]][1]; |
| 1099 | MCHBAR16(0x400*i + 0x294) = odt[s->dimm_config[i]][0]; |
| 1100 | MCHBAR16(0x400*i + 0x29c) = (MCHBAR16(0x400*i + 0x29c) & ~0xfff) | 0x66b; |
| 1101 | MCHBAR32(0x400*i + 0x260) = (MCHBAR32(0x400*i + 0x260) & ~0x70e3c00) | 0x3063c00; |
| 1102 | } |
| 1103 | } |
| 1104 | |
| 1105 | static void dojedec_ddr2(u8 r, u8 ch, u8 cmd, u16 val) |
| 1106 | { |
| 1107 | u32 addr = (ch << 29) | (r*0x08000000); |
| 1108 | volatile u32 rubbish; |
| 1109 | |
| 1110 | MCHBAR8(0x271) = (MCHBAR8(0x271) & ~0x3e) | cmd; |
| 1111 | MCHBAR8(0x671) = (MCHBAR8(0x671) & ~0x3e) | cmd; |
| 1112 | rubbish = read32((void*)((val<<3) | addr)); |
| 1113 | udelay(10); |
| 1114 | MCHBAR8(0x271) = (MCHBAR8(0x271) & ~0x3e) | NORMALOP_CMD; |
| 1115 | MCHBAR8(0x671) = (MCHBAR8(0x671) & ~0x3e) | NORMALOP_CMD; |
| 1116 | } |
| 1117 | |
| 1118 | static void jedec_ddr2(struct sysinfo *s) |
| 1119 | { |
| 1120 | u8 i; |
| 1121 | u16 mrsval, ch, r, v; |
| 1122 | |
| 1123 | u8 odt[16][4] = { |
| 1124 | {0x00, 0x00, 0x00, 0x00}, |
| 1125 | {0x01, 0x00, 0x00, 0x00}, |
| 1126 | {0x01, 0x01, 0x00, 0x00}, |
| 1127 | {0x01, 0x00, 0x00, 0x00}, |
| 1128 | {0x00, 0x00, 0x01, 0x00}, |
| 1129 | {0x11, 0x00, 0x11, 0x00}, |
| 1130 | {0x11, 0x11, 0x11, 0x00}, |
| 1131 | {0x11, 0x00, 0x11, 0x00}, |
| 1132 | {0x00, 0x00, 0x01, 0x01}, |
| 1133 | {0x11, 0x00, 0x11, 0x11}, |
| 1134 | {0x11, 0x11, 0x11, 0x11}, |
| 1135 | {0x11, 0x00, 0x11, 0x11}, |
| 1136 | {0x00, 0x00, 0x01, 0x00}, |
| 1137 | {0x11, 0x00, 0x11, 0x00}, |
| 1138 | {0x11, 0x11, 0x11, 0x00}, |
| 1139 | {0x11, 0x00, 0x11, 0x00} |
| 1140 | }; |
| 1141 | |
| 1142 | u16 jedec[12][2] = { |
| 1143 | {NOP_CMD, 0x0}, |
| 1144 | {PRECHARGE_CMD, 0x0}, |
| 1145 | {EMRS2_CMD, 0x0}, |
| 1146 | {EMRS3_CMD, 0x0}, |
| 1147 | {EMRS1_CMD, 0x0}, |
| 1148 | {MRS_CMD, 0x100}, // DLL Reset |
| 1149 | {PRECHARGE_CMD, 0x0}, |
| 1150 | {CBR_CMD, 0x0}, |
| 1151 | {CBR_CMD, 0x0}, |
| 1152 | {MRS_CMD, 0x0}, // DLL out of reset |
| 1153 | {EMRS1_CMD, 0x380}, // OCD calib default |
| 1154 | {EMRS1_CMD, 0x0} |
| 1155 | }; |
| 1156 | |
| 1157 | mrsval = (s->selected_timings.CAS << 4) | ((s->selected_timings.tWR - 1) << 9) | 0xb; |
| 1158 | |
| 1159 | printk(BIOS_DEBUG, "MRS...\n"); |
| 1160 | |
| 1161 | udelay(200); |
| 1162 | |
| 1163 | FOR_EACH_POPULATED_RANK(s->dimms, ch, r) { |
| 1164 | printk(BIOS_DEBUG, "CH%d: Found Rank %d\n", ch, r); |
| 1165 | for (i = 0; i < 12; i++) { |
| 1166 | v = jedec[i][1]; |
| 1167 | switch (jedec[i][0]) { |
| 1168 | case EMRS1_CMD: |
| 1169 | v |= (odt[s->dimm_config[ch]][r] << 2); |
| 1170 | break; |
| 1171 | case MRS_CMD: |
| 1172 | v |= mrsval; |
| 1173 | break; |
| 1174 | default: |
| 1175 | break; |
| 1176 | } |
| 1177 | dojedec_ddr2(r + ch*4, ch, jedec[i][0], v); |
| 1178 | udelay(1); |
| 1179 | //printk(BIOS_DEBUG, "Jedec step %d\n", i); |
| 1180 | } |
| 1181 | } |
| 1182 | printk(BIOS_DEBUG, "MRS done\n"); |
| 1183 | } |
| 1184 | |
| 1185 | static u8 sampledqs(u16 mchloc, u32 addr, u8 hilow, u8 repeat) |
| 1186 | { |
| 1187 | u8 dqsmatch = 1; |
| 1188 | volatile u32 strobe; |
| 1189 | |
| 1190 | while (repeat-- > 0) { |
| 1191 | MCHBAR8(0x5d8) = MCHBAR8(0x5d8) & ~0x2; |
| 1192 | udelay(2); |
| 1193 | MCHBAR8(0x5d8) = MCHBAR8(0x5d8) | 0x2; |
| 1194 | udelay(2); |
| 1195 | MCHBAR8(0x9d8) = MCHBAR8(0x9d8) & ~0x2; |
| 1196 | udelay(2); |
| 1197 | MCHBAR8(0x9d8) = MCHBAR8(0x9d8) | 0x2; |
| 1198 | udelay(2); |
| 1199 | barrier(); |
| 1200 | strobe = read32((u32 *)addr); |
| 1201 | barrier(); |
| 1202 | if (((MCHBAR32(mchloc) & 0x40) >> 6) != hilow) { |
| 1203 | dqsmatch = 0; |
| 1204 | } |
| 1205 | } |
| 1206 | return dqsmatch; |
| 1207 | } |
| 1208 | |
| 1209 | static void rcven_ddr2(struct sysinfo *s) |
| 1210 | { |
| 1211 | u8 i, reg8, ch, lane; |
| 1212 | u32 addr; |
| 1213 | u8 tap = 0; |
| 1214 | u8 savecc, savemedium, savetap, coarsecommon, medium; |
| 1215 | u8 lanecoarse[8] = {0}; |
| 1216 | u8 mincoarse = 0xff; |
| 1217 | u8 pitap[2][8]; |
| 1218 | u16 coarsectrl[2]; |
| 1219 | u16 coarsedelay[2]; |
| 1220 | u16 mediumphase[2]; |
| 1221 | u16 readdelay[2]; |
| 1222 | u16 mchbar; |
| 1223 | MCHBAR8(0x5d8) = MCHBAR8(0x5d8) & ~0xc; |
| 1224 | MCHBAR8(0x9d8) = MCHBAR8(0x9d8) & ~0xc; |
| 1225 | MCHBAR8(0x5dc) = MCHBAR8(0x5dc) & ~0x80; |
| 1226 | |
| 1227 | FOR_EACH_POPULATED_CHANNEL(s->dimms, ch) { |
| 1228 | addr = (ch << 29); |
| 1229 | for (i = 0; !RANK_IS_POPULATED(s->dimms, ch, i); i++) { |
| 1230 | addr += 128*1024*1024; |
| 1231 | } |
| 1232 | for (lane = 0; lane < 8; lane++) { |
| 1233 | printk(BIOS_DEBUG, "Channel %d, Lane %d addr=0x%08x\n", ch, lane, addr); |
| 1234 | coarsecommon = (s->selected_timings.CAS - 1); |
| 1235 | switch (lane) { |
| 1236 | case 0: case 1: medium = 0; break; |
| 1237 | case 2: case 3: medium = 1; break; |
| 1238 | case 4: case 5: medium = 2; break; |
| 1239 | case 6: case 7: medium = 3; break; |
| 1240 | default: medium = 0; break; |
| 1241 | } |
| 1242 | mchbar = 0x400*ch + 0x561 + (lane << 2); |
| 1243 | tap = 0; |
| 1244 | MCHBAR32(0x400*ch + 0x248) = (MCHBAR32(0x400*ch + 0x248) & ~0xf0000) | |
| 1245 | (coarsecommon << 16); |
| 1246 | MCHBAR16(0x400*ch + 0x58c) = (MCHBAR16(0x400*ch + 0x58c) & ~(3 << (lane*2))) | |
| 1247 | (medium << (lane*2)); |
| 1248 | MCHBAR8(0x400*ch + 0x560 + lane*4) = MCHBAR8(0x400*ch + 0x560 + lane*4) & ~0xf; |
| 1249 | MCHBAR8(0x400*ch + 0x560 + lane*4) = MCHBAR8(0x400*ch + 0x560 + lane*4) & ~0x70; |
| 1250 | savecc = coarsecommon; |
| 1251 | savemedium = medium; |
| 1252 | savetap = 0; |
| 1253 | |
| 1254 | MCHBAR16(0x400*ch + 0x588) = (MCHBAR16(0x400*ch + 0x588) & ~(3 << (lane*2))) | |
| 1255 | (1 << (lane*2)); |
| 1256 | |
| 1257 | printk(BIOS_DEBUG, "rcven 0.1 coarse=%d\n", coarsecommon); |
| 1258 | while (sampledqs(mchbar, addr, 1, 1) == 1) { |
| 1259 | if (medium < 3) { |
| 1260 | medium++; |
| 1261 | MCHBAR16(0x400*ch + 0x58c) = (MCHBAR16(0x400*ch + 0x58c) & |
| 1262 | ~(3 << (lane*2))) | (medium << (lane*2)); |
| 1263 | } else { |
| 1264 | medium = 0; |
| 1265 | coarsecommon++; |
| 1266 | MCHBAR32(0x400*ch + 0x248) = (MCHBAR32(0x400*ch + 0x248) & |
| 1267 | ~0xf0000) | (coarsecommon << 16); |
| 1268 | MCHBAR16(0x400*ch + 0x58c) = (MCHBAR16(0x400*ch + 0x58c) & |
| 1269 | ~(3 << (lane*2))) | (medium << (lane*2)); |
| 1270 | } |
| 1271 | if (coarsecommon > 16) { |
| 1272 | die("Coarse > 16: DQS tuning failed, halt\n"); |
| 1273 | break; |
| 1274 | } |
| 1275 | } |
| 1276 | printk(BIOS_DEBUG, " GOT IT (high -> low transition) coarse=%d medium=%d\n", coarsecommon, medium); |
| 1277 | |
| 1278 | savemedium = medium; |
| 1279 | savecc = coarsecommon; |
| 1280 | if (medium < 3) { |
| 1281 | medium++; |
| 1282 | MCHBAR16(0x400*ch + 0x58c) = (MCHBAR16(0x400*ch + 0x58c) & |
| 1283 | ~(3 << (lane*2))) | (medium << (lane*2)); |
| 1284 | } else { |
| 1285 | medium = 0; |
| 1286 | coarsecommon++; |
| 1287 | |
| 1288 | MCHBAR32(0x400*ch + 0x248) = (MCHBAR32(0x400*ch + 0x248) & ~0xf0000) | |
| 1289 | (coarsecommon << 16); |
| 1290 | MCHBAR16(0x400*ch + 0x58c) = (MCHBAR16(0x400*ch + 0x58c) & ~(3 << (lane*2))) | |
| 1291 | (medium << (lane*2)); |
| 1292 | } |
| 1293 | |
| 1294 | printk(BIOS_DEBUG, "rcven 0.2\n"); |
| 1295 | while (sampledqs(mchbar, addr, 0, 1) == 1) { |
| 1296 | savemedium = medium; |
| 1297 | savecc = coarsecommon; |
| 1298 | if (medium < 3) { |
| 1299 | medium++; |
| 1300 | MCHBAR16(0x400*ch + 0x58c) = (MCHBAR16(0x400*ch + 0x58c) & |
| 1301 | ~(3 << (lane*2))) | (medium << (lane*2)); |
| 1302 | } else { |
| 1303 | medium = 0; |
| 1304 | coarsecommon++; |
| 1305 | MCHBAR32(0x400*ch + 0x248) = (MCHBAR32(0x400*ch + 0x248) & |
| 1306 | ~0xf0000) | (coarsecommon << 16); |
| 1307 | MCHBAR16(0x400*ch + 0x58c) = (MCHBAR16(0x400*ch + 0x58c) & |
| 1308 | ~(3 << (lane*2))) | (medium << (lane*2)); |
| 1309 | } |
| 1310 | if (coarsecommon > 16) { |
| 1311 | die("Coarse DQS tuning 2 failed, halt\n"); |
| 1312 | break; |
| 1313 | } |
| 1314 | } |
| 1315 | printk(BIOS_DEBUG, " GOT IT (low -> high transition) coarse=%d medium=%d\n", coarsecommon, medium); |
| 1316 | |
| 1317 | |
| 1318 | coarsecommon = savecc; |
| 1319 | medium = savemedium; |
| 1320 | MCHBAR32(0x400*ch + 0x248) = (MCHBAR32(0x400*ch + 0x248) & |
| 1321 | ~0xf0000) | (coarsecommon << 16); |
| 1322 | MCHBAR16(0x400*ch + 0x58c) = (MCHBAR16(0x400*ch + 0x58c) & |
| 1323 | ~(3 << (lane*2))) | (medium << (lane*2)); |
| 1324 | |
| 1325 | printk(BIOS_DEBUG, "rcven 0.3\n"); |
| 1326 | tap = 0; |
| 1327 | while (sampledqs(mchbar, addr, 1, 1) == 0) { |
| 1328 | savetap = tap; |
| 1329 | tap++; |
| 1330 | if (tap > 14) { |
| 1331 | break; |
| 1332 | } |
| 1333 | MCHBAR8(0x400*ch + 0x560 + (lane*4)) = |
| 1334 | (MCHBAR8(0x400*ch + 0x560 + (lane*4)) & ~0xf) | tap; |
| 1335 | } |
| 1336 | |
| 1337 | tap = savetap; |
| 1338 | MCHBAR8(0x400*ch + 0x560 + (lane*4)) = |
| 1339 | (MCHBAR8(0x400*ch + 0x560 + (lane*4)) & ~0xf) | tap; |
| 1340 | MCHBAR8(0x400*ch + 0x560 + (lane*4)) = |
| 1341 | (MCHBAR8(0x400*ch + 0x560 + (lane*4)) & ~0x70) | 0x30; |
| 1342 | if (medium < 3) { |
| 1343 | medium++; |
| 1344 | MCHBAR16(0x400*ch + 0x58c) = (MCHBAR16(0x400*ch + 0x58c) & |
| 1345 | ~(3 << (lane*2))) | (medium << (lane*2)); |
| 1346 | } else { |
| 1347 | medium = 0; |
| 1348 | coarsecommon++; |
| 1349 | MCHBAR32(0x400*ch + 0x248) = (MCHBAR32(0x400*ch + 0x248) & |
| 1350 | ~0xf0000) | (coarsecommon << 16); |
| 1351 | MCHBAR16(0x400*ch + 0x58c) = (MCHBAR16(0x400*ch + 0x58c) & |
| 1352 | ~(3 << (lane*2))) | (medium << (lane*2)); |
| 1353 | } |
| 1354 | if (sampledqs(mchbar, addr, 1, 1) == 0) { |
| 1355 | die("Not at DQS high, doh\n"); |
| 1356 | } |
| 1357 | |
| 1358 | printk(BIOS_DEBUG, "rcven 0.4\n"); |
| 1359 | while (sampledqs(mchbar, addr, 1, 1) == 1) { |
| 1360 | coarsecommon--; |
| 1361 | MCHBAR32(0x400*ch + 0x248) = (MCHBAR32(0x400*ch + 0x248) & |
| 1362 | ~0xf0000) | (coarsecommon << 16); |
| 1363 | if (coarsecommon == 0) { |
| 1364 | die("Couldn't find DQS-high 0 indicator, halt\n"); |
| 1365 | break; |
| 1366 | } |
| 1367 | } |
| 1368 | printk(BIOS_DEBUG, " GOT IT (high -> low transition) coarse=%d medium=%d\n", coarsecommon, medium); |
| 1369 | |
| 1370 | printk(BIOS_DEBUG, "rcven 0.5\n"); |
| 1371 | while (sampledqs(mchbar, addr, 0, 1) == 1) { |
| 1372 | savemedium = medium; |
| 1373 | savecc = coarsecommon; |
| 1374 | if (medium < 3) { |
| 1375 | medium++; |
| 1376 | MCHBAR16(0x400*ch + 0x58c) = (MCHBAR16(0x400*ch + 0x58c) & |
| 1377 | ~(3 << (lane*2))) | (medium << (lane*2)); |
| 1378 | } else { |
| 1379 | medium = 0; |
| 1380 | coarsecommon++; |
| 1381 | MCHBAR32(0x400*ch + 0x248) = (MCHBAR32(0x400*ch + 0x248) & |
| 1382 | ~0xf0000) | (coarsecommon << 16); |
| 1383 | MCHBAR16(0x400*ch + 0x58c) = (MCHBAR16(0x400*ch + 0x58c) & |
| 1384 | ~(3 << (lane*2))) | (medium << (lane*2)); |
| 1385 | } |
| 1386 | if (coarsecommon > 16) { |
| 1387 | die("Coarse DQS tuning 5 failed, halt\n"); |
| 1388 | break; |
| 1389 | } |
| 1390 | } |
| 1391 | printk(BIOS_DEBUG, " GOT IT (low -> high transition) coarse=%d medium=%d\n", coarsecommon, medium); |
| 1392 | |
| 1393 | printk(BIOS_DEBUG, "rcven 0.6\n"); |
| 1394 | coarsecommon = savecc; |
| 1395 | medium = savemedium; |
| 1396 | MCHBAR32(0x400*ch + 0x248) = (MCHBAR32(0x400*ch + 0x248) & |
| 1397 | ~0xf0000) | (coarsecommon << 16); |
| 1398 | MCHBAR16(0x400*ch + 0x58c) = (MCHBAR16(0x400*ch + 0x58c) & |
| 1399 | ~(3 << (lane*2))) | (medium << (lane*2)); |
| 1400 | while (sampledqs(mchbar, addr, 1, 1) == 0) { |
| 1401 | savetap = tap; |
| 1402 | tap++; |
| 1403 | if (tap > 14) { |
| 1404 | break; |
| 1405 | } |
| 1406 | MCHBAR8(0x400*ch + 0x560 + lane*4) = |
| 1407 | (MCHBAR8(0x400*ch + 0x560 + lane*4) & ~0xf) | tap; |
| 1408 | } |
| 1409 | tap = savetap; |
| 1410 | MCHBAR8(0x400*ch + 0x560 + lane*4) = |
| 1411 | (MCHBAR8(0x400*ch + 0x560 + lane*4) & ~0xf) | tap; |
| 1412 | MCHBAR8(0x400*ch + 0x560 + lane*4) = |
| 1413 | (MCHBAR8(0x400*ch + 0x560 + lane*4) & ~0x70) | 0x70; |
| 1414 | |
| 1415 | pitap[ch][lane] = 0x70 | tap; |
| 1416 | |
| 1417 | MCHBAR16(0x400*ch + 0x588) = MCHBAR16(0x400*ch + 0x588) & ~(3 << (lane*2)); |
| 1418 | lanecoarse[lane] = coarsecommon; |
| 1419 | printk(BIOS_DEBUG, "rcven 0.7\n"); |
| 1420 | } // END EACH LANE |
| 1421 | |
| 1422 | // Find minimum coarse value |
| 1423 | for (lane = 0; lane < 8; lane++) { |
| 1424 | if (mincoarse > lanecoarse[lane]) { |
| 1425 | mincoarse = lanecoarse[lane]; |
| 1426 | } |
| 1427 | } |
| 1428 | |
| 1429 | printk(BIOS_DEBUG, "Found min coarse value = %d\n", mincoarse); |
| 1430 | |
| 1431 | for (lane = 0; lane < 8; lane++) { |
| 1432 | reg8 = (lanecoarse[lane] == 0) ? 0 : lanecoarse[lane] - mincoarse; |
| 1433 | MCHBAR16(0x400*ch + 0x5fa) = (MCHBAR16(0x400*ch + 0x5fa) & ~(3 << (lane*2))) | |
| 1434 | (reg8 << (lane*2)); |
| 1435 | } |
| 1436 | MCHBAR32(0x400*ch + 0x248) = (MCHBAR32(0x400*ch + 0x248) & ~0xf0000) | (mincoarse << 16); |
| 1437 | coarsectrl[ch] = mincoarse; |
| 1438 | coarsedelay[ch] = MCHBAR16(0x400*ch + 0x5fa); |
| 1439 | mediumphase[ch] = MCHBAR16(0x400*ch + 0x58c); |
| 1440 | readdelay[ch] = MCHBAR16(0x400*ch + 0x588); |
| 1441 | } // END EACH POPULATED CHANNEL |
| 1442 | |
| 1443 | /* TODO: Resume support using this */ |
| 1444 | FOR_EACH_CHANNEL(ch) { |
| 1445 | for (lane = 0; lane < 8; lane++) { |
| 1446 | MCHBAR8(0x400*ch + 0x560 + (lane*4)) = |
| 1447 | (MCHBAR8(0x400*ch + 0x560 + (lane*4)) & ~0xf) | pitap[ch][lane]; |
| 1448 | } |
| 1449 | MCHBAR32(0x400*ch + 0x248) = (MCHBAR32(0x400*ch + 0x248) & ~0xf0000) | |
| 1450 | (coarsectrl[ch] << 16); |
| 1451 | MCHBAR16(0x400*ch + 0x5fa) = coarsedelay[ch]; |
| 1452 | MCHBAR16(0x400*ch + 0x58c) = mediumphase[ch]; |
| 1453 | } |
| 1454 | printk(BIOS_DEBUG, "End rcven\n"); |
| 1455 | } |
| 1456 | |
| 1457 | static void dradrb_ddr2(struct sysinfo *s) |
| 1458 | { |
| 1459 | u8 map, i, ch, r, rankpop0, rankpop1; |
| 1460 | u32 c0dra = 0; |
| 1461 | u32 c1dra = 0; |
| 1462 | u32 c0drb = 0; |
| 1463 | u32 c1drb = 0; |
| 1464 | u32 dra; |
| 1465 | u32 dra0; |
| 1466 | u32 dra1; |
| 1467 | u16 totalmemorymb; |
| 1468 | u16 size, offset; |
| 1469 | u8 dratab[2][2][2][4] = { |
| 1470 | { |
| 1471 | { |
| 1472 | {0xff, 0xff, 0xff, 0xff}, |
| 1473 | {0xff, 0x00, 0x02, 0xff} |
| 1474 | }, |
| 1475 | { |
| 1476 | {0xff, 0x01, 0xff, 0xff}, |
| 1477 | {0xff, 0x03, 0xff, 0xff} |
| 1478 | } |
| 1479 | }, |
| 1480 | { |
| 1481 | { |
| 1482 | {0xff, 0xff, 0xff, 0xff}, |
| 1483 | {0xff, 0x04, 0x06, 0x08} |
| 1484 | }, |
| 1485 | { |
| 1486 | {0xff, 0xff, 0xff, 0xff}, |
| 1487 | {0x05, 0x07, 0x09, 0xff} |
| 1488 | } |
| 1489 | } |
| 1490 | }; |
| 1491 | |
| 1492 | u8 drbtab[10] = {0x04, 0x02, 0x08, 0x04, 0x08, 0x04, 0x10, 0x08, 0x20, 0x10}; |
| 1493 | |
| 1494 | // DRA |
| 1495 | rankpop0 = 0; |
| 1496 | rankpop1 = 0; |
| 1497 | FOR_EACH_POPULATED_RANK(s->dimms, ch, r) { |
| 1498 | if ((s->dimms[ch<<1].card_type && ((r) < s->dimms[ch<<1].ranks))) { |
| 1499 | i = ch << 1; |
| 1500 | } else { |
| 1501 | i = (ch << 1) + 1; |
| 1502 | } |
| 1503 | dra = dratab[s->dimms[i].banks] |
| 1504 | [s->dimms[i].width] |
| 1505 | [s->dimms[i].cols-9] |
| 1506 | [s->dimms[i].rows-12]; |
| 1507 | if (s->dimms[i].banks == 1) { |
| 1508 | dra |= 0x80; |
| 1509 | } |
| 1510 | if (ch == 0) { |
| 1511 | c0dra |= dra << (r*8); |
| 1512 | rankpop0 |= 1 << r; |
| 1513 | } else { |
| 1514 | c1dra |= dra << (r*8); |
| 1515 | rankpop1 |= 1 << r; |
| 1516 | } |
| 1517 | } |
| 1518 | MCHBAR32(0x208) = c0dra; |
| 1519 | MCHBAR32(0x608) = c1dra; |
| 1520 | |
| 1521 | MCHBAR8(0x262) = (MCHBAR8(0x262) & ~0xf0) | ((rankpop0 << 4) & 0xf0); |
| 1522 | MCHBAR8(0x662) = (MCHBAR8(0x662) & ~0xf0) | ((rankpop1 << 4) & 0xf0); |
| 1523 | |
| 1524 | if (ONLY_DIMMA_IS_POPULATED(s->dimms, 0) || ONLY_DIMMB_IS_POPULATED(s->dimms, 0)) { |
| 1525 | MCHBAR8(0x260) = MCHBAR8(0x260) | 1; |
| 1526 | } |
| 1527 | if (ONLY_DIMMA_IS_POPULATED(s->dimms, 1) || ONLY_DIMMB_IS_POPULATED(s->dimms, 1)) { |
| 1528 | MCHBAR8(0x660) = MCHBAR8(0x660) | 1; |
| 1529 | } |
| 1530 | |
| 1531 | // DRB |
| 1532 | FOR_EACH_POPULATED_RANK(s->dimms, ch, r) { |
| 1533 | if ((s->dimms[ch<<1].card_type && ((r) < s->dimms[ch<<1].ranks))) { |
| 1534 | i = ch << 1; |
| 1535 | } else { |
| 1536 | i = (ch << 1) + 1; |
| 1537 | } |
| 1538 | if (ch == 0) { |
| 1539 | dra0 = (c0dra >> (8*r)) & 0x7f; |
| 1540 | c0drb = (u16)(c0drb + drbtab[dra0]); |
| 1541 | s->dimms[i].rank_capacity_mb = drbtab[dra0] << 6; |
| 1542 | MCHBAR16(0x200 + 2*r) = c0drb; |
| 1543 | } else { |
| 1544 | dra1 = (c1dra >> (8*r)) & 0x7f; |
| 1545 | c1drb = (u16)(c1drb + drbtab[dra1]); |
| 1546 | s->dimms[i].rank_capacity_mb = drbtab[dra1] << 6; |
| 1547 | MCHBAR16(0x600 + 2*r) = c1drb; |
| 1548 | } |
| 1549 | } |
| 1550 | |
| 1551 | s->channel_capacity[0] = c0drb << 6; |
| 1552 | s->channel_capacity[1] = c1drb << 6; |
| 1553 | totalmemorymb = s->channel_capacity[0] + s->channel_capacity[1]; |
| 1554 | printk(BIOS_DEBUG, "Total memory: %d + %d = %dMiB\n", |
| 1555 | s->channel_capacity[0], s->channel_capacity[1], totalmemorymb); |
| 1556 | |
| 1557 | rankpop1 >>= 4; |
| 1558 | if (rankpop1) { |
| 1559 | MCHBAR16(0x600 + 2*msbpos(rankpop1)) = c0drb + c1drb; |
| 1560 | MCHBAR16(0x602 + 2*msbpos(rankpop1)) = c0drb + c1drb; |
| 1561 | MCHBAR16(0x604 + 2*msbpos(rankpop1)) = c0drb + c1drb; |
| 1562 | MCHBAR16(0x606 + 2*msbpos(rankpop1)) = c0drb + c1drb; |
| 1563 | } |
| 1564 | |
| 1565 | MCHBAR8(0x111) = MCHBAR8(0x111) | 0x2; |
| 1566 | MCHBAR16(0x104) = 0; |
| 1567 | size = s->channel_capacity[0] + s->channel_capacity[1]; |
| 1568 | MCHBAR16(0x102) = size; |
| 1569 | map = 0; |
| 1570 | if (s->channel_capacity[0] == 0) { |
| 1571 | map = 0; |
| 1572 | } else if (s->channel_capacity[1] == 0) { |
| 1573 | map |= 0x20; |
| 1574 | } else { |
| 1575 | map |= 0x40; |
| 1576 | } |
| 1577 | map |= 0x18; |
| 1578 | if (s->channel_capacity[0] <= s->channel_capacity[1]) { |
| 1579 | map |= 0x5; |
| 1580 | } else if (s->channel_capacity[0] > s->channel_capacity[1]) { |
| 1581 | map |= 0x4; |
| 1582 | } |
| 1583 | MCHBAR8(0x110) = map; |
| 1584 | MCHBAR16(0x10e) = 0; |
| 1585 | if (s->channel_capacity[1] != 0) { |
| 1586 | offset = 0; |
| 1587 | } else if (s->channel_capacity[0] > s->channel_capacity[1]) { |
| 1588 | offset = size; |
| 1589 | } else { |
| 1590 | offset = 0; |
| 1591 | } |
| 1592 | MCHBAR16(0x108) = offset; |
| 1593 | MCHBAR16(0x10a) = 0; |
| 1594 | } |
| 1595 | |
| 1596 | static void mmap_ddr2(struct sysinfo *s) |
| 1597 | { |
| 1598 | u32 gfxsize, gttsize, tsegsize, mmiosize, tom, tolud, touud, gfxbase, gttbase, tsegbase; |
| 1599 | u16 ggc; |
| 1600 | u16 ggc2uma[] = { 0, 0, 0, 0, 0, 32, 48, 64, 128, 256, 96, 160, 224, 352 }; |
| 1601 | u8 ggc2gtt[] = { 0, 1, 0, 2, 0, 0, 0, 0, 0, 2, 3, 4}; |
| 1602 | |
| 1603 | ggc = pci_read_config16(PCI_DEV(0,0,0), 0x52); |
| 1604 | gfxsize = ggc2uma[(ggc & 0xf0) >> 4]; |
| 1605 | gttsize = ggc2gtt[(ggc & 0xf00) >> 8]; |
| 1606 | tsegsize = 1; // 1MB TSEG |
| 1607 | mmiosize = 0x400; // 1GB MMIO |
| 1608 | tom = s->channel_capacity[0] + s->channel_capacity[1]; |
| 1609 | tolud = MIN(0x1000 - mmiosize, tom); |
| 1610 | touud = tom; |
| 1611 | gfxbase = tolud - gfxsize; |
| 1612 | gttbase = gfxbase - gttsize; |
| 1613 | tsegbase = gttbase - tsegsize; |
| 1614 | |
| 1615 | pci_write_config16(PCI_DEV(0,0,0), 0xb0, tolud << 4); |
| 1616 | pci_write_config16(PCI_DEV(0,0,0), 0xa0, tom >> 6); |
| 1617 | pci_write_config16(PCI_DEV(0,0,0), 0xa2, touud); |
| 1618 | pci_write_config32(PCI_DEV(0,0,0), 0xa4, gfxbase << 20); |
| 1619 | pci_write_config32(PCI_DEV(0,0,0), 0xa8, gttbase << 20); |
| 1620 | pci_write_config32(PCI_DEV(0,0,0), 0xac, tsegbase << 20); |
| 1621 | } |
| 1622 | |
| 1623 | static void enhanced_ddr2(struct sysinfo *s) |
| 1624 | { |
| 1625 | u8 ch, reg8; |
| 1626 | |
| 1627 | MCHBAR32(0xfb0) = 0x1000d024; |
| 1628 | MCHBAR32(0xfb4) = 0xc842; |
| 1629 | MCHBAR32(0xfbc) = 0xf; |
| 1630 | MCHBAR32(0xfc4) = 0xfe22244; |
| 1631 | MCHBAR8(0x12f) = 0x5c; |
| 1632 | MCHBAR8(0xfb0) = (MCHBAR8(0xfb0) & ~1) | 1; |
| 1633 | MCHBAR8(0x12f) = MCHBAR8(0x12f) | 0x2; |
| 1634 | MCHBAR8(0x6c0) = (MCHBAR8(0x6c0) & ~0xf0) | 0xa0; |
| 1635 | MCHBAR32(0xfa8) = 0x30d400; |
| 1636 | |
| 1637 | FOR_EACH_POPULATED_CHANNEL(s->dimms, ch) { |
| 1638 | MCHBAR8(0x400*ch + 0x26c) = MCHBAR8(0x400*ch + 0x26c) | 1; |
| 1639 | MCHBAR32(0x400*ch + 0x278) = 0x88141881; |
| 1640 | MCHBAR16(0x400*ch + 0x27c) = 0x0041; |
| 1641 | MCHBAR8(0x400*ch + 0x292) = 0xf2; |
| 1642 | MCHBAR16(0x400*ch + 0x272) = MCHBAR16(0x400*ch + 0x272) | 0x100; |
| 1643 | MCHBAR8(0x400*ch + 0x243) = (MCHBAR8(0x400*ch + 0x243) & ~0x2) | 1; |
| 1644 | MCHBAR32(0x400*ch + 0x288) = 0x8040200; |
| 1645 | MCHBAR32(0x400*ch + 0x28c) = 0xff402010; |
| 1646 | MCHBAR32(0x400*ch + 0x290) = 0x4f2091c; |
| 1647 | } |
| 1648 | |
| 1649 | reg8 = pci_read_config8(PCI_DEV(0,0,0), 0xf0); |
| 1650 | pci_write_config8(PCI_DEV(0,0,0), 0xf0, reg8 | 1); |
| 1651 | MCHBAR32(0xfa0) = (MCHBAR32(0xfa0) & ~0x20002) | 0x2; |
| 1652 | MCHBAR32(0xfa4) = (MCHBAR32(0xfa4) & ~0x219100c3) | 0x219100c2; |
| 1653 | MCHBAR32(0x2c) = 0x44a53; |
| 1654 | MCHBAR32(0x30) = 0x1f5a86; |
| 1655 | MCHBAR32(0x34) = 0x1902810; |
| 1656 | MCHBAR32(0x38) = 0xf7000000; |
| 1657 | MCHBAR32(0x3c) = 0x23014410; |
| 1658 | MCHBAR32(0x40) = (MCHBAR32(0x40) & ~0x8f038000) | 0x8f038000; |
| 1659 | MCHBAR32(0x20) = 0x33001; |
| 1660 | pci_write_config8(PCI_DEV(0,0,0), 0xf0, reg8 & ~1); |
| 1661 | } |
| 1662 | |
| 1663 | static void power_ddr2(struct sysinfo *s) |
| 1664 | { |
| 1665 | u32 reg1, reg2, reg3, reg4, clkgate, x592; |
| 1666 | u8 lane, ch; |
| 1667 | u8 twl = 0; |
| 1668 | u16 x264, x23c; |
| 1669 | |
| 1670 | twl = s->selected_timings.CAS - 1; |
| 1671 | x264 = 0x78; |
| 1672 | switch (s->selected_timings.mem_clk) { |
| 1673 | default: |
| 1674 | case MEM_CLOCK_667MHz: |
| 1675 | reg1 = 0x99; |
| 1676 | reg2 = 0x1048a9; |
| 1677 | clkgate = 0x230000; |
| 1678 | x23c = 0x7a89; |
| 1679 | break; |
| 1680 | case MEM_CLOCK_800MHz: |
| 1681 | if (s->selected_timings.CAS == 5) { |
| 1682 | reg1 = 0x19a; |
| 1683 | reg2 = 0x1048aa; |
| 1684 | } else { |
| 1685 | reg1 = 0x9a; |
| 1686 | reg2 = 0x2158aa; |
| 1687 | x264 = 0x89; |
| 1688 | } |
| 1689 | clkgate = 0x280000; |
| 1690 | x23c = 0x7b89; |
| 1691 | break; |
| 1692 | } |
| 1693 | reg3 = 0x232; |
| 1694 | reg4 = 0x2864; |
| 1695 | |
| 1696 | if (CHANNEL_IS_POPULATED(s->dimms, 0) && CHANNEL_IS_POPULATED(s->dimms, 1)) { |
| 1697 | MCHBAR32(0x14) = 0x0010461f; |
| 1698 | } else { |
| 1699 | MCHBAR32(0x14) = 0x0010691f; |
| 1700 | } |
| 1701 | MCHBAR32(0x18) = 0xdf6437f7; |
| 1702 | MCHBAR32(0x1c) = 0x0; |
| 1703 | MCHBAR32(0x24) = (MCHBAR32(0x24) & ~0xe0000000) | 0x30000000; |
| 1704 | MCHBAR32(0x44) = (MCHBAR32(0x44) & ~0x1fef0000) | 0x6b0000; |
| 1705 | MCHBAR16(0x115) = (u16) reg1; |
| 1706 | MCHBAR32(0x117) = (MCHBAR32(0x117) & ~0xffffff) | reg2; |
| 1707 | MCHBAR8(0x124) = 0x7; |
| 1708 | MCHBAR16(0x12a) = (MCHBAR16(0x12a) & 0) | 0x80; |
| 1709 | MCHBAR8(0x12c) = (MCHBAR8(0x12c) & 0) | 0xa0; |
| 1710 | MCHBAR16(0x174) = MCHBAR16(0x174) & ~(1 << 15); |
| 1711 | MCHBAR16(0x188) = (MCHBAR16(0x188) & ~0x1f00) | 0x1f00; |
| 1712 | MCHBAR8(0x18c) = MCHBAR8(0x18c) & ~0x8; |
| 1713 | MCHBAR8(0x192) = (MCHBAR8(0x192) & ~1) | 1; |
| 1714 | MCHBAR8(0x193) = (MCHBAR8(0x193) & ~0xf) | 0xf; |
| 1715 | MCHBAR16(0x1b4) = (MCHBAR16(0x1b4) & ~0x480) | 0x80; |
| 1716 | MCHBAR16(0x210) = (MCHBAR16(0x210) & ~0x1fff) | 0x3f; // | clockgatingiii |
| 1717 | MCHBAR32(0x6d1) = (MCHBAR32(0x6d1) & ~0xff03ff) | 0x100 | clkgate; |
| 1718 | MCHBAR8(0x212) = (MCHBAR8(0x212) & ~0x7f) | 0x7f; |
| 1719 | MCHBAR32(0x2c0) = (MCHBAR32(0x2c0) & ~0xffff0) | 0xcc5f0; |
| 1720 | MCHBAR8(0x2c4) = (MCHBAR8(0x2c4) & ~0x70) | 0x70; |
| 1721 | MCHBAR32(0x2d1) = (MCHBAR32(0x2d1) & ~0xffffff) | 0xff2831; // | clockgatingi |
| 1722 | MCHBAR32(0x2d4) = 0x40453600; |
| 1723 | MCHBAR32(0x300) = 0xc0b0a08; |
| 1724 | MCHBAR32(0x304) = 0x6040201; |
| 1725 | MCHBAR32(0x30c) = (MCHBAR32(0x30c) & ~0x43c0f) | 0x41405; |
| 1726 | MCHBAR16(0x610) = 0x232; |
| 1727 | MCHBAR16(0x612) = 0x2864; |
| 1728 | MCHBAR32(0x62c) = (MCHBAR32(0x62c) & ~0xc000000) | 0x4000000; |
| 1729 | MCHBAR32(0xae4) = 0; |
| 1730 | MCHBAR32(0xc00) = (MCHBAR32(0xc00) & ~0xf0000) | 0x10000; |
| 1731 | MCHBAR32(0xf00) = 0x393a3b3c; |
| 1732 | MCHBAR32(0xf04) = 0x3d3e3f40; |
| 1733 | MCHBAR32(0xf08) = 0x393a3b3c; |
| 1734 | MCHBAR32(0xf0c) = 0x3d3e3f40; |
| 1735 | MCHBAR32(0xf18) = MCHBAR32(0xf18) & ~0xfff00001; |
| 1736 | MCHBAR32(0xf48) = 0xfff0ffe0; |
| 1737 | MCHBAR32(0xf4c) = 0xffc0ff00; |
| 1738 | MCHBAR32(0xf50) = 0xfc00f000; |
| 1739 | MCHBAR32(0xf54) = 0xc0008000; |
| 1740 | MCHBAR32(0xf6c) = (MCHBAR32(0xf6c) & ~0xffff0000) | 0xffff0000; |
| 1741 | MCHBAR32(0xfac) = MCHBAR32(0xfac) & ~0x80000000; |
| 1742 | MCHBAR32(0xfb8) = MCHBAR32(0xfb8) & ~0xff000000; |
| 1743 | MCHBAR32(0xfbc) = (MCHBAR32(0xfbc) & ~0x7f800) | 0xf000; |
| 1744 | MCHBAR32(0x1104) = 0x3003232; |
| 1745 | MCHBAR32(0x1108) = 0x74; |
| 1746 | if (s->selected_timings.fsb_clk == FSB_CLOCK_800MHz) { |
| 1747 | MCHBAR32(0x110c) = 0xaa; |
| 1748 | } else { |
| 1749 | MCHBAR32(0x110c) = 0x100; |
| 1750 | } |
| 1751 | MCHBAR32(0x1110) = 0x10810350 & ~0x78; |
| 1752 | MCHBAR32(0x1114) = 0; |
| 1753 | if (s->selected_timings.mem_clk == MEM_CLOCK_667MHz) { |
| 1754 | twl = 5; |
| 1755 | } else { |
| 1756 | twl = 6; |
| 1757 | } |
| 1758 | x592 = 0xff; |
| 1759 | if (pci_read_config8(PCI_DEV(0,0,0), 0x8) < 3) { |
| 1760 | x592 = ~0x4; |
| 1761 | } |
| 1762 | FOR_EACH_POPULATED_CHANNEL(s->dimms, ch) { |
| 1763 | MCHBAR8(0x400*ch + 0x239) = twl + 15; |
| 1764 | MCHBAR16(0x400*ch + 0x23c) = x23c; |
| 1765 | MCHBAR32(0x400*ch + 0x248) = (MCHBAR32(0x400*ch + 0x248) & ~0x706033) | 0x406033; |
| 1766 | MCHBAR32(0x400*ch + 0x260) = (MCHBAR32(0x400*ch + 0x260) & ~(1 << 16)) | (1 << 16); |
| 1767 | MCHBAR8(0x400*ch + 0x264) = x264; |
| 1768 | MCHBAR8(0x400*ch + 0x592) = (MCHBAR8(0x400*ch + 0x592) & ~0x3f) | (0x3c & x592); |
| 1769 | MCHBAR8(0x400*ch + 0x593) = (MCHBAR8(0x400*ch + 0x593) & ~0x1f) | 0x1e; |
| 1770 | } |
| 1771 | |
| 1772 | for (lane = 0; lane < 8; lane++) { |
| 1773 | MCHBAR8(0x561 + (lane << 2)) = MCHBAR8(0x561 + (lane << 2)) & ~(1 << 3); |
| 1774 | } |
| 1775 | } |
| 1776 | |
| 1777 | void raminit_ddr2(struct sysinfo *s) |
| 1778 | { |
| 1779 | u8 ch; |
| 1780 | u8 r, bank; |
| 1781 | u32 reg32; |
| 1782 | |
| 1783 | // Select timings based on SPD info |
| 1784 | sdram_detect_smallest_params2(s); |
| 1785 | |
| 1786 | // Reset if required |
| 1787 | checkreset_ddr2(s); |
| 1788 | |
| 1789 | // Clear self refresh |
| 1790 | MCHBAR32(0xf14) = MCHBAR32(0xf14) | 0x3; |
| 1791 | |
| 1792 | // Clear host clk gate reg |
| 1793 | MCHBAR32(0x1c) = MCHBAR32(0x1c) | 0xffffffff; |
| 1794 | |
| 1795 | // Select DDR2 |
| 1796 | MCHBAR8(0x1a8) = MCHBAR8(0x1a8) & ~0x4; |
| 1797 | |
| 1798 | // Set freq |
| 1799 | MCHBAR32(0xc00) = (MCHBAR32(0xc00) & ~0x70) | |
| 1800 | (s->selected_timings.mem_clk << 4) | (1 << 10); |
| 1801 | |
| 1802 | // Overwrite freq if chipset rejects it |
| 1803 | s->selected_timings.mem_clk = (MCHBAR8(0xc00) & 0x70) >> 4; |
| 1804 | if (s->selected_timings.mem_clk > (s->max_fsb + 3)) { |
| 1805 | die("Error: DDR is faster than FSB, halt\n"); |
| 1806 | } |
| 1807 | |
| 1808 | udelay(250000); |
| 1809 | |
| 1810 | // Program clock crossing |
| 1811 | clkcross_ddr2(s); |
| 1812 | printk(BIOS_DEBUG, "Done clk crossing\n"); |
| 1813 | |
| 1814 | // DDR2 IO |
| 1815 | setioclk_ddr2(s); |
| 1816 | printk(BIOS_DEBUG, "Done I/O clk\n"); |
| 1817 | |
| 1818 | // Grant to launch |
| 1819 | launch_ddr2(s); |
| 1820 | printk(BIOS_DEBUG, "Done launch\n"); |
| 1821 | |
| 1822 | // Program DDR2 timings |
| 1823 | timings_ddr2(s); |
| 1824 | printk(BIOS_DEBUG, "Done timings\n"); |
| 1825 | |
| 1826 | // Program DLL |
| 1827 | dll_ddr2(s); |
| 1828 | |
| 1829 | // RCOMP |
| 1830 | rcomp_ddr2(s); |
| 1831 | printk(BIOS_DEBUG, "RCOMP\n"); |
| 1832 | |
| 1833 | // ODT |
| 1834 | odt_ddr2(s); |
| 1835 | printk(BIOS_DEBUG, "Done ODT\n"); |
| 1836 | |
| 1837 | // RCOMP update |
| 1838 | while ((MCHBAR8(0x130) & 1) != 0 ); |
| 1839 | printk(BIOS_DEBUG, "Done RCOMP update\n"); |
| 1840 | |
| 1841 | // Set defaults |
| 1842 | MCHBAR32(0x260) = (MCHBAR32(0x260) & ~1) | 0xf00000; |
| 1843 | MCHBAR32(0x660) = (MCHBAR32(0x660) & ~1) | 0xf00000; |
| 1844 | MCHBAR32(0x208) = 0x01010101; |
| 1845 | MCHBAR32(0x608) = 0x01010101; |
| 1846 | MCHBAR32(0x200) = 0x00040002; |
| 1847 | MCHBAR32(0x204) = 0x00080006; |
| 1848 | MCHBAR32(0x600) = 0x00040002; |
| 1849 | MCHBAR32(0x604) = 0x00100006; |
| 1850 | MCHBAR8(0x111) = MCHBAR8(0x111) | 0x2; |
| 1851 | MCHBAR32(0x104) = 0; |
| 1852 | MCHBAR16(0x102) = 0x400; |
| 1853 | MCHBAR8(0x100) = (2 << 5) | (3 << 3); |
| 1854 | MCHBAR16(0x10e) = 0; |
| 1855 | MCHBAR32(0x108) = 0; |
| 1856 | pci_write_config16(PCI_DEV(0,0,0), 0xb0, 0x4000); |
| 1857 | pci_write_config16(PCI_DEV(0,0,0), 0xa0, 0x0010); |
| 1858 | pci_write_config16(PCI_DEV(0,0,0), 0xa2, 0x0400); |
| 1859 | pci_write_config32(PCI_DEV(0,0,0), 0xa4, 0x40000000); |
| 1860 | pci_write_config32(PCI_DEV(0,0,0), 0xa8, 0x40000000); |
| 1861 | pci_write_config32(PCI_DEV(0,0,0), 0xac, 0x40000000); |
| 1862 | |
| 1863 | // IOBUFACT |
| 1864 | if (CHANNEL_IS_POPULATED(s->dimms, 0)) { |
| 1865 | MCHBAR8(0x5dd) = (MCHBAR8(0x5dd) & ~0x3f) | 0x3f; |
| 1866 | MCHBAR8(0x5d8) = MCHBAR8(0x5d8) | 0x7; |
| 1867 | } |
| 1868 | if (CHANNEL_IS_POPULATED(s->dimms, 1)) { |
| 1869 | if (pci_read_config8(PCI_DEV(0,0,0), 0x8) < 2) { |
| 1870 | MCHBAR8(0x5dd) = (MCHBAR8(0x5dd) & ~0x3f) | 0x3f; |
| 1871 | MCHBAR8(0x5d8) = MCHBAR8(0x5d8) | 1; |
| 1872 | } |
| 1873 | MCHBAR8(0x9dd) = (MCHBAR8(0x9dd) & ~0x3f) | 0x3f; |
| 1874 | MCHBAR8(0x9d8) = MCHBAR8(0x9d8) | 0x7; |
| 1875 | } |
| 1876 | |
| 1877 | // Pre jedec |
| 1878 | MCHBAR8(0x40) = MCHBAR8(0x40) | 0x2; |
| 1879 | FOR_EACH_POPULATED_CHANNEL(s->dimms, ch) { |
| 1880 | MCHBAR32(0x400*ch + 0x260) = MCHBAR32(0x400*ch + 0x260) | (1 << 27); |
| 1881 | } |
| 1882 | MCHBAR16(0x212) = (MCHBAR16(0x212) & ~0xf000) | 0xf000; |
| 1883 | MCHBAR16(0x212) = (MCHBAR16(0x212) & ~0xf00) | 0xf00; |
| 1884 | printk(BIOS_DEBUG, "Done pre-jedec\n"); |
| 1885 | |
| 1886 | // JEDEC reset |
| 1887 | jedec_ddr2(s); |
| 1888 | |
| 1889 | printk(BIOS_DEBUG, "Done jedec steps\n"); |
| 1890 | |
| 1891 | // After JEDEC reset |
| 1892 | MCHBAR8(0x40) = MCHBAR8(0x40) & ~0x2; |
| 1893 | FOR_EACH_POPULATED_CHANNEL(s->dimms, ch) { |
| 1894 | if (s->selected_timings.mem_clk == MEM_CLOCK_667MHz) { |
| 1895 | reg32 = (2 << 18) | (3 << 13) | (5 << 8); |
| 1896 | } else { |
| 1897 | reg32 = (2 << 18) | (3 << 13) | (4 << 8); |
| 1898 | } |
| 1899 | MCHBAR32(0x400*ch + 0x274) = (MCHBAR32(0x400*ch + 0x274) & ~0xfff00) | reg32; |
| 1900 | MCHBAR8(0x400*ch + 0x274) = MCHBAR8(0x400*ch + 0x274) & ~0x80; |
| 1901 | MCHBAR8(0x400*ch + 0x26c) = MCHBAR8(0x400*ch + 0x26c) | 1; |
| 1902 | MCHBAR32(0x400*ch + 0x278) = 0x88141881; |
| 1903 | MCHBAR16(0x400*ch + 0x27c) = 0x41; |
| 1904 | MCHBAR8(0x400*ch + 0x292) = 0xf2; |
| 1905 | MCHBAR8(0x400*ch + 0x271) = (MCHBAR8(0x400*ch + 0x271) & ~0xe) | 0xe; |
| 1906 | } |
| 1907 | MCHBAR8(0x2c4) = MCHBAR8(0x2c4) | 0x8; |
| 1908 | MCHBAR8(0x2c3) = MCHBAR8(0x2c3) | 0x40; |
| 1909 | MCHBAR8(0x2c4) = MCHBAR8(0x2c4) | 0x4; |
| 1910 | |
| 1911 | printk(BIOS_DEBUG, "Done post-jedec\n"); |
| 1912 | |
| 1913 | // Set DDR2 init complete |
| 1914 | FOR_EACH_POPULATED_CHANNEL(s->dimms, ch) { |
| 1915 | MCHBAR32(0x400*ch + 0x268) = (MCHBAR32(0x400*ch + 0x268) & ~0xc0000000) | 0xc0000000; |
| 1916 | } |
| 1917 | |
| 1918 | // Receive enable |
| 1919 | rcven_ddr2(s); |
| 1920 | printk(BIOS_DEBUG, "Done rcven\n"); |
| 1921 | |
| 1922 | // Finish rcven |
| 1923 | FOR_EACH_CHANNEL(ch) { |
| 1924 | MCHBAR8(0x400*ch + 0x5d8) = MCHBAR8(0x400*ch + 0x5d8) & ~0xe; |
| 1925 | MCHBAR8(0x400*ch + 0x5d8) = MCHBAR8(0x400*ch + 0x5d8) | 0x2; |
| 1926 | MCHBAR8(0x400*ch + 0x5d8) = MCHBAR8(0x400*ch + 0x5d8) | 0x4; |
| 1927 | MCHBAR8(0x400*ch + 0x5d8) = MCHBAR8(0x400*ch + 0x5d8) | 0x8; |
| 1928 | } |
| 1929 | MCHBAR8(0x5dc) = MCHBAR8(0x5dc) | 0x80; |
| 1930 | MCHBAR8(0x5dc) = MCHBAR8(0x5dc) & ~0x80; |
| 1931 | MCHBAR8(0x5dc) = MCHBAR8(0x5dc) | 0x80; |
| 1932 | |
| 1933 | // Dummy writes / reads |
| 1934 | volatile u32 data; |
| 1935 | FOR_EACH_POPULATED_RANK(s->dimms, ch, r) { |
| 1936 | for (bank = 0; bank < 4; bank++) { |
| 1937 | reg32 = (ch << 29) | (r*0x8000000) | (bank << 12); |
| 1938 | write32((u32 *)reg32, 0xffffffff); |
| 1939 | data = read32((u32 *)reg32); |
| 1940 | printk(BIOS_DEBUG, "Wrote ones, Read: [0x%08x]=0x%08x\n", reg32, data); |
| 1941 | write32((u32 *)reg32, 0x00000000); |
| 1942 | data = read32((u32 *)reg32); |
| 1943 | printk(BIOS_DEBUG, "Wrote zeros, Read: [0x%08x]=0x%08x\n", reg32, data); |
| 1944 | } |
| 1945 | } |
| 1946 | printk(BIOS_DEBUG, "Done dummy reads\n"); |
| 1947 | |
| 1948 | // XXX tRD |
| 1949 | |
| 1950 | // XXX Write training |
| 1951 | |
| 1952 | // XXX Read training |
| 1953 | |
| 1954 | // DRADRB |
| 1955 | dradrb_ddr2(s); |
| 1956 | printk(BIOS_DEBUG, "Done DRADRB\n"); |
| 1957 | |
| 1958 | // Memory map |
| 1959 | mmap_ddr2(s); |
| 1960 | printk(BIOS_DEBUG, "Done memory map\n"); |
| 1961 | |
| 1962 | // Enhanced mode |
| 1963 | enhanced_ddr2(s); |
| 1964 | printk(BIOS_DEBUG, "Done enhanced mode\n"); |
| 1965 | |
| 1966 | // Periodic RCOMP |
| 1967 | MCHBAR16(0x160) = (MCHBAR16(0x160) & ~0xfff) | 0x999; |
| 1968 | MCHBAR16(0x1b4) = MCHBAR16(0x1b4) | 0x3000; |
| 1969 | MCHBAR8(0x130) = MCHBAR8(0x130) | 0x82; |
| 1970 | printk(BIOS_DEBUG, "Done PRCOMP\n"); |
| 1971 | |
| 1972 | // Power settings |
| 1973 | power_ddr2(s); |
| 1974 | printk(BIOS_DEBUG, "Done power settings\n"); |
| 1975 | |
| 1976 | // ME related |
| 1977 | //MCHBAR32(0xa30) = MCHBAR32(0xa30) | (1 << 26); |
| 1978 | |
| 1979 | printk(BIOS_DEBUG, "Done ddr2\n"); |
| 1980 | } |