Michał Żygowski | 90989b3 | 2022-04-07 15:16:46 +0200 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
| 2 | |
| 3 | #include <assert.h> |
| 4 | #include <console/console.h> |
| 5 | #include <fsp/api.h> |
| 6 | #include <soc/romstage.h> |
| 7 | #include <soc/meminit.h> |
| 8 | |
Michał Żygowski | c354f31 | 2022-04-15 18:19:19 +0200 | [diff] [blame] | 9 | #include "gpio.h" |
| 10 | |
Michał Żygowski | 90989b3 | 2022-04-07 15:16:46 +0200 | [diff] [blame] | 11 | static const struct mb_cfg ddr4_mem_config = { |
| 12 | .type = MEM_TYPE_DDR4, |
| 13 | |
Michał Żygowski | 02db6b4 | 2022-04-08 17:12:13 +0200 | [diff] [blame] | 14 | /* According to DOC #573387 rcomp values no longer have to be provided */ |
| 15 | /* DDR DIMM configuration does not need to set DQ/DQS maps */ |
Michał Żygowski | 90989b3 | 2022-04-07 15:16:46 +0200 | [diff] [blame] | 16 | |
| 17 | .UserBd = BOARD_TYPE_DESKTOP_2DPC, /* FIXME */ |
| 18 | |
| 19 | .ddr_config = { |
Michał Żygowski | 02db6b4 | 2022-04-08 17:12:13 +0200 | [diff] [blame] | 20 | .dq_pins_interleaved = true, |
Michał Żygowski | 90989b3 | 2022-04-07 15:16:46 +0200 | [diff] [blame] | 21 | }, |
| 22 | }; |
| 23 | |
| 24 | static const struct mem_spd dimm_module_spd_info = { |
| 25 | .topo = MEM_TOPO_DIMM_MODULE, |
| 26 | .smbus = { |
| 27 | [0] = { |
| 28 | .addr_dimm[0] = 0x50, |
| 29 | .addr_dimm[1] = 0x51, |
| 30 | }, |
| 31 | [1] = { |
| 32 | .addr_dimm[0] = 0x52, |
| 33 | .addr_dimm[1] = 0x53, |
| 34 | }, |
| 35 | }, |
| 36 | }; |
| 37 | |
| 38 | void mainboard_memory_init_params(FSPM_UPD *memupd) |
| 39 | { |
Michał Żygowski | c354f31 | 2022-04-15 18:19:19 +0200 | [diff] [blame] | 40 | memupd->FspmConfig.CpuPcieRpClockReqMsgEnable[0] = 1; |
| 41 | memupd->FspmConfig.CpuPcieRpClockReqMsgEnable[1] = 1; |
| 42 | memupd->FspmConfig.CpuPcieRpClockReqMsgEnable[2] = 0; |
| 43 | memupd->FspmConfig.DmiMaxLinkSpeed = 4; // Gen4 speed, undocumented |
| 44 | memupd->FspmConfig.SkipExtGfxScan = 0; |
| 45 | |
| 46 | memupd->FspmConfig.PchHdaAudioLinkHdaEnable = 1; |
| 47 | memupd->FspmConfig.PchHdaSdiEnable[0] = 1; |
| 48 | |
| 49 | /* |
| 50 | * Let FSP configure virtual wires, CLKREQs, etc. |
| 51 | * Otherwise undefined behaviour occurs when coreboot enables ASPM on |
| 52 | * CPU PCIe root ports. This is caused by FSP reprogramming certain |
| 53 | * pads including CLKREQ pins, despite GpioOverride = 1. |
| 54 | */ |
| 55 | memupd->FspmConfig.GpioOverride = 0; |
| 56 | |
Michał Żygowski | 90989b3 | 2022-04-07 15:16:46 +0200 | [diff] [blame] | 57 | memcfg_init(memupd, &ddr4_mem_config, &dimm_module_spd_info, false); |
Michał Żygowski | c354f31 | 2022-04-15 18:19:19 +0200 | [diff] [blame] | 58 | |
| 59 | gpio_configure_pads(gpio_table, ARRAY_SIZE(gpio_table)); |
Michał Żygowski | 90989b3 | 2022-04-07 15:16:46 +0200 | [diff] [blame] | 60 | } |