Kapil Porwal | 93b7fd1 | 2023-02-25 22:23:01 +0530 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
| 2 | |
| 3 | #include <acpi/acpigen.h> |
| 4 | #include <acpi/acpi_device.h> |
| 5 | #include <acpi/acpi_soundwire.h> |
| 6 | #include <device/device.h> |
Kapil Porwal | 93b7fd1 | 2023-02-25 22:23:01 +0530 | [diff] [blame] | 7 | #include <device/soundwire.h> |
| 8 | #include <mipi/ids.h> |
| 9 | #include <stdio.h> |
| 10 | |
| 11 | #include "chip.h" |
| 12 | |
| 13 | static struct soundwire_address cs42l42_address = { |
| 14 | .version = SOUNDWIRE_VERSION_1_0, |
| 15 | .manufacturer_id = MIPI_MFG_ID_CIRRUS, |
| 16 | .part_id = MIPI_DEV_ID_CIRRUS_CS42L42, |
| 17 | .class = MIPI_CLASS_NONE |
| 18 | }; |
| 19 | |
| 20 | static struct soundwire_slave cs42l42_slave = { |
| 21 | .wake_up_unavailable = false, |
| 22 | .test_mode_supported = false, |
| 23 | .clock_stop_mode1_supported = true, |
| 24 | .simplified_clockstopprepare_sm_supported = false, |
| 25 | .clockstopprepare_hard_reset_behavior = true, |
| 26 | .highPHY_capable = false, |
| 27 | .paging_supported = true, |
| 28 | .bank_delay_supported = true, |
| 29 | .port15_read_behavior = false, |
| 30 | .source_port_list = SOUNDWIRE_PORT(1), |
| 31 | .sink_port_list = SOUNDWIRE_PORT(2) | SOUNDWIRE_PORT(3) |
| 32 | }; |
| 33 | |
| 34 | static struct soundwire_bra_mode cs42l42_dp0_bra_mode = { |
| 35 | .bus_frequency_configs_count = 6, |
| 36 | .bus_frequency_configs = { |
| 37 | 11289600, /* 11.2896 MHz */ |
| 38 | 12000 * KHz, /* 12 MHz */ |
| 39 | 12288 * KHz, /* 12.288 MHz */ |
| 40 | 22579200, /* 22.5792 MHz */ |
| 41 | 24000 * KHz, /* 24 MHz */ |
| 42 | 24576 * KHz, /* 24.576 MHz */ |
| 43 | }, |
| 44 | .max_data_per_frame = 4096, /* MaxRow*MaxCol = 256*16 = 4096 */ |
| 45 | .min_us_between_transactions = 0 |
| 46 | }; |
| 47 | |
| 48 | static struct soundwire_dp0 cs42l42_dp0 = { |
| 49 | .port_max_wordlength = 64, |
| 50 | .port_min_wordlength = 1, |
| 51 | .bra_imp_def_response_supported = false, |
| 52 | .simplified_channel_prepare_sm = true, |
| 53 | .imp_def_dp0_interrupts_supported = 0, |
| 54 | .imp_def_bpt_supported = true, |
| 55 | .bra_mode_count = 1, |
| 56 | .bra_mode_list = { 0 } |
| 57 | }; |
| 58 | |
| 59 | static struct soundwire_audio_mode cs42l42_audio_mode = { |
| 60 | .bus_frequency_configs_count = 6, |
| 61 | .bus_frequency_configs = { |
| 62 | 11289600, /* 11.2896 MHz */ |
| 63 | 12000 * KHz, /* 12 MHz */ |
| 64 | 12288 * KHz, /* 12.288 MHz */ |
| 65 | 22579200, /* 22.5792 MHz */ |
| 66 | 24000 * KHz, /* 24 MHz */ |
| 67 | 24576 * KHz, /* 24.576 MHz */ |
| 68 | }, |
| 69 | /* Support 8 KHz to 192 KHz sampling frequency */ |
| 70 | .max_sampling_frequency = 192 * KHz, |
| 71 | .min_sampling_frequency = 8 * KHz, |
| 72 | .prepare_channel_behavior = CHANNEL_PREPARE_ANY_FREQUENCY |
| 73 | }; |
| 74 | |
| 75 | static struct soundwire_dpn cs42l42_dp1 = { |
| 76 | .port_max_wordlength = 64, |
| 77 | .port_min_wordlength = 1, |
| 78 | .data_port_type = FULL_DATA_PORT, |
| 79 | .max_grouping_supported = BLOCK_GROUP_COUNT_1, |
| 80 | .simplified_channelprepare_sm = false, |
| 81 | .imp_def_dpn_interrupts_supported = 0, |
| 82 | .min_channel_number = 1, |
| 83 | .max_channel_number = 1, |
| 84 | .modes_supported = MODE_ISOCHRONOUS | MODE_TX_CONTROLLED | |
| 85 | MODE_RX_CONTROLLED | MODE_FULL_ASYNCHRONOUS, |
| 86 | .block_packing_mode = true, |
| 87 | .port_audio_mode_count = 1, |
| 88 | .port_audio_mode_list = { 0 } |
| 89 | }; |
| 90 | |
| 91 | static struct soundwire_dpn cs42l42_dpn = { |
| 92 | .port_max_wordlength = 64, |
| 93 | .port_min_wordlength = 1, |
| 94 | .data_port_type = FULL_DATA_PORT, |
| 95 | .max_grouping_supported = BLOCK_GROUP_COUNT_1, |
| 96 | .simplified_channelprepare_sm = false, |
| 97 | .imp_def_dpn_interrupts_supported = 0, |
| 98 | .min_channel_number = 1, |
| 99 | .max_channel_number = 2, |
| 100 | .modes_supported = MODE_ISOCHRONOUS | MODE_TX_CONTROLLED | |
| 101 | MODE_RX_CONTROLLED | MODE_FULL_ASYNCHRONOUS, |
| 102 | .block_packing_mode = true, |
| 103 | .port_audio_mode_count = 1, |
| 104 | .port_audio_mode_list = { 0 } |
| 105 | }; |
| 106 | |
| 107 | static const struct soundwire_codec cs42l42_codec = { |
| 108 | .slave = &cs42l42_slave, |
| 109 | .dp0_bra_mode = { &cs42l42_dp0_bra_mode }, |
| 110 | .dp0 = &cs42l42_dp0, |
| 111 | .audio_mode = { &cs42l42_audio_mode }, |
| 112 | .dpn = { |
| 113 | { |
| 114 | .port = 1, |
| 115 | .source = &cs42l42_dp1, |
| 116 | }, |
| 117 | { |
| 118 | .port = 2, |
| 119 | .sink = &cs42l42_dpn, |
| 120 | }, |
| 121 | { |
| 122 | .port = 3, |
| 123 | .sink = &cs42l42_dpn, |
| 124 | } |
| 125 | } |
| 126 | }; |
| 127 | |
| 128 | static void soundwire_cs42l42_fill_ssdt(const struct device *dev) |
| 129 | { |
| 130 | struct drivers_soundwire_cs42l42_config *config = dev->chip_info; |
| 131 | const char *scope = acpi_device_scope(dev); |
| 132 | const char *path = acpi_device_path(dev); |
| 133 | struct acpi_dp *dsd; |
| 134 | int gpio_index = 0; |
| 135 | |
| 136 | if (!scope) |
| 137 | return; |
| 138 | |
| 139 | acpigen_write_scope(scope); |
| 140 | acpigen_write_device(acpi_device_name(dev)); |
| 141 | |
| 142 | /* Set codec address IDs. */ |
| 143 | cs42l42_address.link_id = dev->path.generic.id; |
| 144 | cs42l42_address.unique_id = dev->path.generic.subid; |
| 145 | |
| 146 | acpigen_write_ADR_soundwire_device(&cs42l42_address); |
| 147 | acpigen_write_name_string("_DDN", config->desc ? : dev->chip_ops->name); |
| 148 | acpigen_write_STA(acpi_device_status(dev)); |
| 149 | |
| 150 | /* Resources */ |
| 151 | acpigen_write_name("_CRS"); |
| 152 | acpigen_write_resourcetemplate_header(); |
| 153 | |
| 154 | /* Use either Interrupt() or GpioInt() */ |
| 155 | if (config->irq_gpio.pin_count) |
| 156 | acpi_device_write_gpio(&config->irq_gpio); |
| 157 | else |
| 158 | acpi_device_write_interrupt(&config->irq); |
| 159 | |
| 160 | /* for cs42l42 reset gpio */ |
| 161 | if (config->reset_gpio.pin_count) |
| 162 | acpi_device_write_gpio(&config->reset_gpio); |
| 163 | |
| 164 | acpigen_write_resourcetemplate_footer(); |
| 165 | |
| 166 | dsd = acpi_dp_new_table("_DSD"); |
| 167 | |
| 168 | if (config->irq_gpio.pin_count) |
| 169 | acpi_dp_add_gpio(dsd, "irq-gpios", path, |
| 170 | gpio_index++, /* Index = 0 */ |
| 171 | 0, /* Pin = 0 (There is a single pin in the GPIO resource). */ |
| 172 | config->irq_gpio.active_low); |
| 173 | if (config->reset_gpio.pin_count) |
| 174 | acpi_dp_add_gpio(dsd, "reset-gpios", path, |
| 175 | gpio_index++, /* Index = 0 or 1 (if irq gpio is written). */ |
| 176 | 0, /* Pin = 0 (There is a single pin in the GPIO resource). */ |
| 177 | config->reset_gpio.active_low); |
| 178 | acpi_dp_add_integer(dsd, "cirrus,ts-inv", config->ts_inv ? 1 : 0); |
| 179 | acpi_dp_add_integer(dsd, "cirrus,ts-dbnc-rise", config->ts_dbnc_rise); |
| 180 | acpi_dp_add_integer(dsd, "cirrus,ts-dbnc-fall", config->ts_dbnc_fall); |
| 181 | acpi_dp_add_integer(dsd, "cirrus,btn-det-init-dbnce", config->btn_det_init_dbnce); |
| 182 | if (config->btn_det_init_dbnce > 200) { |
| 183 | printk(BIOS_ERR, "%s: Incorrect btn_det_init_dbnce(%d). Using default of 100ms\n", |
| 184 | __func__, config->btn_det_init_dbnce); |
| 185 | config->btn_det_init_dbnce = 100; |
| 186 | } |
| 187 | acpi_dp_add_integer(dsd, "cirrus,btn-det-event-dbnce", config->btn_det_event_dbnce); |
| 188 | if (config->btn_det_event_dbnce > 100) { |
| 189 | printk(BIOS_ERR, "%s: Incorrect btn_det_event_dbnce(%d). Using default of 10ms\n", |
| 190 | __func__, config->btn_det_event_dbnce); |
| 191 | config->btn_det_event_dbnce = 10; |
| 192 | } |
| 193 | acpi_dp_add_integer_array(dsd, "cirrus,bias-lvls", config->bias_lvls, 4); |
| 194 | acpi_dp_add_integer(dsd, "cirrus,hs-bias-ramp-rate", config->hs_bias_ramp_rate); |
| 195 | if (config->hs_bias_sense_disable) |
| 196 | acpi_dp_add_integer(dsd, "cirrus,hs-bias-sense-disable", 1); |
| 197 | |
| 198 | soundwire_gen_codec(dsd, &cs42l42_codec, NULL); |
| 199 | acpi_dp_write(dsd); |
| 200 | |
| 201 | acpigen_pop_len(); /* Device */ |
| 202 | acpigen_pop_len(); /* Scope */ |
| 203 | } |
| 204 | |
| 205 | static const char *soundwire_cs42l42_acpi_name(const struct device *dev) |
| 206 | { |
| 207 | struct drivers_soundwire_cs42l42_config *config = dev->chip_info; |
| 208 | if (config->acpi_name[0] != 0) |
| 209 | return config->acpi_name; |
| 210 | snprintf(config->acpi_name, sizeof(config->acpi_name), "SW%1X%1X", |
| 211 | dev->path.generic.id, dev->path.generic.subid); |
| 212 | return config->acpi_name; |
| 213 | } |
| 214 | |
| 215 | static struct device_operations soundwire_cs42l42_ops = { |
| 216 | .read_resources = noop_read_resources, |
| 217 | .set_resources = noop_set_resources, |
| 218 | .acpi_name = soundwire_cs42l42_acpi_name, |
| 219 | .acpi_fill_ssdt = soundwire_cs42l42_fill_ssdt, |
| 220 | }; |
| 221 | |
| 222 | static void soundwire_cs42l42_enable(struct device *dev) |
| 223 | { |
| 224 | dev->ops = &soundwire_cs42l42_ops; |
| 225 | } |
| 226 | |
| 227 | struct chip_operations drivers_soundwire_cs42l42_ops = { |
Nicholas Sudsgaard | bfb11be | 2024-01-30 09:53:46 +0900 | [diff] [blame] | 228 | .name = "Cirrus Logic CS42L42 SoundWire Codec", |
Kapil Porwal | 93b7fd1 | 2023-02-25 22:23:01 +0530 | [diff] [blame] | 229 | .enable_dev = soundwire_cs42l42_enable |
| 230 | }; |