Ben Chuang | ff17b31 | 2020-09-03 16:02:46 +0800 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
| 2 | |
| 3 | /* Driver for Genesys Logic GL9755 */ |
| 4 | |
| 5 | #include <console/console.h> |
| 6 | #include <device/device.h> |
Ben Chuang | ff17b31 | 2020-09-03 16:02:46 +0800 | [diff] [blame] | 7 | #include <device/pci.h> |
| 8 | #include <device/pci_ops.h> |
| 9 | #include <device/pci_ids.h> |
| 10 | #include "gl9755.h" |
| 11 | |
Duncan Laurie | bd8bb8ea | 2020-11-17 10:13:05 -0800 | [diff] [blame] | 12 | static void gl9755_enable(struct device *dev) |
Ben Chuang | ff17b31 | 2020-09-03 16:02:46 +0800 | [diff] [blame] | 13 | { |
Duncan Laurie | bd8bb8ea | 2020-11-17 10:13:05 -0800 | [diff] [blame] | 14 | uint32_t reg; |
| 15 | |
| 16 | printk(BIOS_INFO, "GL9755: configure ASPM and LTR\n"); |
Ben Chuang | ff17b31 | 2020-09-03 16:02:46 +0800 | [diff] [blame] | 17 | |
| 18 | /* Set Vendor Config to be configurable */ |
| 19 | pci_or_config32(dev, CFG, CFG_EN); |
Duncan Laurie | bd8bb8ea | 2020-11-17 10:13:05 -0800 | [diff] [blame] | 20 | |
Ben Chuang | ff17b31 | 2020-09-03 16:02:46 +0800 | [diff] [blame] | 21 | /* Set LTR value */ |
| 22 | pci_write_config32(dev, LTR, NO_SNOOP_SCALE|NO_SNOOP_VALUE|SNOOP_SCALE|SNOOP_VALUE); |
Duncan Laurie | bd8bb8ea | 2020-11-17 10:13:05 -0800 | [diff] [blame] | 23 | |
| 24 | /* Adjust L1 exit latency to enable ASPM */ |
| 25 | reg = pci_read_config32(dev, CFG2); |
| 26 | reg &= ~CFG2_LAT_L1_MASK; |
| 27 | reg |= CFG2_LAT_L1_64US; |
| 28 | pci_write_config32(dev, CFG2, reg); |
| 29 | |
Ben Chuang | 325f431 | 2021-09-14 11:31:42 +0800 | [diff] [blame] | 30 | /* Disable ASPM L0s support */ |
| 31 | pci_and_config32(dev, CFG2, ~CFG2_L0S_SUPPORT); |
| 32 | |
Ben Chuang | 6024350 | 2021-02-05 17:33:38 +0800 | [diff] [blame] | 33 | /* Turn off debug mode to enable SCP/OCP */ |
| 34 | pci_and_config32(dev, CFG3, ~SCP_DEBUG); |
| 35 | |
Ben Chuang | ff17b31 | 2020-09-03 16:02:46 +0800 | [diff] [blame] | 36 | /* Set Vendor Config to be non-configurable */ |
| 37 | pci_and_config32(dev, CFG, ~CFG_EN); |
| 38 | } |
| 39 | |
| 40 | static struct device_operations gl9755_ops = { |
| 41 | .read_resources = pci_dev_read_resources, |
| 42 | .set_resources = pci_dev_set_resources, |
| 43 | .enable_resources = pci_dev_enable_resources, |
| 44 | .ops_pci = &pci_dev_ops_pci, |
Duncan Laurie | bd8bb8ea | 2020-11-17 10:13:05 -0800 | [diff] [blame] | 45 | .enable = gl9755_enable |
Ben Chuang | ff17b31 | 2020-09-03 16:02:46 +0800 | [diff] [blame] | 46 | }; |
| 47 | |
| 48 | static const unsigned short pci_device_ids[] = { |
Felix Singer | 43b7f41 | 2022-03-07 04:34:52 +0100 | [diff] [blame] | 49 | PCI_DID_GLI_9755, |
Ben Chuang | ff17b31 | 2020-09-03 16:02:46 +0800 | [diff] [blame] | 50 | 0 |
| 51 | }; |
| 52 | |
| 53 | static const struct pci_driver genesyslogic_gl9755 __pci_driver = { |
| 54 | .ops = &gl9755_ops, |
Felix Singer | 43b7f41 | 2022-03-07 04:34:52 +0100 | [diff] [blame] | 55 | .vendor = PCI_VID_GLI, |
Ben Chuang | ff17b31 | 2020-09-03 16:02:46 +0800 | [diff] [blame] | 56 | .devices = pci_device_ids, |
| 57 | }; |
| 58 | |
| 59 | struct chip_operations drivers_generic_genesyslogic_gl9755_ops = { |
Nicholas Sudsgaard | bfb11be | 2024-01-30 09:53:46 +0900 | [diff] [blame] | 60 | .name = "Genesys Logic GL9755", |
Ben Chuang | ff17b31 | 2020-09-03 16:02:46 +0800 | [diff] [blame] | 61 | }; |