Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2014 Google Inc. |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or modify |
| 7 | * it under the terms of the GNU General Public License as published by |
| 8 | * the Free Software Foundation; version 2 of the License. |
| 9 | * |
| 10 | * This program is distributed in the hope that it will be useful, |
| 11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 13 | * GNU General Public License for more details. |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 14 | */ |
| 15 | |
| 16 | #include <stddef.h> |
| 17 | #include <stdint.h> |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 18 | #include <arch/cbfs.h> |
Kyösti Mälkki | 6e2d0c1 | 2019-06-28 10:08:51 +0300 | [diff] [blame] | 19 | #include <arch/cpu.h> |
Kyösti Mälkki | c641f7e | 2018-12-28 16:54:54 +0200 | [diff] [blame] | 20 | #include <bootblock_common.h> |
Julius Werner | b04cc6b | 2017-03-17 14:14:14 -0700 | [diff] [blame] | 21 | #include <bootmode.h> |
Arthur Heymans | 90cca54 | 2018-11-29 13:36:54 +0100 | [diff] [blame] | 22 | #include <cbmem.h> |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 23 | #include <console/console.h> |
Arthur Heymans | 56f7687 | 2019-05-12 14:01:13 +0200 | [diff] [blame] | 24 | #include <cpu/intel/romstage.h> |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 25 | #include <cpu/x86/mtrr.h> |
| 26 | #include <elog.h> |
Kyösti Mälkki | 65e8f64 | 2016-06-27 11:27:56 +0300 | [diff] [blame] | 27 | #include <program_loading.h> |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 28 | #include <romstage_handoff.h> |
Aaron Durbin | bd74a4b | 2015-03-06 23:17:33 -0600 | [diff] [blame] | 29 | #include <stage_cache.h> |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 30 | #include <timestamp.h> |
Arthur Heymans | cadc70f | 2019-05-12 13:44:22 +0200 | [diff] [blame] | 31 | #include <soc/gpio.h> |
Julius Werner | 4ee4bd5 | 2014-10-20 13:46:39 -0700 | [diff] [blame] | 32 | #include <soc/me.h> |
| 33 | #include <soc/pei_data.h> |
| 34 | #include <soc/pm.h> |
Julius Werner | 4ee4bd5 | 2014-10-20 13:46:39 -0700 | [diff] [blame] | 35 | #include <soc/romstage.h> |
| 36 | #include <soc/spi.h> |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 37 | |
Kyösti Mälkki | 5bc641a | 2019-08-09 09:37:49 +0300 | [diff] [blame] | 38 | void fill_postcar_frame(struct postcar_frame *pcf) |
Arthur Heymans | 90cca54 | 2018-11-29 13:36:54 +0100 | [diff] [blame] | 39 | { |
Arthur Heymans | 90cca54 | 2018-11-29 13:36:54 +0100 | [diff] [blame] | 40 | uintptr_t top_of_ram; |
| 41 | |
Arthur Heymans | 90cca54 | 2018-11-29 13:36:54 +0100 | [diff] [blame] | 42 | /* Cache at least 8 MiB below the top of ram, and at most 8 MiB |
| 43 | * above top of the ram. This satisfies MTRR alignment requirement |
| 44 | * with different TSEG size configurations. |
| 45 | */ |
| 46 | top_of_ram = ALIGN_DOWN((uintptr_t)cbmem_top(), 8*MiB); |
Kyösti Mälkki | 5bc641a | 2019-08-09 09:37:49 +0300 | [diff] [blame] | 47 | postcar_frame_add_mtrr(pcf, top_of_ram - 8*MiB, 16*MiB, |
Arthur Heymans | 90cca54 | 2018-11-29 13:36:54 +0100 | [diff] [blame] | 48 | MTRR_TYPE_WRBACK); |
Arthur Heymans | 90cca54 | 2018-11-29 13:36:54 +0100 | [diff] [blame] | 49 | } |
| 50 | |
Arthur Heymans | 56f7687 | 2019-05-12 14:01:13 +0200 | [diff] [blame] | 51 | /* Entry from cpu/intel/car/romstage.c. */ |
Kyösti Mälkki | 157b189 | 2019-08-16 14:02:25 +0300 | [diff] [blame] | 52 | void mainboard_romstage_entry(void) |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 53 | { |
Arthur Heymans | 5bb15f1 | 2018-12-22 16:02:25 +0100 | [diff] [blame] | 54 | struct romstage_params rp = { 0 }; |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 55 | |
| 56 | post_code(0x30); |
| 57 | |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 58 | /* System Agent Early Initialization */ |
| 59 | systemagent_early_init(); |
| 60 | |
| 61 | /* PCH Early Initialization */ |
| 62 | pch_early_init(); |
| 63 | |
Duncan Laurie | 6168027 | 2014-05-05 12:42:35 -0500 | [diff] [blame] | 64 | /* Get power state */ |
| 65 | rp.power_state = fill_power_state(); |
| 66 | |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 67 | /* Print useful platform information */ |
| 68 | report_platform_info(); |
| 69 | |
| 70 | /* Set CPU frequency to maximum */ |
| 71 | set_max_freq(); |
| 72 | |
Arthur Heymans | cadc70f | 2019-05-12 13:44:22 +0200 | [diff] [blame] | 73 | /* Initialize GPIOs */ |
| 74 | init_gpios(mainboard_gpio_config); |
| 75 | |
Arthur Heymans | 97e9e56 | 2019-05-12 13:47:35 +0200 | [diff] [blame] | 76 | /* Fill in mainboard pei_date. */ |
| 77 | mainboard_pre_raminit(&rp); |
| 78 | |
| 79 | post_code(0x32); |
| 80 | |
| 81 | timestamp_add_now(TS_BEFORE_INITRAM); |
| 82 | |
| 83 | rp.pei_data.boot_mode = rp.power_state->prev_sleep_state; |
| 84 | |
| 85 | if (CONFIG(ELOG_BOOT_COUNT) |
| 86 | && rp.power_state->prev_sleep_state != ACPI_S3) |
| 87 | boot_count_increment(); |
| 88 | |
| 89 | /* Print ME state before MRC */ |
| 90 | intel_me_status(); |
| 91 | |
| 92 | /* Save ME HSIO version */ |
| 93 | intel_me_hsio_version(&rp.power_state->hsio_version, |
| 94 | &rp.power_state->hsio_checksum); |
| 95 | |
| 96 | /* Initialize RAM */ |
| 97 | raminit(&rp.pei_data); |
| 98 | |
| 99 | timestamp_add_now(TS_AFTER_INITRAM); |
| 100 | |
| 101 | romstage_handoff_init(rp.power_state->prev_sleep_state == ACPI_S3); |
| 102 | |
| 103 | mainboard_post_raminit(&rp); |
Duncan Laurie | c88c54c | 2014-04-30 16:36:13 -0700 | [diff] [blame] | 104 | } |