henryc.chen | fb622cc | 2015-07-31 17:10:52 +0800 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright 2015 MediaTek Inc. |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or modify |
| 7 | * it under the terms of the GNU General Public License as published by |
| 8 | * the Free Software Foundation; version 2 of the License. |
| 9 | * |
| 10 | * This program is distributed in the hope that it will be useful, |
| 11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 13 | * GNU General Public License for more details. |
| 14 | * |
| 15 | * You should have received a copy of the GNU General Public License |
| 16 | * along with this program; if not, write to the Free Software |
| 17 | * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA |
| 18 | */ |
| 19 | |
| 20 | #include <arch/io.h> |
| 21 | #include <assert.h> |
| 22 | #include <console/console.h> |
| 23 | #include <delay.h> |
| 24 | #include <soc/infracfg.h> |
| 25 | #include <soc/pmic_wrap.h> |
| 26 | #include <timer.h> |
| 27 | |
| 28 | #define PWRAPTAG "[PWRAP] " |
| 29 | #define pwrap_log(fmt, arg ...) printk(BIOS_INFO, PWRAPTAG fmt, ## arg) |
| 30 | #define pwrap_err(fmt, arg ...) printk(BIOS_ERR, PWRAPTAG "ERROR,line=%d" fmt, \ |
| 31 | __LINE__, ## arg) |
| 32 | |
| 33 | /* define macro and inline function (for do while loop) */ |
| 34 | |
| 35 | typedef u32 (*loop_condition_fp)(u32); |
| 36 | |
| 37 | static inline u32 wait_for_fsm_vldclr(u32 x) |
| 38 | { |
| 39 | return ((x >> RDATA_WACS_FSM_SHIFT) & RDATA_WACS_FSM_MASK) != |
| 40 | WACS_FSM_WFVLDCLR; |
| 41 | } |
| 42 | |
| 43 | static inline u32 wait_for_sync(u32 x) |
| 44 | { |
| 45 | return ((x >> RDATA_SYNC_IDLE_SHIFT) & RDATA_SYNC_IDLE_MASK) != |
| 46 | WACS_SYNC_IDLE; |
| 47 | } |
| 48 | |
| 49 | static inline u32 wait_for_idle_and_sync(u32 x) |
| 50 | { |
| 51 | return ((((x >> RDATA_WACS_FSM_SHIFT) & RDATA_WACS_FSM_MASK) != |
| 52 | WACS_FSM_IDLE) || (((x >> RDATA_SYNC_IDLE_SHIFT) & |
| 53 | RDATA_SYNC_IDLE_MASK)!= WACS_SYNC_IDLE)); |
| 54 | } |
| 55 | |
| 56 | static inline u32 wait_for_cipher_ready(u32 x) |
| 57 | { |
| 58 | return x != 3; |
| 59 | } |
| 60 | |
| 61 | static inline u32 wait_for_state_idle(u32 timeout_us, void *wacs_register, |
| 62 | void *wacs_vldclr_register, |
| 63 | u32 *read_reg) |
| 64 | { |
| 65 | u32 reg_rdata; |
| 66 | |
| 67 | struct stopwatch sw; |
| 68 | |
| 69 | stopwatch_init_usecs_expire(&sw, timeout_us); |
| 70 | do { |
| 71 | reg_rdata = read32((wacs_register)); |
| 72 | /* if last read command timeout,clear vldclr bit |
| 73 | read command state machine:FSM_REQ-->wfdle-->WFVLDCLR; |
| 74 | write:FSM_REQ-->idle */ |
| 75 | switch (((reg_rdata >> RDATA_WACS_FSM_SHIFT) & |
| 76 | RDATA_WACS_FSM_MASK)) { |
| 77 | case WACS_FSM_WFVLDCLR: |
| 78 | write32(wacs_vldclr_register, 1); |
| 79 | pwrap_err("WACS_FSM = PMIC_WRAP_WACS_VLDCLR\n"); |
| 80 | break; |
| 81 | case WACS_FSM_WFDLE: |
| 82 | pwrap_err("WACS_FSM = WACS_FSM_WFDLE\n"); |
| 83 | break; |
| 84 | case WACS_FSM_REQ: |
| 85 | pwrap_err("WACS_FSM = WACS_FSM_REQ\n"); |
| 86 | break; |
| 87 | default: |
| 88 | break; |
| 89 | } |
| 90 | |
| 91 | if (stopwatch_expired(&sw)) |
| 92 | return E_PWR_WAIT_IDLE_TIMEOUT; |
| 93 | |
| 94 | } while (((reg_rdata >> RDATA_WACS_FSM_SHIFT) & RDATA_WACS_FSM_MASK) != |
| 95 | WACS_FSM_IDLE); /* IDLE State */ |
| 96 | if (read_reg) |
| 97 | *read_reg = reg_rdata; |
| 98 | return 0; |
| 99 | } |
| 100 | |
| 101 | static inline u32 wait_for_state_ready(loop_condition_fp fp, u32 timeout_us, |
| 102 | void *wacs_register, u32 *read_reg) |
| 103 | { |
| 104 | u32 reg_rdata; |
| 105 | struct stopwatch sw; |
| 106 | |
| 107 | stopwatch_init_usecs_expire(&sw, timeout_us); |
| 108 | do { |
| 109 | reg_rdata = read32((wacs_register)); |
| 110 | |
| 111 | if (stopwatch_expired(&sw)) { |
| 112 | pwrap_err("timeout when waiting for idle\n"); |
| 113 | return E_PWR_WAIT_IDLE_TIMEOUT; |
| 114 | } |
| 115 | } while (fp(reg_rdata)); /* IDLE State */ |
| 116 | if (read_reg) |
| 117 | *read_reg = reg_rdata; |
| 118 | return 0; |
| 119 | } |
| 120 | |
| 121 | s32 pwrap_wacs2(u32 write, u16 adr, u16 wdata, u16 *rdata, u32 init_check) |
| 122 | { |
| 123 | u32 reg_rdata = 0; |
| 124 | u32 wacs_write = 0; |
| 125 | u32 wacs_adr = 0; |
| 126 | u32 wacs_cmd = 0; |
| 127 | u32 return_value = 0; |
| 128 | |
| 129 | if (init_check) { |
| 130 | reg_rdata = read32(&mt8173_pwrap->wacs2_rdata); |
| 131 | /* Prevent someone to used pwrap before pwrap init */ |
| 132 | if (((reg_rdata >> RDATA_INIT_DONE_SHIFT) & |
| 133 | RDATA_INIT_DONE_MASK) != WACS_INIT_DONE) { |
| 134 | pwrap_err("initialization isn't finished \n"); |
| 135 | return E_PWR_NOT_INIT_DONE; |
| 136 | } |
| 137 | } |
| 138 | reg_rdata = 0; |
| 139 | /* Check IDLE in advance */ |
| 140 | return_value = wait_for_state_idle(TIMEOUT_WAIT_IDLE_US, |
| 141 | &mt8173_pwrap->wacs2_rdata, |
| 142 | &mt8173_pwrap->wacs2_vldclr, |
| 143 | 0); |
| 144 | if (return_value != 0) { |
| 145 | pwrap_err("wait_for_fsm_idle fail,return_value=%d\n", |
| 146 | return_value); |
| 147 | return E_PWR_WAIT_IDLE_TIMEOUT; |
| 148 | } |
| 149 | wacs_write = write << 31; |
| 150 | wacs_adr = (adr >> 1) << 16; |
| 151 | wacs_cmd = wacs_write | wacs_adr | wdata; |
| 152 | |
| 153 | write32(&mt8173_pwrap->wacs2_cmd, wacs_cmd); |
| 154 | if (write == 0) { |
| 155 | if (NULL == rdata) { |
| 156 | pwrap_err("rdata is a NULL pointer\n"); |
| 157 | return E_PWR_INVALID_ARG; |
| 158 | } |
| 159 | return_value = wait_for_state_ready(wait_for_fsm_vldclr, |
| 160 | TIMEOUT_READ_US, |
| 161 | &mt8173_pwrap->wacs2_rdata, |
| 162 | ®_rdata); |
| 163 | if (return_value != 0) { |
| 164 | pwrap_err("wait_for_fsm_vldclr fail,return_value=%d\n", |
| 165 | return_value); |
| 166 | return E_PWR_WAIT_IDLE_TIMEOUT_READ; |
| 167 | } |
| 168 | *rdata = ((reg_rdata >> RDATA_WACS_RDATA_SHIFT) |
| 169 | & RDATA_WACS_RDATA_MASK); |
| 170 | write32(&mt8173_pwrap->wacs2_vldclr, 1); |
| 171 | } |
| 172 | |
| 173 | return 0; |
| 174 | } |
| 175 | |
| 176 | /* external API for pmic_wrap user */ |
| 177 | |
| 178 | s32 pwrap_read(u16 adr, u16 *rdata) |
| 179 | { |
| 180 | return pwrap_wacs2(0, adr, 0, rdata, 1); |
| 181 | } |
| 182 | |
| 183 | s32 pwrap_write(u16 adr, u16 wdata) |
| 184 | { |
| 185 | return pwrap_wacs2(1, adr, wdata, 0, 1); |
| 186 | } |
| 187 | |
| 188 | static s32 pwrap_read_nochk(u16 adr, u16 *rdata) |
| 189 | { |
| 190 | return pwrap_wacs2(0, adr, 0, rdata, 0); |
| 191 | } |
| 192 | |
| 193 | static s32 pwrap_write_nochk(u16 adr, u16 wdata) |
| 194 | { |
| 195 | return pwrap_wacs2(1, adr, wdata, 0, 0); |
| 196 | } |
| 197 | |
| 198 | /* call it in pwrap_init,mustn't check init done */ |
| 199 | static s32 pwrap_init_dio(u32 dio_en) |
| 200 | { |
| 201 | u16 rdata = 0; |
| 202 | u32 return_value = 0; |
| 203 | |
| 204 | pwrap_write_nochk(DEW_DIO_EN, dio_en); |
| 205 | |
| 206 | /* Check IDLE in advance */ |
| 207 | return_value = |
| 208 | wait_for_state_ready(wait_for_idle_and_sync, |
| 209 | TIMEOUT_WAIT_IDLE_US, |
| 210 | &mt8173_pwrap->wacs2_rdata, |
| 211 | 0); |
| 212 | if (return_value != 0) { |
| 213 | pwrap_err("%s fail,return_value=%#x\n", __func__, return_value); |
| 214 | return return_value; |
| 215 | } |
| 216 | write32(&mt8173_pwrap->dio_en, dio_en); |
| 217 | /* Read Test */ |
| 218 | pwrap_read_nochk(DEW_READ_TEST, &rdata); |
| 219 | if (rdata != DEFAULT_VALUE_READ_TEST) { |
| 220 | pwrap_err("fail,dio_en = %#x, READ_TEST rdata=%#x\n", dio_en, |
| 221 | rdata); |
| 222 | return E_PWR_READ_TEST_FAIL; |
| 223 | } |
| 224 | |
| 225 | return 0; |
| 226 | } |
| 227 | |
| 228 | /* |
| 229 | * pwrap_init_sidly - configure serial input delay |
| 230 | * |
| 231 | * This configures the serial input delay. We can configure 0, 2, 4 or 6ns |
| 232 | * delay. Do a read test with all possible values and chose the best delay. |
| 233 | */ |
| 234 | static s32 pwrap_init_sidly(void) |
| 235 | { |
| 236 | u16 rdata; |
| 237 | u32 i; |
| 238 | u32 pass = 0; |
| 239 | u32 sidly = 0; |
| 240 | |
| 241 | for (i = 0; i < 4; i++) { |
| 242 | write32(&mt8173_pwrap->sidly, i); |
| 243 | pwrap_wacs2(0, DEW_READ_TEST, 0, &rdata, 0); |
| 244 | if (rdata == DEFAULT_VALUE_READ_TEST) |
| 245 | pass |= 1 << i; |
| 246 | } |
| 247 | |
| 248 | /* |
| 249 | * Config SIDLY according to results |
| 250 | * Pass range should be continuously or return failed |
| 251 | */ |
| 252 | switch (pass) { |
| 253 | /* only 1 pass, choose it */ |
| 254 | case 1 << 0: |
| 255 | sidly = 0; |
| 256 | break; |
| 257 | case 1 << 1: |
| 258 | sidly = 1; |
| 259 | break; |
| 260 | case 1 << 2: |
| 261 | sidly = 2; |
| 262 | break; |
| 263 | case 1 << 3: |
| 264 | sidly = 3; |
| 265 | break; |
| 266 | /* two pass, choose the one on SIDLY boundary */ |
| 267 | case (1 << 0) | (1 << 1): |
| 268 | sidly = 0; |
| 269 | break; |
| 270 | case (1 << 1) | (1 << 2): /* no boundary, choose smaller one */ |
| 271 | sidly = 1; |
| 272 | break; |
| 273 | case (1 << 2) | (1 << 3): |
| 274 | sidly = 3; |
| 275 | break; |
| 276 | /* three pass, choose the middle one */ |
| 277 | case (1 << 0) | (1 << 1) | (1 << 2): |
| 278 | sidly = 1; |
| 279 | break; |
| 280 | case (1 << 1) | (1 << 2) | (1 << 3): |
| 281 | sidly = 2; |
| 282 | break; |
| 283 | /* four pass, choose the smaller middle one */ |
| 284 | case (1 << 0) | (1 << 1) | (1 << 2) | (1 << 3): |
| 285 | sidly = 1; |
| 286 | break; |
| 287 | /* pass range not continuous, should not happen */ |
| 288 | default: |
| 289 | die("sidly pass range not continuous\n"); |
| 290 | } |
| 291 | |
| 292 | write32(&mt8173_pwrap->sidly, sidly); |
| 293 | |
| 294 | return 0; |
| 295 | } |
| 296 | |
| 297 | static s32 pwrap_reset_spislv(void) |
| 298 | { |
| 299 | u32 ret = 0; |
| 300 | u32 return_value = 0; |
| 301 | |
| 302 | write32(&mt8173_pwrap->hiprio_arb_en, 0); |
| 303 | write32(&mt8173_pwrap->wrap_en, 0); |
| 304 | write32(&mt8173_pwrap->mux_sel, 1); |
| 305 | write32(&mt8173_pwrap->man_en, 1); |
| 306 | write32(&mt8173_pwrap->dio_en, 0); |
| 307 | |
| 308 | write32(&mt8173_pwrap->man_cmd, (OP_WR << 13) | (OP_CSL << 8)); |
| 309 | /* to reset counter */ |
| 310 | write32(&mt8173_pwrap->man_cmd, (OP_WR << 13) | (OP_OUTS << 8)); |
| 311 | write32(&mt8173_pwrap->man_cmd, (OP_WR << 13) | (OP_CSH << 8)); |
| 312 | /* |
| 313 | * In order to pull CSN signal to PMIC, |
| 314 | * PMIC will count it then reset spi slave |
| 315 | */ |
| 316 | write32(&mt8173_pwrap->man_cmd, (OP_WR << 13) | (OP_OUTS << 8)); |
| 317 | write32(&mt8173_pwrap->man_cmd, (OP_WR << 13) | (OP_OUTS << 8)); |
| 318 | write32(&mt8173_pwrap->man_cmd, (OP_WR << 13) | (OP_OUTS << 8)); |
| 319 | write32(&mt8173_pwrap->man_cmd, (OP_WR << 13) | (OP_OUTS << 8)); |
| 320 | |
| 321 | return_value = wait_for_state_ready(wait_for_sync, |
| 322 | TIMEOUT_WAIT_IDLE_US, |
| 323 | &mt8173_pwrap->wacs2_rdata, 0); |
| 324 | if (return_value != 0) { |
| 325 | pwrap_err("%s fail,return_value=%#x\n", __func__, return_value); |
| 326 | ret = E_PWR_TIMEOUT; |
| 327 | } |
| 328 | |
| 329 | write32(&mt8173_pwrap->man_en, 0); |
| 330 | write32(&mt8173_pwrap->mux_sel, 0); |
| 331 | |
| 332 | return ret; |
| 333 | } |
| 334 | |
| 335 | static s32 pwrap_init_reg_clock(enum pmic_regck regck_sel) |
| 336 | { |
| 337 | u16 wdata = 0; |
| 338 | u16 rdata = 0; |
| 339 | |
| 340 | /* Set reg clk freq */ |
| 341 | pwrap_read_nochk(PMIC_TOP_CKCON2, &rdata); |
| 342 | |
| 343 | if (regck_sel == REG_CLOCK_18MHZ) |
| 344 | wdata = (rdata & (~(0x3 << 10))) | (0x1 << 10); |
| 345 | else |
| 346 | wdata = rdata & (~(0x3 << 10)); |
| 347 | |
| 348 | pwrap_write_nochk(PMIC_TOP_CKCON2, wdata); |
| 349 | pwrap_read_nochk(PMIC_TOP_CKCON2, &rdata); |
| 350 | if (rdata != wdata) { |
| 351 | pwrap_err("pwrap_init_reg_clock,rdata=%#x\n", rdata); |
| 352 | return E_PWR_INIT_REG_CLOCK; |
| 353 | } |
| 354 | /* Config SPI Waveform according to reg clk */ |
| 355 | switch (regck_sel) { |
| 356 | case REG_CLOCK_18MHZ: |
| 357 | write32(&mt8173_pwrap->rddmy, 0xc); |
| 358 | write32(&mt8173_pwrap->cshext_write, 0x0); |
| 359 | write32(&mt8173_pwrap->cshext_read, 0x4); |
| 360 | write32(&mt8173_pwrap->cslext_start, 0x0); |
| 361 | write32(&mt8173_pwrap->cslext_end, 0x4); |
| 362 | break; |
| 363 | case REG_CLOCK_26MHZ: |
| 364 | write32(&mt8173_pwrap->rddmy, 0xc); |
| 365 | write32(&mt8173_pwrap->cshext_write, 0x0); |
| 366 | write32(&mt8173_pwrap->cshext_read, 0x4); |
| 367 | write32(&mt8173_pwrap->cslext_start, 0x2); |
| 368 | write32(&mt8173_pwrap->cslext_end, 0x2); |
| 369 | break; |
| 370 | default: |
| 371 | write32(&mt8173_pwrap->rddmy, 0xf); |
| 372 | write32(&mt8173_pwrap->cshext_write, 0xf); |
| 373 | write32(&mt8173_pwrap->cshext_read, 0xf); |
| 374 | write32(&mt8173_pwrap->cslext_start, 0xf); |
| 375 | write32(&mt8173_pwrap->cslext_end, 0xf); |
| 376 | break; |
| 377 | } |
| 378 | |
| 379 | return 0; |
| 380 | } |
| 381 | |
| 382 | s32 pwrap_init(void) |
| 383 | { |
| 384 | s32 sub_return = 0; |
| 385 | s32 sub_return1 = 0; |
| 386 | u16 rdata = 0x0; |
| 387 | |
| 388 | setbits_le32(&mt8173_infracfg->infra_rst0, INFRA_PMIC_WRAP_RST); |
| 389 | /* add 1us delay for toggling SW reset */ |
| 390 | udelay(1); |
| 391 | /* clear reset bit */ |
| 392 | clrbits_le32(&mt8173_infracfg->infra_rst0, INFRA_PMIC_WRAP_RST); |
| 393 | |
| 394 | /* Enable DCM */ |
| 395 | write32(&mt8173_pwrap->dcm_en, 3); |
| 396 | write32(&mt8173_pwrap->dcm_dbc_prd, 0); |
| 397 | |
| 398 | /* Reset SPISLV */ |
| 399 | sub_return = pwrap_reset_spislv(); |
| 400 | if (sub_return != 0) { |
| 401 | pwrap_err("error,pwrap_reset_spislv fail,sub_return=%#x\n", |
| 402 | sub_return); |
| 403 | return E_PWR_INIT_RESET_SPI; |
| 404 | } |
| 405 | /* Enable WACS2 */ |
| 406 | write32(&mt8173_pwrap->wrap_en, 1); |
| 407 | write32(&mt8173_pwrap->hiprio_arb_en, WACS2); |
| 408 | write32(&mt8173_pwrap->wacs2_en, 1); |
| 409 | |
| 410 | /* SIDLY setting */ |
| 411 | sub_return = pwrap_init_sidly(); |
| 412 | if (sub_return != 0) { |
| 413 | pwrap_err("error,pwrap_init_sidly fail,sub_return=%#x\n", |
| 414 | sub_return); |
| 415 | return E_PWR_INIT_SIDLY; |
| 416 | } |
| 417 | /* |
| 418 | * SPI Waveform Configuration |
| 419 | * 18MHz/26MHz/safe mode/ |
| 420 | */ |
| 421 | sub_return = pwrap_init_reg_clock(REG_CLOCK_26MHZ); |
| 422 | if (sub_return != 0) { |
| 423 | pwrap_err("error,pwrap_init_reg_clock fail,sub_return=%#x\n", |
| 424 | sub_return); |
| 425 | return E_PWR_INIT_REG_CLOCK; |
| 426 | } |
| 427 | /* |
| 428 | * Enable PMIC |
| 429 | */ |
| 430 | pwrap_read_nochk(PMIC_WRP_CKPDN, &rdata); |
| 431 | sub_return = pwrap_write_nochk(PMIC_WRP_CKPDN, rdata & 0x50); |
| 432 | /* clear dewrap reset bit */ |
| 433 | sub_return1 = pwrap_write_nochk(PMIC_WRP_RST_CON, 0); |
| 434 | if ((sub_return != 0) || (sub_return1 != 0)) { |
| 435 | pwrap_err("Enable PMIC fail, sub_return=%#x sub_return1=%#x\n", |
| 436 | sub_return, sub_return1); |
| 437 | return E_PWR_INIT_ENABLE_PMIC; |
| 438 | } |
| 439 | /* Enable DIO mode */ |
| 440 | sub_return = pwrap_init_dio(1); |
| 441 | if (sub_return != 0) { |
| 442 | pwrap_err("pwrap_init_dio error code=%#x, sub_return=%#x\n", |
| 443 | 0x11, sub_return); |
| 444 | return E_PWR_INIT_DIO; |
| 445 | } |
| 446 | |
| 447 | /* |
| 448 | * Write test using WACS2, |
| 449 | * make sure the read/write function ready |
| 450 | */ |
| 451 | sub_return = pwrap_write_nochk(DEW_WRITE_TEST, WRITE_TEST_VALUE); |
| 452 | sub_return1 = pwrap_read_nochk(DEW_WRITE_TEST, &rdata); |
| 453 | if ((rdata != WRITE_TEST_VALUE) || (sub_return != 0) |
| 454 | || (sub_return1 != 0)) { |
| 455 | pwrap_err("write error, rdata=%#x, return=%#x, return1=%#x\n", |
| 456 | rdata, sub_return, sub_return1); |
| 457 | return E_PWR_INIT_WRITE_TEST; |
| 458 | } |
| 459 | |
| 460 | /* Signature Checking - Using CRC |
| 461 | * should be the last to modify WRITE_TEST |
| 462 | */ |
| 463 | sub_return = pwrap_write_nochk(DEW_CRC_EN, 0x1); |
| 464 | if (sub_return != 0) { |
| 465 | pwrap_err("enable CRC fail,sub_return=%#x\n", sub_return); |
| 466 | return E_PWR_INIT_ENABLE_CRC; |
| 467 | } |
| 468 | write32(&mt8173_pwrap->crc_en, 0x1); |
| 469 | write32(&mt8173_pwrap->sig_mode, 0x0); |
| 470 | write32(&mt8173_pwrap->sig_adr, DEW_CRC_VAL); |
| 471 | |
| 472 | /* PMIC_WRAP enables */ |
| 473 | write32(&mt8173_pwrap->hiprio_arb_en, 0x1ff); |
| 474 | write32(&mt8173_pwrap->wacs0_en, 0x1); |
| 475 | write32(&mt8173_pwrap->wacs1_en, 0x1); |
| 476 | |
| 477 | /* |
| 478 | * switch event pin from usbdl mode to normal mode for pmic interrupt, |
| 479 | * NEW@MT6397 |
| 480 | */ |
| 481 | pwrap_read_nochk(PMIC_TOP_CKCON3, &rdata); |
| 482 | sub_return = pwrap_write_nochk(PMIC_TOP_CKCON3, (rdata & 0x0007)); |
| 483 | if (sub_return != 0) |
| 484 | pwrap_err("!!switch event pin fail,sub_return=%d\n", |
| 485 | sub_return); |
| 486 | |
| 487 | /* Initialization Done */ |
| 488 | write32(&mt8173_pwrap->init_done2, 0x1); |
| 489 | write32(&mt8173_pwrap->init_done0, 0x1); |
| 490 | write32(&mt8173_pwrap->init_done1, 0x1); |
| 491 | |
| 492 | return 0; |
| 493 | } |