Kyösti Mälkki | e8b4da2 | 2014-10-21 18:22:32 +0300 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2010 Advanced Micro Devices, Inc. |
| 5 | * Copyright (C) 2014 Sage Electronic Engineering, LLC |
| 6 | * |
| 7 | * This program is free software; you can redistribute it and/or modify |
| 8 | * it under the terms of the GNU General Public License as published by |
| 9 | * the Free Software Foundation; version 2 of the License. |
| 10 | * |
| 11 | * This program is distributed in the hope that it will be useful, |
| 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 14 | * GNU General Public License for more details. |
Kyösti Mälkki | e8b4da2 | 2014-10-21 18:22:32 +0300 | [diff] [blame] | 15 | */ |
| 16 | |
| 17 | #include <console/console.h> |
| 18 | #include <device/device.h> |
| 19 | #include <device/pci.h> |
| 20 | #include <device/pnp.h> |
| 21 | #include <device/pci_ids.h> |
| 22 | #include <device/pci_ops.h> |
| 23 | #include <device/pci_def.h> |
| 24 | #include <pc80/mc146818rtc.h> |
| 25 | #include <pc80/isa-dma.h> |
| 26 | #include <arch/io.h> |
| 27 | #include <arch/ioapic.h> |
Edward O'Callaghan | 4565aea | 2015-06-07 19:42:47 +1000 | [diff] [blame] | 28 | #include <arch/acpi.h> |
Dave Frodin | 8d9a1bd | 2015-03-31 16:10:58 -0600 | [diff] [blame] | 29 | #include <pc80/i8254.h> |
| 30 | #include <pc80/i8259.h> |
Kyösti Mälkki | e8b4da2 | 2014-10-21 18:22:32 +0300 | [diff] [blame] | 31 | #include "hudson.h" |
| 32 | |
| 33 | static void lpc_init(device_t dev) |
| 34 | { |
| 35 | u8 byte; |
| 36 | u32 dword; |
| 37 | device_t sm_dev; |
| 38 | |
| 39 | /* Enable the LPC Controller */ |
| 40 | sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0)); |
| 41 | dword = pci_read_config32(sm_dev, 0x64); |
| 42 | dword |= 1 << 20; |
| 43 | pci_write_config32(sm_dev, 0x64, dword); |
| 44 | |
| 45 | /* Initialize isa dma */ |
| 46 | isa_dma_init(); |
| 47 | |
| 48 | /* Enable DMA transaction on the LPC bus */ |
| 49 | byte = pci_read_config8(dev, 0x40); |
| 50 | byte |= (1 << 2); |
| 51 | pci_write_config8(dev, 0x40, byte); |
| 52 | |
| 53 | /* Disable the timeout mechanism on LPC */ |
| 54 | byte = pci_read_config8(dev, 0x48); |
| 55 | byte &= ~(1 << 7); |
| 56 | pci_write_config8(dev, 0x48, byte); |
| 57 | |
| 58 | /* Disable LPC MSI Capability */ |
| 59 | byte = pci_read_config8(dev, 0x78); |
| 60 | byte &= ~(1 << 1); |
| 61 | byte &= ~(1 << 0); /* Keep the old way. i.e., when bus master/DMA cycle is going |
| 62 | on on LPC, it holds PCI grant, so no LPC slave cycle can |
| 63 | interrupt and visit LPC. */ |
| 64 | pci_write_config8(dev, 0x78, byte); |
| 65 | |
Elyes HAOUAS | 1bcd7fc | 2016-07-28 21:20:04 +0200 | [diff] [blame] | 66 | /* bit0: Enable prefetch a cacheline (64 bytes) when Host reads code from SPI ROM */ |
Kyösti Mälkki | e8b4da2 | 2014-10-21 18:22:32 +0300 | [diff] [blame] | 67 | /* bit3: Fix SPI_CS# timing issue when running at 66M. TODO:A12. */ |
| 68 | byte = pci_read_config8(dev, 0xBB); |
| 69 | byte |= 1 << 0 | 1 << 3; |
| 70 | pci_write_config8(dev, 0xBB, byte); |
| 71 | |
Gabe Black | 03abaee21 | 2014-04-30 21:31:44 -0700 | [diff] [blame] | 72 | cmos_check_update_date(); |
Kyösti Mälkki | e8b4da2 | 2014-10-21 18:22:32 +0300 | [diff] [blame] | 73 | |
| 74 | /* Initialize the real time clock. |
| 75 | * The 0 argument tells cmos_init not to |
| 76 | * update CMOS unless it is invalid. |
| 77 | * 1 tells cmos_init to always initialize the CMOS. |
| 78 | */ |
| 79 | cmos_init(0); |
Dave Frodin | 8d9a1bd | 2015-03-31 16:10:58 -0600 | [diff] [blame] | 80 | |
| 81 | /* Initialize i8259 pic */ |
| 82 | setup_i8259 (); |
| 83 | |
| 84 | /* Initialize i8254 timers */ |
| 85 | setup_i8254 (); |
Kyösti Mälkki | e8b4da2 | 2014-10-21 18:22:32 +0300 | [diff] [blame] | 86 | } |
| 87 | |
| 88 | static void hudson_lpc_read_resources(device_t dev) |
| 89 | { |
| 90 | struct resource *res; |
| 91 | |
| 92 | /* Get the normal pci resources of this device */ |
| 93 | pci_dev_read_resources(dev); /* We got one for APIC, or one more for TRAP */ |
| 94 | |
| 95 | /* Add an extra subtractive resource for both memory and I/O. */ |
| 96 | res = new_resource(dev, IOINDEX_SUBTRACTIVE(0, 0)); |
| 97 | res->base = 0; |
| 98 | res->size = 0x1000; |
| 99 | res->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE | |
| 100 | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; |
| 101 | |
| 102 | res = new_resource(dev, IOINDEX_SUBTRACTIVE(1, 0)); |
| 103 | res->base = 0xff800000; |
| 104 | res->size = 0x00800000; /* 8 MB for flash */ |
| 105 | res->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE | |
| 106 | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; |
| 107 | |
| 108 | /* Add a memory resource for the SPI BAR. */ |
| 109 | fixed_mem_resource(dev, 2, SPI_BASE_ADDRESS / 1024, 1, IORESOURCE_SUBTRACTIVE); |
| 110 | |
| 111 | res = new_resource(dev, 3); /* IOAPIC */ |
| 112 | res->base = IO_APIC_ADDR; |
| 113 | res->size = 0x00001000; |
| 114 | res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; |
| 115 | |
| 116 | compact_resources(dev); |
| 117 | } |
| 118 | |
| 119 | static void hudson_lpc_set_resources(struct device *dev) |
| 120 | { |
| 121 | struct resource *res; |
| 122 | |
| 123 | /* Special case. SPI Base Address. The SpiRomEnable should STAY set. */ |
| 124 | res = find_resource(dev, 2); |
| 125 | pci_write_config32(dev, SPIROM_BASE_ADDRESS_REGISTER, res->base | SPI_ROM_ENABLE); |
| 126 | |
| 127 | pci_dev_set_resources(dev); |
| 128 | } |
| 129 | |
| 130 | /** |
| 131 | * @brief Enable resources for children devices |
| 132 | * |
Edward O'Callaghan | 4565aea | 2015-06-07 19:42:47 +1000 | [diff] [blame] | 133 | * @param dev the device whose children's resources are to be enabled |
Kyösti Mälkki | e8b4da2 | 2014-10-21 18:22:32 +0300 | [diff] [blame] | 134 | * |
| 135 | */ |
| 136 | static void hudson_lpc_enable_childrens_resources(device_t dev) |
| 137 | { |
| 138 | struct bus *link; |
| 139 | u32 reg, reg_x; |
| 140 | int var_num = 0; |
| 141 | u16 reg_var[3]; |
| 142 | u16 reg_size[1] = {512}; |
| 143 | u8 wiosize = pci_read_config8(dev, 0x74); |
| 144 | |
| 145 | /* Be bit relaxed, tolerate that LPC region might be bigger than resource we try to fit, |
| 146 | * do it like this for all regions < 16 bytes. If there is a resource > 16 bytes |
| 147 | * it must be 512 bytes to be able to allocate the fresh LPC window. |
| 148 | * |
| 149 | * AGESA likes to enable already one LPC region in wide port base 0x64-0x65, |
| 150 | * using DFLT_SIO_PME_BASE_ADDRESS, 512 bytes size |
| 151 | * The code tries to check if resource can fit into this region |
| 152 | */ |
| 153 | |
| 154 | reg = pci_read_config32(dev, 0x44); |
| 155 | reg_x = pci_read_config32(dev, 0x48); |
| 156 | |
| 157 | /* check if ranges are free and not use them if entry is just already taken */ |
| 158 | if (reg_x & (1 << 2)) |
| 159 | var_num = 1; |
| 160 | /* just in case check if someone did not manually set other ranges too */ |
| 161 | if (reg_x & (1 << 24)) |
| 162 | var_num = 2; |
| 163 | |
| 164 | if (reg_x & (1 << 25)) |
| 165 | var_num = 3; |
| 166 | |
| 167 | /* check AGESA region size */ |
| 168 | if (wiosize & (1 << 0)) |
| 169 | reg_size[0] = 16; |
| 170 | |
| 171 | reg_var[2] = pci_read_config16(dev, 0x90); |
| 172 | reg_var[1] = pci_read_config16(dev, 0x66); |
| 173 | reg_var[0] = pci_read_config16(dev, 0x64); |
| 174 | |
| 175 | for (link = dev->link_list; link; link = link->next) { |
| 176 | device_t child; |
| 177 | for (child = link->children; child; |
| 178 | child = child->sibling) { |
| 179 | if (child->enabled |
| 180 | && (child->path.type == DEVICE_PATH_PNP)) { |
| 181 | struct resource *res; |
| 182 | for (res = child->resource_list; res; res = res->next) { |
| 183 | u32 base, end; /* don't need long long */ |
| 184 | u32 rsize, set = 0, set_x = 0; |
| 185 | if (!(res->flags & IORESOURCE_IO)) |
| 186 | continue; |
| 187 | base = res->base; |
| 188 | end = resource_end(res); |
| 189 | /* find a resource size */ |
| 190 | printk(BIOS_DEBUG, "hudson lpc decode:%s, base=0x%08x, end=0x%08x\n", |
| 191 | dev_path(child), base, end); |
| 192 | switch (base) { |
| 193 | case 0x60: /* KB */ |
| 194 | case 0x64: /* MS */ |
| 195 | set |= (1 << 29); |
| 196 | rsize = 1; |
| 197 | break; |
| 198 | case 0x3f8: /* COM1 */ |
| 199 | set |= (1 << 6); |
| 200 | rsize = 8; |
| 201 | break; |
| 202 | case 0x2f8: /* COM2 */ |
| 203 | set |= (1 << 7); |
| 204 | rsize = 8; |
| 205 | break; |
| 206 | case 0x378: /* Parallel 1 */ |
| 207 | set |= (1 << 0); |
| 208 | set |= (1 << 1); /* + 0x778 for ECP */ |
| 209 | rsize = 8; |
| 210 | break; |
| 211 | case 0x3f0: /* FD0 */ |
| 212 | set |= (1 << 26); |
| 213 | rsize = 8; |
| 214 | break; |
| 215 | case 0x220: /* 0x220 - 0x227 */ |
| 216 | set |= (1 << 8); |
| 217 | rsize = 8; |
| 218 | break; |
| 219 | case 0x228: /* 0x228 - 0x22f */ |
| 220 | set |= (1 << 9); |
| 221 | rsize = 8; |
| 222 | break; |
| 223 | case 0x238: /* 0x238 - 0x23f */ |
| 224 | set |= (1 << 10); |
| 225 | rsize = 8; |
| 226 | break; |
| 227 | case 0x300: /* 0x300 -0x301 */ |
| 228 | set |= (1 << 18); |
| 229 | rsize = 2; |
| 230 | break; |
| 231 | case 0x400: |
| 232 | set_x |= (1 << 16); |
| 233 | rsize = 0x40; |
| 234 | break; |
| 235 | case 0x480: |
| 236 | set_x |= (1 << 17); |
| 237 | rsize = 0x40; |
| 238 | break; |
| 239 | case 0x500: |
| 240 | set_x |= (1 << 18); |
| 241 | rsize = 0x40; |
| 242 | break; |
| 243 | case 0x580: |
| 244 | set_x |= (1 << 19); |
| 245 | rsize = 0x40; |
| 246 | break; |
| 247 | case 0x4700: |
| 248 | set_x |= (1 << 22); |
| 249 | rsize = 0xc; |
| 250 | break; |
| 251 | case 0xfd60: |
| 252 | set_x |= (1 << 23); |
| 253 | rsize = 16; |
| 254 | break; |
| 255 | default: |
| 256 | rsize = 0; |
| 257 | /* try AGESA allocated region in region 0 */ |
| 258 | if ((var_num > 0) && ((base >=reg_var[0]) && |
| 259 | ((base + res->size) <= (reg_var[0] + reg_size[0])))) |
| 260 | rsize = reg_size[0]; |
| 261 | } |
| 262 | /* check if region found and matches the enable */ |
| 263 | if (res->size <= rsize) { |
| 264 | reg |= set; |
| 265 | reg_x |= set_x; |
| 266 | /* check if we can fit resource in variable range */ |
| 267 | } else if ((var_num < 3) && |
| 268 | ((res->size <= 16) || (res->size == 512))) { |
| 269 | /* use variable ranges if pre-defined do not match */ |
| 270 | switch (var_num) { |
| 271 | case 0: |
| 272 | reg_x |= (1 << 2); |
| 273 | if (res->size <= 16) { |
| 274 | wiosize |= (1 << 0); |
| 275 | } |
| 276 | break; |
| 277 | case 1: |
| 278 | reg_x |= (1 << 24); |
| 279 | if (res->size <= 16) |
| 280 | wiosize |= (1 << 2); |
| 281 | break; |
| 282 | case 2: |
| 283 | reg_x |= (1 << 25); |
| 284 | if (res->size <= 16) |
| 285 | wiosize |= (1 << 3); |
| 286 | break; |
| 287 | } |
| 288 | reg_var[var_num++] = |
| 289 | base & 0xffff; |
| 290 | } else { |
| 291 | printk(BIOS_ERR, "cannot fit LPC decode region:%s, base=0x%08x, end=0x%08x\n", |
| 292 | dev_path(child), base, end); |
| 293 | } |
| 294 | } |
| 295 | } |
| 296 | } |
| 297 | } |
| 298 | pci_write_config32(dev, 0x44, reg); |
| 299 | pci_write_config32(dev, 0x48, reg_x); |
| 300 | /* Set WideIO for as many IOs found (fall through is on purpose) */ |
| 301 | switch (var_num) { |
| 302 | case 3: |
| 303 | pci_write_config16(dev, 0x90, reg_var[2]); |
| 304 | /* fall through */ |
| 305 | case 2: |
| 306 | pci_write_config16(dev, 0x66, reg_var[1]); |
| 307 | /* fall through */ |
| 308 | case 1: |
| 309 | pci_write_config16(dev, 0x64, reg_var[0]); |
| 310 | break; |
| 311 | } |
| 312 | pci_write_config8(dev, 0x74, wiosize); |
| 313 | } |
| 314 | |
| 315 | static void hudson_lpc_enable_resources(device_t dev) |
| 316 | { |
| 317 | pci_dev_enable_resources(dev); |
| 318 | hudson_lpc_enable_childrens_resources(dev); |
| 319 | } |
| 320 | |
Edward O'Callaghan | 4565aea | 2015-06-07 19:42:47 +1000 | [diff] [blame] | 321 | unsigned long acpi_fill_mcfg(unsigned long current) |
| 322 | { |
| 323 | /* Just a dummy */ |
| 324 | return current; |
| 325 | } |
| 326 | |
Kyösti Mälkki | e8b4da2 | 2014-10-21 18:22:32 +0300 | [diff] [blame] | 327 | static struct pci_operations lops_pci = { |
| 328 | .set_subsystem = pci_dev_set_subsystem, |
| 329 | }; |
| 330 | |
| 331 | static struct device_operations lpc_ops = { |
| 332 | .read_resources = hudson_lpc_read_resources, |
| 333 | .set_resources = hudson_lpc_set_resources, |
| 334 | .enable_resources = hudson_lpc_enable_resources, |
Vladimir Serbinenko | 83f81ca | 2014-11-09 13:30:50 +0100 | [diff] [blame] | 335 | #if IS_ENABLED(CONFIG_HAVE_ACPI_TABLES) |
Dave Frodin | 5c015f0 | 2015-01-27 07:19:04 -0700 | [diff] [blame] | 336 | .write_acpi_tables = acpi_write_hpet, |
Kyösti Mälkki | 0b5b541 | 2014-11-26 08:11:07 +0200 | [diff] [blame] | 337 | #endif |
Kyösti Mälkki | e8b4da2 | 2014-10-21 18:22:32 +0300 | [diff] [blame] | 338 | .init = lpc_init, |
Kyösti Mälkki | d0e212c | 2015-02-26 20:47:47 +0200 | [diff] [blame] | 339 | .scan_bus = scan_lpc_bus, |
Kyösti Mälkki | e8b4da2 | 2014-10-21 18:22:32 +0300 | [diff] [blame] | 340 | .ops_pci = &lops_pci, |
| 341 | }; |
WANG Siyuan | f2dfef0 | 2015-05-20 14:41:01 +0800 | [diff] [blame] | 342 | |
| 343 | static const unsigned short pci_device_ids[] = { |
Kyösti Mälkki | 9d9a552 | 2016-11-19 22:14:59 +0200 | [diff] [blame^] | 344 | PCI_DEVICE_ID_AMD_SB900_LPC, |
WANG Siyuan | f2dfef0 | 2015-05-20 14:41:01 +0800 | [diff] [blame] | 345 | PCI_DEVICE_ID_AMD_CZ_LPC, |
| 346 | 0 |
| 347 | }; |
Kyösti Mälkki | e8b4da2 | 2014-10-21 18:22:32 +0300 | [diff] [blame] | 348 | static const struct pci_driver lpc_driver __pci_driver = { |
| 349 | .ops = &lpc_ops, |
| 350 | .vendor = PCI_VENDOR_ID_AMD, |
WANG Siyuan | f2dfef0 | 2015-05-20 14:41:01 +0800 | [diff] [blame] | 351 | .devices = pci_device_ids, |
Kyösti Mälkki | e8b4da2 | 2014-10-21 18:22:32 +0300 | [diff] [blame] | 352 | }; |