Mario Scheithauer | e510f21 | 2018-11-05 09:13:33 +0100 | [diff] [blame] | 1 | chip soc/intel/apollolake |
| 2 | |
| 3 | device cpu_cluster 0 on |
| 4 | device lapic 0 on end |
| 5 | end |
| 6 | |
| 7 | register "sci_irq" = "SCIS_IRQ10" |
| 8 | |
Mario Scheithauer | e510f21 | 2018-11-05 09:13:33 +0100 | [diff] [blame] | 9 | # EMMC TX DATA Delay 1 |
| 10 | # Refer to EDS-Vol2-22.3. |
| 11 | # [14:8] steps of delay for HS400, each 125ps. |
| 12 | # [6:0] steps of delay for SDR104/HS200, each 125ps. |
| 13 | register "emmc_tx_data_cntl1" = "0x0C16" |
| 14 | |
| 15 | # EMMC TX DATA Delay 2 |
| 16 | # Refer to EDS-Vol2-22.3. |
| 17 | # [30:24] steps of delay for SDR50, each 125ps. |
| 18 | # [22:16] steps of delay for DDR50, each 125ps. |
| 19 | # [14:8] steps of delay for SDR25/HS50, each 125ps. |
| 20 | # [6:0] steps of delay for SDR12, each 125ps. |
| 21 | register "emmc_tx_data_cntl2" = "0x28162828" |
| 22 | |
| 23 | # EMMC RX CMD/DATA Delay 1 |
| 24 | # Refer to EDS-Vol2-22.3. |
| 25 | # [30:24] steps of delay for SDR50, each 125ps. |
| 26 | # [22:16] steps of delay for DDR50, each 125ps. |
| 27 | # [14:8] steps of delay for SDR25/HS50, each 125ps. |
| 28 | # [6:0] steps of delay for SDR12, each 125ps. |
| 29 | register "emmc_rx_cmd_data_cntl1" = "0x00181717" |
| 30 | |
| 31 | # EMMC RX CMD/DATA Delay 2 |
| 32 | # Refer to EDS-Vol2-22.3. |
| 33 | # [17:16] stands for Rx Clock before Output Buffer |
| 34 | # [14:8] steps of delay for Auto Tuning Mode, each 125ps. |
| 35 | # [6:0] steps of delay for HS200, each 125ps. |
| 36 | register "emmc_rx_cmd_data_cntl2" = "0x10008" |
| 37 | |
| 38 | # 0:HS400(Default), 1:HS200, 2:DDR50 |
Mario Scheithauer | 1f21a96 | 2019-07-10 13:15:54 +0200 | [diff] [blame] | 39 | register "emmc_host_max_speed" = "1" |
Mario Scheithauer | e510f21 | 2018-11-05 09:13:33 +0100 | [diff] [blame] | 40 | |
Werner Zeh | 9d40a0b | 2022-12-22 10:23:55 +0100 | [diff] [blame^] | 41 | # I2C7 controller used for PTN |
| 42 | register "common_soc_config" = "{ |
| 43 | .i2c[7] = { |
| 44 | .speed = I2C_SPEED_STANDARD, |
| 45 | .rise_time_ns = 210, |
| 46 | .fall_time_ns = 100, |
| 47 | .data_hold_time_ns = 300, |
| 48 | } |
| 49 | }" |
| 50 | |
Mario Scheithauer | e510f21 | 2018-11-05 09:13:33 +0100 | [diff] [blame] | 51 | device domain 0 on |
| 52 | device pci 00.0 on end # - Host Bridge |
| 53 | device pci 00.1 off end # - DPTF |
| 54 | device pci 00.2 off end # - NPK |
| 55 | device pci 02.0 on end # - Gen - Display |
| 56 | device pci 03.0 off end # - Iunit |
| 57 | device pci 0d.0 on end # - P2SB |
| 58 | device pci 0d.1 off end # - PMC |
| 59 | device pci 0d.2 on end # - SPI |
| 60 | device pci 0d.3 off end # - Shared SRAM |
Werner Zeh | a4e5236 | 2019-04-12 09:10:27 +0200 | [diff] [blame] | 61 | device pci 0e.0 on end # - Audio |
Subrata Banik | e9b9373 | 2020-09-17 15:48:54 +0530 | [diff] [blame] | 62 | device pci 0f.0 on end # - CSE |
Mario Scheithauer | e510f21 | 2018-11-05 09:13:33 +0100 | [diff] [blame] | 63 | device pci 11.0 on end # - ISH |
Mario Scheithauer | f023270 | 2022-01-26 11:53:00 +0100 | [diff] [blame] | 64 | device pci 12.0 on # - SATA |
Sean Rhodes | 5777995 | 2022-05-19 15:35:31 +0100 | [diff] [blame] | 65 | register "SataPortsEnable[0]" = "1" |
| 66 | register "SataPortsEnable[1]" = "1" |
Mario Scheithauer | f023270 | 2022-01-26 11:53:00 +0100 | [diff] [blame] | 67 | register "DisableSataSalpSupport" = "1" |
| 68 | end |
Mario Scheithauer | 92e4ed1 | 2021-01-14 14:54:38 +0100 | [diff] [blame] | 69 | device pci 13.0 on # - RP 2 - PCIe A 0 |
| 70 | register "pcie_rp_clkreq_pin[2]" = "CLKREQ_DISABLED" |
| 71 | register "pcie_rp_hotplug_enable[2]" = "0" |
| 72 | end |
| 73 | device pci 13.1 on # - RP 3 - PCIe A 1 |
| 74 | register "pcie_rp_clkreq_pin[3]" = "CLKREQ_DISABLED" |
| 75 | register "pcie_rp_hotplug_enable[3]" = "0" |
| 76 | end |
| 77 | device pci 13.2 on # - RP 4 - PCIe-A 2 |
| 78 | register "pcie_rp_clkreq_pin[4]" = "CLKREQ_DISABLED" |
| 79 | register "pcie_rp_hotplug_enable[4]" = "0" |
| 80 | end |
| 81 | device pci 13.3 on # - RP 5 - PCIe-A 3 |
| 82 | register "pcie_rp_clkreq_pin[5]" = "CLKREQ_DISABLED" |
| 83 | register "pcie_rp_hotplug_enable[5]" = "0" |
| 84 | end |
| 85 | device pci 14.0 on # - RP 0 - PCIe-B 0 |
| 86 | register "pcie_rp_clkreq_pin[0]" = "CLKREQ_DISABLED" |
| 87 | register "pcie_rp_hotplug_enable[0]" = "0" |
| 88 | end |
| 89 | device pci 14.1 on # - RP 1 - PCIe-B 1 |
| 90 | register "pcie_rp_clkreq_pin[1]" = "CLKREQ_DISABLED" |
| 91 | register "pcie_rp_hotplug_enable[1]" = "0" |
| 92 | end |
Mario Scheithauer | e510f21 | 2018-11-05 09:13:33 +0100 | [diff] [blame] | 93 | device pci 15.0 on end # - XHCI |
| 94 | device pci 15.1 off end # - XDCI |
Mario Scheithauer | adc7d8e | 2018-11-09 10:37:29 +0100 | [diff] [blame] | 95 | device pci 16.0 on end # - I2C 0 |
| 96 | device pci 16.1 on end # - I2C 1 |
| 97 | device pci 16.2 on end # - I2C 2 |
| 98 | device pci 16.3 on end # - I2C 3 |
| 99 | device pci 17.0 on end # - I2C 4 |
| 100 | device pci 17.1 on end # - I2C 5 |
| 101 | device pci 17.2 on end # - I2C 6 |
Uwe Poeche | 9965885 | 2019-11-05 15:44:42 +0100 | [diff] [blame] | 102 | device pci 17.3 on # - I2C 7 |
| 103 | # Enable external display bridge (eDP to LVDS) |
| 104 | chip drivers/i2c/ptn3460 |
| 105 | device i2c 0x60 on end # PTN3460 DP2LVDS Bridge |
| 106 | end |
Werner Zeh | 9d40a0b | 2022-12-22 10:23:55 +0100 | [diff] [blame^] | 107 | # Add dummy I2C device to limit BUS speed to 100 kHz in OS |
| 108 | chip drivers/i2c/generic |
| 109 | register "hid" = ""PRP0001"" |
| 110 | register "speed" = "I2C_SPEED_STANDARD" |
| 111 | device i2c 0x7f on end |
| 112 | end |
| 113 | |
Uwe Poeche | 9965885 | 2019-11-05 15:44:42 +0100 | [diff] [blame] | 114 | end |
Mario Scheithauer | e510f21 | 2018-11-05 09:13:33 +0100 | [diff] [blame] | 115 | device pci 18.0 on end # - UART 0 |
| 116 | device pci 18.1 on end # - UART 1 |
| 117 | device pci 18.2 on end # - UART 2 |
| 118 | device pci 18.3 on end # - UART 3 |
| 119 | device pci 19.0 off end # - SPI 0 |
| 120 | device pci 19.1 off end # - SPI 1 |
| 121 | device pci 19.2 off end # - SPI 2 |
| 122 | device pci 1a.0 off end # - PWM |
Mario Scheithauer | 5d69297 | 2018-11-09 11:04:06 +0100 | [diff] [blame] | 123 | device pci 1b.0 on end # - SDCARD |
Mario Scheithauer | e510f21 | 2018-11-05 09:13:33 +0100 | [diff] [blame] | 124 | device pci 1c.0 on end # - eMMC |
| 125 | device pci 1d.0 off end # - UFS |
| 126 | device pci 1e.0 off end # - SDIO |
Elyes HAOUAS | bda27cd | 2020-06-27 07:17:16 +0200 | [diff] [blame] | 127 | device pci 1f.0 on # - LPC |
Uwe Poeche | fdd0519 | 2019-02-06 12:52:56 +0100 | [diff] [blame] | 128 | chip drivers/pc80/tpm |
| 129 | device pnp 0c31.0 on end |
| 130 | end |
| 131 | end |
Mario Scheithauer | e510f21 | 2018-11-05 09:13:33 +0100 | [diff] [blame] | 132 | device pci 1f.1 on end # - SMBUS |
| 133 | end |
| 134 | end |