Angel Pons | a2ee761 | 2020-04-04 18:51:15 +0200 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
Patrick Georgi | 40a3e32 | 2015-06-22 19:41:29 +0200 | [diff] [blame] | 2 | |
Julius Werner | 73be9dd | 2018-08-07 14:02:55 -0700 | [diff] [blame] | 3 | #include <arch/lib_helpers.h> |
Patrick Georgi | 40a3e32 | 2015-06-22 19:41:29 +0200 | [diff] [blame] | 4 | #include <arch/stages.h> |
Arthur Heymans | 879c9fc | 2019-11-01 21:42:33 +0100 | [diff] [blame] | 5 | #include <cbmem.h> |
Elyes HAOUAS | 20eaef0 | 2019-03-29 17:45:28 +0100 | [diff] [blame] | 6 | #include <console/console.h> |
Kyösti Mälkki | 13f6650 | 2019-03-03 08:01:05 +0200 | [diff] [blame] | 7 | #include <device/mmio.h> |
Patrick Georgi | 40a3e32 | 2015-06-22 19:41:29 +0200 | [diff] [blame] | 8 | #include <soc/addressmap.h> |
| 9 | #include <soc/clock.h> |
| 10 | #include <soc/mmu_operations.h> |
Furquan Shaikh | fdb3a8d | 2015-10-15 15:50:30 -0700 | [diff] [blame] | 11 | #include <soc/mtc.h> |
Patrick Georgi | 40a3e32 | 2015-06-22 19:41:29 +0200 | [diff] [blame] | 12 | |
Julius Werner | 7dcf9d5 | 2015-10-16 13:10:02 -0700 | [diff] [blame] | 13 | static void arm64_arch_timer_init(void) |
Patrick Georgi | 40a3e32 | 2015-06-22 19:41:29 +0200 | [diff] [blame] | 14 | { |
| 15 | uint32_t freq = clock_get_osc_khz() * 1000; |
| 16 | // Set the cntfrq register. |
Julius Werner | 73be9dd | 2018-08-07 14:02:55 -0700 | [diff] [blame] | 17 | raw_write_cntfrq_el0(freq); |
Patrick Georgi | 40a3e32 | 2015-06-22 19:41:29 +0200 | [diff] [blame] | 18 | } |
| 19 | |
Yen Lin | c2eae1a | 2015-05-07 12:28:43 -0700 | [diff] [blame] | 20 | static void mselect_enable_wrap(void) |
| 21 | { |
| 22 | uint32_t reg; |
| 23 | |
| 24 | #define ERR_RESP_EN_SLAVE1 (0x1 << 24) |
| 25 | #define ERR_RESP_EN_SLAVE2 (0x1 << 25) |
| 26 | #define WRAP_TO_INCR_SLAVE0 (0x1 << 27) |
| 27 | #define WRAP_TO_INCR_SLAVE1 (0x1 << 28) |
| 28 | #define WRAP_TO_INCR_SLAVE2 (0x1 << 29) |
| 29 | |
| 30 | reg = read32((void *)TEGRA_MSELECT_CONFIG); |
| 31 | /* Disable error mechanism */ |
| 32 | reg &= ~(ERR_RESP_EN_SLAVE1 | ERR_RESP_EN_SLAVE2); |
| 33 | /* Enable WRAP type conversion */ |
| 34 | reg |= (WRAP_TO_INCR_SLAVE0 | WRAP_TO_INCR_SLAVE1 | |
| 35 | WRAP_TO_INCR_SLAVE2); |
| 36 | write32((void *)TEGRA_MSELECT_CONFIG, reg); |
| 37 | } |
| 38 | |
Julius Werner | 7dcf9d5 | 2015-10-16 13:10:02 -0700 | [diff] [blame] | 39 | /* Tegra-specific entry point, called from assembly in stage_entry.S */ |
| 40 | void ramstage_entry(void); |
| 41 | void ramstage_entry(void) |
Patrick Georgi | 40a3e32 | 2015-06-22 19:41:29 +0200 | [diff] [blame] | 42 | { |
Julius Werner | 7dcf9d5 | 2015-10-16 13:10:02 -0700 | [diff] [blame] | 43 | /* TODO: Move arch timer setup to BL31? */ |
| 44 | arm64_arch_timer_init(); |
| 45 | |
Yen Lin | c2eae1a | 2015-05-07 12:28:43 -0700 | [diff] [blame] | 46 | /* Enable WRAP to INCR burst type conversion in MSELECT */ |
| 47 | mselect_enable_wrap(); |
| 48 | |
Julius Werner | 7dcf9d5 | 2015-10-16 13:10:02 -0700 | [diff] [blame] | 49 | /* TODO: Move TrustZone setup to BL31? */ |
Patrick Georgi | 40a3e32 | 2015-06-22 19:41:29 +0200 | [diff] [blame] | 50 | trustzone_region_init(); |
| 51 | |
| 52 | tegra210_mmu_init(); |
Furquan Shaikh | fdb3a8d | 2015-10-15 15:50:30 -0700 | [diff] [blame] | 53 | |
| 54 | clock_init_arm_generic_timer(); |
| 55 | |
| 56 | if (tegra210_run_mtc() != 0) |
| 57 | printk(BIOS_ERR, "MTC: No training data.\n"); |
Julius Werner | 7dcf9d5 | 2015-10-16 13:10:02 -0700 | [diff] [blame] | 58 | |
Arthur Heymans | 879c9fc | 2019-11-01 21:42:33 +0100 | [diff] [blame] | 59 | /* Ramstage is run on a different core, so passing cbmem_top |
| 60 | via calling arguments is not an option, but it is not a problem |
| 61 | to call cbmem_top_chipset() again here to populate _cbmem_top_ptr. */ |
| 62 | _cbmem_top_ptr = (uintptr_t)cbmem_top_chipset(); |
| 63 | |
Julius Werner | 7dcf9d5 | 2015-10-16 13:10:02 -0700 | [diff] [blame] | 64 | /* Jump to boot state machine in common code. */ |
| 65 | main(); |
Patrick Georgi | 40a3e32 | 2015-06-22 19:41:29 +0200 | [diff] [blame] | 66 | } |