Angel Pons | 4b42983 | 2020-04-02 23:48:50 +0200 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
Kyösti Mälkki | 191d221 | 2014-06-15 12:06:12 +0300 | [diff] [blame] | 2 | |
| 3 | #define __SIMPLE_DEVICE__ |
| 4 | |
Kyösti Mälkki | a963acd | 2019-08-16 20:34:25 +0300 | [diff] [blame] | 5 | #include <arch/romstage.h> |
Kyösti Mälkki | f1b58b7 | 2019-03-01 13:43:02 +0200 | [diff] [blame] | 6 | #include <device/pci_ops.h> |
Kyösti Mälkki | 191d221 | 2014-06-15 12:06:12 +0300 | [diff] [blame] | 7 | #include <cbmem.h> |
Kyösti Mälkki | 2c3fd49 | 2016-07-22 22:52:14 +0300 | [diff] [blame] | 8 | #include <cpu/x86/mtrr.h> |
Kyösti Mälkki | d53fd70 | 2019-08-14 06:25:55 +0300 | [diff] [blame] | 9 | #include <cpu/x86/smm.h> |
Kyösti Mälkki | 2c3fd49 | 2016-07-22 22:52:14 +0300 | [diff] [blame] | 10 | #include <program_loading.h> |
Kyösti Mälkki | f091f4d | 2019-08-14 03:49:21 +0300 | [diff] [blame] | 11 | #include <cpu/intel/smm_reloc.h> |
Angel Pons | 95de231 | 2020-02-17 13:08:53 +0100 | [diff] [blame] | 12 | #include "ironlake.h" |
Kyösti Mälkki | 191d221 | 2014-06-15 12:06:12 +0300 | [diff] [blame] | 13 | |
Kyösti Mälkki | f1e3c76 | 2014-12-22 12:28:07 +0200 | [diff] [blame] | 14 | static uintptr_t smm_region_start(void) |
Kyösti Mälkki | 191d221 | 2014-06-15 12:06:12 +0300 | [diff] [blame] | 15 | { |
| 16 | /* Base of TSEG is top of usable DRAM */ |
Kyösti Mälkki | f1e3c76 | 2014-12-22 12:28:07 +0200 | [diff] [blame] | 17 | uintptr_t tom = pci_read_config32(PCI_DEV(0,0,0), TSEG); |
| 18 | return tom; |
| 19 | } |
| 20 | |
Kyösti Mälkki | d53fd70 | 2019-08-14 06:25:55 +0300 | [diff] [blame] | 21 | static uintptr_t northbridge_get_tseg_base(void) |
Arthur Heymans | 97c7c6b | 2018-05-15 16:45:21 +0200 | [diff] [blame] | 22 | { |
Kyösti Mälkki | d53fd70 | 2019-08-14 06:25:55 +0300 | [diff] [blame] | 23 | return smm_region_start(); |
Arthur Heymans | 97c7c6b | 2018-05-15 16:45:21 +0200 | [diff] [blame] | 24 | } |
| 25 | |
Kyösti Mälkki | d53fd70 | 2019-08-14 06:25:55 +0300 | [diff] [blame] | 26 | static size_t northbridge_get_tseg_size(void) |
Kyösti Mälkki | f6c2068 | 2019-08-02 06:14:50 +0300 | [diff] [blame] | 27 | { |
| 28 | return CONFIG_SMM_TSEG_SIZE; |
| 29 | } |
| 30 | |
Arthur Heymans | 340e4b8 | 2019-10-23 17:25:58 +0200 | [diff] [blame] | 31 | void *cbmem_top_chipset(void) |
Kyösti Mälkki | f1e3c76 | 2014-12-22 12:28:07 +0200 | [diff] [blame] | 32 | { |
| 33 | return (void *) smm_region_start(); |
Kyösti Mälkki | 191d221 | 2014-06-15 12:06:12 +0300 | [diff] [blame] | 34 | } |
Kyösti Mälkki | a4ffe9d | 2016-06-27 13:24:11 +0300 | [diff] [blame] | 35 | |
Kyösti Mälkki | d53fd70 | 2019-08-14 06:25:55 +0300 | [diff] [blame] | 36 | void smm_region(uintptr_t *start, size_t *size) |
Kyösti Mälkki | f6c2068 | 2019-08-02 06:14:50 +0300 | [diff] [blame] | 37 | { |
Kyösti Mälkki | d53fd70 | 2019-08-14 06:25:55 +0300 | [diff] [blame] | 38 | *start = northbridge_get_tseg_base(); |
| 39 | *size = northbridge_get_tseg_size(); |
Kyösti Mälkki | f6c2068 | 2019-08-02 06:14:50 +0300 | [diff] [blame] | 40 | } |
| 41 | |
Kyösti Mälkki | 5bc641a | 2019-08-09 09:37:49 +0300 | [diff] [blame] | 42 | void fill_postcar_frame(struct postcar_frame *pcf) |
Kyösti Mälkki | a4ffe9d | 2016-06-27 13:24:11 +0300 | [diff] [blame] | 43 | { |
Kyösti Mälkki | 2c3fd49 | 2016-07-22 22:52:14 +0300 | [diff] [blame] | 44 | uintptr_t top_of_ram; |
| 45 | |
Kyösti Mälkki | 2c3fd49 | 2016-07-22 22:52:14 +0300 | [diff] [blame] | 46 | /* Cache at least 8 MiB below the top of ram, and at most 8 MiB |
| 47 | * above top of the ram. This satisfies MTRR alignment requirement |
| 48 | * with different TSEG size configurations. |
| 49 | */ |
| 50 | top_of_ram = ALIGN_DOWN((uintptr_t)cbmem_top(), 8*MiB); |
Kyösti Mälkki | 5bc641a | 2019-08-09 09:37:49 +0300 | [diff] [blame] | 51 | postcar_frame_add_mtrr(pcf, top_of_ram - 8*MiB, 8*MiB, MTRR_TYPE_WRBACK); |
| 52 | postcar_frame_add_mtrr(pcf, top_of_ram, 8*MiB, MTRR_TYPE_WRBACK); |
Kyösti Mälkki | a4ffe9d | 2016-06-27 13:24:11 +0300 | [diff] [blame] | 53 | } |