Richard Smith | cb8eab4 | 2006-07-24 04:25:47 +0000 | [diff] [blame] | 1 | /* |
Stefan Reinauer | 7e61e45 | 2008-01-18 10:35:56 +0000 | [diff] [blame] | 2 | * This file is part of the coreboot project. |
Uwe Hermann | 1a9c892 | 2007-04-01 17:24:03 +0000 | [diff] [blame] | 3 | * |
Uwe Hermann | 1683cef | 2008-11-27 00:47:07 +0000 | [diff] [blame] | 4 | * Copyright (C) 2007-2008 Uwe Hermann <uwe@hermann-uwe.de> |
Keith Hui | 59356ca | 2010-03-06 18:16:25 +0000 | [diff] [blame] | 5 | * Copyright (C) 2010 Keith Hui <buurin@gmail.com> |
Uwe Hermann | 1a9c892 | 2007-04-01 17:24:03 +0000 | [diff] [blame] | 6 | * |
| 7 | * This program is free software; you can redistribute it and/or modify |
| 8 | * it under the terms of the GNU General Public License as published by |
| 9 | * the Free Software Foundation; either version 2 of the License, or |
| 10 | * (at your option) any later version. |
| 11 | * |
| 12 | * This program is distributed in the hope that it will be useful, |
| 13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 15 | * GNU General Public License for more details. |
| 16 | * |
| 17 | * You should have received a copy of the GNU General Public License |
| 18 | * along with this program; if not, write to the Free Software |
| 19 | * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA |
Richard Smith | cb8eab4 | 2006-07-24 04:25:47 +0000 | [diff] [blame] | 20 | */ |
| 21 | |
Uwe Hermann | 1a9c892 | 2007-04-01 17:24:03 +0000 | [diff] [blame] | 22 | #include <spd.h> |
| 23 | #include <sdram_mode.h> |
| 24 | #include <delay.h> |
Carl-Daniel Hailfinger | 2ee6779 | 2008-10-01 12:52:52 +0000 | [diff] [blame] | 25 | #include <stdlib.h> |
Uwe Hermann | 1a9c892 | 2007-04-01 17:24:03 +0000 | [diff] [blame] | 26 | #include "i440bx.h" |
Keith Hui | 59356ca | 2010-03-06 18:16:25 +0000 | [diff] [blame] | 27 | #include "raminit.h" |
Richard Smith | cb8eab4 | 2006-07-24 04:25:47 +0000 | [diff] [blame] | 28 | |
Uwe Hermann | 1a9c892 | 2007-04-01 17:24:03 +0000 | [diff] [blame] | 29 | /*----------------------------------------------------------------------------- |
| 30 | Macros and definitions. |
| 31 | -----------------------------------------------------------------------------*/ |
Richard Smith | cb8eab4 | 2006-07-24 04:25:47 +0000 | [diff] [blame] | 32 | |
Uwe Hermann | 1a9c892 | 2007-04-01 17:24:03 +0000 | [diff] [blame] | 33 | /* Debugging macros. */ |
Uwe Hermann | 01ce601 | 2010-03-05 10:03:50 +0000 | [diff] [blame] | 34 | #if CONFIG_DEBUG_RAM_SETUP |
Uwe Hermann | 1a9c892 | 2007-04-01 17:24:03 +0000 | [diff] [blame] | 35 | #define PRINT_DEBUG(x) print_debug(x) |
| 36 | #define PRINT_DEBUG_HEX8(x) print_debug_hex8(x) |
| 37 | #define PRINT_DEBUG_HEX16(x) print_debug_hex16(x) |
| 38 | #define PRINT_DEBUG_HEX32(x) print_debug_hex32(x) |
| 39 | #define DUMPNORTH() dump_pci_device(PCI_DEV(0, 0, 0)) |
Richard Smith | cb8eab4 | 2006-07-24 04:25:47 +0000 | [diff] [blame] | 40 | #else |
Uwe Hermann | 941a6f0 | 2007-04-30 23:27:27 +0000 | [diff] [blame] | 41 | #define PRINT_DEBUG(x) |
Uwe Hermann | 1a9c892 | 2007-04-01 17:24:03 +0000 | [diff] [blame] | 42 | #define PRINT_DEBUG_HEX8(x) |
| 43 | #define PRINT_DEBUG_HEX16(x) |
| 44 | #define PRINT_DEBUG_HEX32(x) |
| 45 | #define DUMPNORTH() |
Richard Smith | cb8eab4 | 2006-07-24 04:25:47 +0000 | [diff] [blame] | 46 | #endif |
| 47 | |
Uwe Hermann | 1683cef | 2008-11-27 00:47:07 +0000 | [diff] [blame] | 48 | #define NB PCI_DEV(0, 0, 0) |
| 49 | |
Uwe Hermann | 1a9c892 | 2007-04-01 17:24:03 +0000 | [diff] [blame] | 50 | /* SDRAMC[7:5] - SDRAM Mode Select (SMS). */ |
| 51 | #define RAM_COMMAND_NORMAL 0x0 |
| 52 | #define RAM_COMMAND_NOP 0x1 |
| 53 | #define RAM_COMMAND_PRECHARGE 0x2 |
| 54 | #define RAM_COMMAND_MRS 0x3 |
| 55 | #define RAM_COMMAND_CBR 0x4 |
Richard Smith | cb8eab4 | 2006-07-24 04:25:47 +0000 | [diff] [blame] | 56 | |
Uwe Hermann | 1a9c892 | 2007-04-01 17:24:03 +0000 | [diff] [blame] | 57 | /* Map the JEDEC SPD refresh rates (array index) to 440BX refresh rates as |
| 58 | * defined in DRAMC[2:0]. |
| 59 | * |
| 60 | * [0] == Normal 15.625 us -> 15.6 us |
| 61 | * [1] == Reduced(.25X) 3.9 us -> 7.8 ns |
| 62 | * [2] == Reduced(.5X) 7.8 us -> 7.8 us |
| 63 | * [3] == Extended(2x) 31.3 us -> 31.2 us |
| 64 | * [4] == Extended(4x) 62.5 us -> 62.4 us |
| 65 | * [5] == Extended(8x) 125 us -> 124.8 us |
| 66 | */ |
| 67 | static const uint32_t refresh_rate_map[] = { |
| 68 | 1, 5, 5, 2, 3, 4 |
| 69 | }; |
Richard Smith | cb8eab4 | 2006-07-24 04:25:47 +0000 | [diff] [blame] | 70 | |
Uwe Hermann | 1a9c892 | 2007-04-01 17:24:03 +0000 | [diff] [blame] | 71 | /* Table format: register, bitmask, value. */ |
| 72 | static const long register_values[] = { |
| 73 | /* NBXCFG - NBX Configuration Register |
Uwe Hermann | f5a6fd2 | 2007-05-27 23:31:31 +0000 | [diff] [blame] | 74 | * 0x50 - 0x53 |
Uwe Hermann | 1a9c892 | 2007-04-01 17:24:03 +0000 | [diff] [blame] | 75 | * |
| 76 | * [31:24] SDRAM Row Without ECC |
| 77 | * 0 = ECC components are populated in this row |
| 78 | * 1 = ECC components are not populated in this row |
| 79 | * [23:19] Reserved |
| 80 | * [18:18] Host Bus Fast Data Ready Enable (HBFDRE) |
| 81 | * Assertion of DRAM data on host bus occurs... |
| 82 | * 0 = ...one clock after sampling snoop results (default) |
| 83 | * 1 = ...on the same clock the snoop result is being sampled |
| 84 | * (this mode is faster by one clock cycle) |
| 85 | * [17:17] ECC - EDO static Drive mode |
| 86 | * 0 = Normal mode (default) |
| 87 | * 1 = ECC signals are always driven |
| 88 | * [16:16] IDSEL_REDIRECT |
| 89 | * 0 = IDSEL1 is allocated to this bridge (default) |
| 90 | * 1 = IDSEL7 is allocated to this bridge |
| 91 | * [15:15] WSC# Handshake Disable |
| 92 | * 1 = Uni-processor mode |
| 93 | * 0 = Dual-processor mode with external IOAPIC (default) |
| 94 | * [14:14] Intel Reserved |
| 95 | * [13:12] Host/DRAM Frequency |
| 96 | * 00 = 100 MHz |
| 97 | * 01 = Reserved |
| 98 | * 10 = 66 MHz |
| 99 | * 11 = Reserved |
| 100 | * [11:11] AGP to PCI Access Enable |
| 101 | * 1 = Enable |
| 102 | * 0 = Disable |
| 103 | * [10:10] PCI Agent to Aperture Access Disable |
| 104 | * 1 = Disable |
| 105 | * 0 = Enable (default) |
| 106 | * [09:09] Aperture Access Global Enable |
| 107 | * 1 = Enable |
| 108 | * 0 = Disable |
| 109 | * [08:07] DRAM Data Integrity Mode (DDIM) |
| 110 | * 00 = Non-ECC |
| 111 | * 01 = EC-only |
| 112 | * 10 = ECC Mode |
| 113 | * 11 = ECC Mode with hardware scrubbing enabled |
| 114 | * [06:06] ECC Diagnostic Mode Enable (EDME) |
| 115 | * 1 = Enable |
| 116 | * 0 = Normal operation mode (default) |
| 117 | * [05:05] MDA Present (MDAP) |
| 118 | * Works in conjunction with the VGA_EN bit. |
| 119 | * VGA_EN MDAP |
| 120 | * 0 x All VGA cycles are sent to PCI |
| 121 | * 1 0 All VGA cycles are sent to AGP |
| 122 | * 1 1 All VGA cycles are sent to AGP, except for |
| 123 | * cycles in the MDA range. |
| 124 | * [04:04] Reserved |
| 125 | * [03:03] USWC Write Post During I/O Bridge Access Enable (UWPIO) |
| 126 | * 1 = Enable |
| 127 | * 0 = Disable |
| 128 | * [02:02] In-Order Queue Depth (IOQD) |
| 129 | * 1 = In-order queue = maximum |
| 130 | * 0 = A7# is sampled asserted (i.e., 0) |
| 131 | * [01:00] Reserved |
Richard Smith | cb8eab4 | 2006-07-24 04:25:47 +0000 | [diff] [blame] | 132 | */ |
Uwe Hermann | 1a9c892 | 2007-04-01 17:24:03 +0000 | [diff] [blame] | 133 | // TODO |
Uwe Hermann | bc359473 | 2007-06-07 22:16:30 +0000 | [diff] [blame] | 134 | NBXCFG + 0, 0x00, 0x0c, |
| 135 | // NBXCFG + 1, 0x00, 0xa0, |
| 136 | NBXCFG + 1, 0x00, 0x80, |
| 137 | NBXCFG + 2, 0x00, 0x00, |
| 138 | NBXCFG + 3, 0x00, 0xff, |
Uwe Hermann | 1a9c892 | 2007-04-01 17:24:03 +0000 | [diff] [blame] | 139 | |
| 140 | /* DRAMC - DRAM Control Register |
| 141 | * 0x57 |
| 142 | * |
| 143 | * [7:6] Reserved |
| 144 | * [5:5] Module Mode Configuration (MMCONFIG) |
| 145 | * TODO |
| 146 | * [4:3] DRAM Type (DT) |
| 147 | * 00 = EDO |
| 148 | * 01 = SDRAM |
| 149 | * 10 = Registered SDRAM |
| 150 | * 11 = Reserved |
| 151 | * Note: EDO, SDRAM and Registered SDRAM cannot be mixed. |
| 152 | * [2:0] DRAM Refresh Rate (DRR) |
| 153 | * 000 = Refresh disabled |
| 154 | * 001 = 15.6 us |
| 155 | * 010 = 31.2 us |
| 156 | * 011 = 62.4 us |
| 157 | * 100 = 124.8 us |
| 158 | * 101 = 249.6 us |
| 159 | * 110 = Reserved |
| 160 | * 111 = Reserved |
Richard Smith | cb8eab4 | 2006-07-24 04:25:47 +0000 | [diff] [blame] | 161 | */ |
Uwe Hermann | 1a9c892 | 2007-04-01 17:24:03 +0000 | [diff] [blame] | 162 | /* Choose SDRAM (not registered), and disable refresh for now. */ |
Uwe Hermann | bc359473 | 2007-06-07 22:16:30 +0000 | [diff] [blame] | 163 | DRAMC, 0x00, 0x08, |
Richard Smith | cb8eab4 | 2006-07-24 04:25:47 +0000 | [diff] [blame] | 164 | |
Uwe Hermann | 1a9c892 | 2007-04-01 17:24:03 +0000 | [diff] [blame] | 165 | /* |
| 166 | * PAM[6:0] - Programmable Attribute Map Registers |
Uwe Hermann | f5a6fd2 | 2007-05-27 23:31:31 +0000 | [diff] [blame] | 167 | * 0x59 - 0x5f |
Uwe Hermann | 1a9c892 | 2007-04-01 17:24:03 +0000 | [diff] [blame] | 168 | * |
| 169 | * 0x59 [3:0] Reserved |
| 170 | * 0x59 [5:4] 0xF0000 - 0xFFFFF BIOS area |
| 171 | * 0x5a [1:0] 0xC0000 - 0xC3FFF ISA add-on BIOS |
| 172 | * 0x5a [5:4] 0xC4000 - 0xC7FFF ISA add-on BIOS |
| 173 | * 0x5b [1:0] 0xC8000 - 0xCBFFF ISA add-on BIOS |
| 174 | * 0x5b [5:4] 0xCC000 - 0xCFFFF ISA add-on BIOS |
| 175 | * 0x5c [1:0] 0xD0000 - 0xD3FFF ISA add-on BIOS |
| 176 | * 0x5c [5:4] 0xD4000 - 0xD7FFF ISA add-on BIOS |
| 177 | * 0x5d [1:0] 0xD8000 - 0xDBFFF ISA add-on BIOS |
| 178 | * 0x5d [5:4] 0xDC000 - 0xDFFFF ISA add-on BIOS |
| 179 | * 0x5e [1:0] 0xE0000 - 0xE3FFF BIOS entension |
| 180 | * 0x5e [5:4] 0xE4000 - 0xE7FFF BIOS entension |
| 181 | * 0x5f [1:0] 0xE8000 - 0xEBFFF BIOS entension |
| 182 | * 0x5f [5:4] 0xEC000 - 0xEFFFF BIOS entension |
| 183 | * |
| 184 | * Bit assignment: |
| 185 | * 00 = DRAM Disabled (all access goes to memory mapped I/O space) |
| 186 | * 01 = Read Only (Reads to DRAM, writes to memory mapped I/O space) |
| 187 | * 10 = Write Only (Writes to DRAM, reads to memory mapped I/O space) |
| 188 | * 11 = Read/Write (all access goes to DRAM) |
| 189 | */ |
Keith Hui | 59356ca | 2010-03-06 18:16:25 +0000 | [diff] [blame] | 190 | |
| 191 | /* |
| 192 | * Map all legacy regions to RAM (read/write). This is required if |
| 193 | * you want to use the RAM area from 768 KB - 1 MB. If the PAM |
| 194 | * registers are not set here appropriately, the RAM in that region |
| 195 | * will not be accessible, thus a RAM check of it will also fail. |
| 196 | * |
| 197 | * TODO: This was set in sdram_set_spd_registers(). |
| 198 | * Test if it still works when set here. |
| 199 | */ |
| 200 | PAM0, 0x00, 0x30, |
| 201 | PAM1, 0x00, 0x33, |
| 202 | PAM2, 0x00, 0x33, |
| 203 | PAM3, 0x00, 0x33, |
| 204 | PAM4, 0x00, 0x33, |
| 205 | PAM5, 0x00, 0x33, |
| 206 | PAM6, 0x00, 0x33, |
Richard Smith | cb8eab4 | 2006-07-24 04:25:47 +0000 | [diff] [blame] | 207 | |
Uwe Hermann | 1a9c892 | 2007-04-01 17:24:03 +0000 | [diff] [blame] | 208 | /* DRB[0:7] - DRAM Row Boundary Registers |
| 209 | * 0x60 - 0x67 |
| 210 | * |
| 211 | * An array of 8 byte registers, which hold the ending memory address |
| 212 | * assigned to each pair of DIMMs, in 8MB granularity. |
| 213 | * |
| 214 | * 0x60 DRB0 = Total memory in row0 (in 8 MB) |
| 215 | * 0x61 DRB1 = Total memory in row0+1 (in 8 MB) |
| 216 | * 0x62 DRB2 = Total memory in row0+1+2 (in 8 MB) |
| 217 | * 0x63 DRB3 = Total memory in row0+1+2+3 (in 8 MB) |
| 218 | * 0x64 DRB4 = Total memory in row0+1+2+3+4 (in 8 MB) |
| 219 | * 0x65 DRB5 = Total memory in row0+1+2+3+4+5 (in 8 MB) |
| 220 | * 0x66 DRB6 = Total memory in row0+1+2+3+4+5+6 (in 8 MB) |
| 221 | * 0x67 DRB7 = Total memory in row0+1+2+3+4+5+6+7 (in 8 MB) |
| 222 | */ |
Uwe Hermann | f5a6fd2 | 2007-05-27 23:31:31 +0000 | [diff] [blame] | 223 | /* Set the DRBs to zero for now, this will be fixed later. */ |
Uwe Hermann | 1a9c892 | 2007-04-01 17:24:03 +0000 | [diff] [blame] | 224 | DRB0, 0x00, 0x00, |
| 225 | DRB1, 0x00, 0x00, |
| 226 | DRB2, 0x00, 0x00, |
| 227 | DRB3, 0x00, 0x00, |
| 228 | DRB4, 0x00, 0x00, |
| 229 | DRB5, 0x00, 0x00, |
| 230 | DRB6, 0x00, 0x00, |
| 231 | DRB7, 0x00, 0x00, |
| 232 | |
| 233 | /* FDHC - Fixed DRAM Hole Control Register |
| 234 | * 0x68 |
| 235 | * |
| 236 | * Controls two fixed DRAM holes: 512 KB - 640 KB and 15 MB - 16 MB. |
| 237 | * |
| 238 | * [7:6] Hole Enable (HEN) |
| 239 | * 00 = None |
| 240 | * 01 = 512 KB - 640 KB (128 KB) |
| 241 | * 10 = 15 MB - 16 MB (1 MB) |
| 242 | * 11 = Reserved |
| 243 | * [5:0] Reserved |
| 244 | */ |
| 245 | /* No memory holes. */ |
| 246 | FDHC, 0x00, 0x00, |
| 247 | |
| 248 | /* RPS - SDRAM Row Page Size Register |
| 249 | * 0x74 - 0x75 |
| 250 | * |
| 251 | * Sets the row page size for SDRAM. For EDO memory, the page |
| 252 | * size is fixed at 2 KB. |
| 253 | * |
| 254 | * [15:0] Page Size (PS) |
| 255 | * TODO |
| 256 | */ |
| 257 | // TODO |
Uwe Hermann | bc359473 | 2007-06-07 22:16:30 +0000 | [diff] [blame] | 258 | RPS + 0, 0x00, 0x00, |
| 259 | RPS + 1, 0x00, 0x00, |
Uwe Hermann | 1a9c892 | 2007-04-01 17:24:03 +0000 | [diff] [blame] | 260 | |
| 261 | /* SDRAMC - SDRAM Control Register |
Uwe Hermann | 7ea18cf | 2007-05-04 00:51:17 +0000 | [diff] [blame] | 262 | * 0x76 - 0x77 |
Uwe Hermann | 1a9c892 | 2007-04-01 17:24:03 +0000 | [diff] [blame] | 263 | * |
| 264 | * [15:10] Reserved |
| 265 | * [09:08] Idle/Pipeline DRAM Leadoff Timing (IPDLT) |
| 266 | * 00 = Illegal |
| 267 | * 01 = Add a clock delay to the lead-off clock count |
| 268 | * 10 = Illegal |
| 269 | * 11 = Illegal |
| 270 | * [07:05] SDRAM Mode Select (SMS) |
| 271 | * 000 = Normal SDRAM Operation (default) |
| 272 | * 001 = NOP Command Enable |
| 273 | * 010 = All Banks Precharge Enable |
| 274 | * 011 = Mode Register Set Enable |
| 275 | * 100 = CBR Enable |
| 276 | * 101 = Reserved |
| 277 | * 110 = Reserved |
| 278 | * 111 = Reserved |
| 279 | * [04:04] SDRAMPWR |
| 280 | * 0 = 3 DIMM configuration |
| 281 | * 1 = 4 DIMM configuration |
| 282 | * [03:03] Leadoff Command Timing (LCT) |
| 283 | * 0 = 4 CS# Clock |
| 284 | * 1 = 3 CS# Clock |
| 285 | * [02:02] CAS# Latency (CL) |
| 286 | * 0 = 3 DCLK CAS# latency |
| 287 | * 1 = 2 DCLK CAS# latency |
| 288 | * [01:01] SDRAM RAS# to CAS# Delay (SRCD) |
| 289 | * 0 = 3 clocks between a row activate and a read or write cmd. |
| 290 | * 1 = 2 clocks between a row activate and a read or write cmd. |
| 291 | * [00:00] SDRAM RAS# Precharge (SRP) |
| 292 | * 0 = 3 clocks of RAS# precharge |
| 293 | * 1 = 2 clocks of RAS# precharge |
| 294 | */ |
Uwe Hermann | bc359473 | 2007-06-07 22:16:30 +0000 | [diff] [blame] | 295 | SDRAMC + 0, 0x00, 0x00, |
Mats Erik Andersson | 45db366 | 2008-09-30 04:52:29 +0000 | [diff] [blame] | 296 | SDRAMC + 1, 0x00, 0x00, |
Uwe Hermann | 1a9c892 | 2007-04-01 17:24:03 +0000 | [diff] [blame] | 297 | |
| 298 | /* PGPOL - Paging Policy Register |
| 299 | * 0x78 - 0x79 |
| 300 | * |
| 301 | * [15:08] Banks per Row (BPR) |
| 302 | * TODO |
| 303 | * 0 = 2 banks |
| 304 | * 1 = 4 banks |
| 305 | * [07:05] Reserved |
| 306 | * [04:04] Intel Reserved |
| 307 | * [03:00] DRAM Idle Timer (DIT) |
| 308 | * 0000 = 0 clocks |
| 309 | * 0001 = 2 clocks |
| 310 | * 0010 = 4 clocks |
| 311 | * 0011 = 8 clocks |
| 312 | * 0100 = 10 clocks |
| 313 | * 0101 = 12 clocks |
| 314 | * 0110 = 16 clocks |
| 315 | * 0111 = 32 clocks |
| 316 | * 1xxx = Infinite (pages are not closed for idle condition) |
| 317 | */ |
| 318 | // TODO |
Uwe Hermann | bc359473 | 2007-06-07 22:16:30 +0000 | [diff] [blame] | 319 | PGPOL + 0, 0x00, 0x00, |
| 320 | PGPOL + 1, 0x00, 0xff, |
Uwe Hermann | 1a9c892 | 2007-04-01 17:24:03 +0000 | [diff] [blame] | 321 | |
| 322 | /* PMCR - Power Management Control Register |
| 323 | * 0x7a |
| 324 | * |
| 325 | * [07:07] Power Down SDRAM Enable (PDSE) |
| 326 | * 1 = Enable |
| 327 | * 0 = Disable |
| 328 | * [06:06] ACPI Control Register Enable (SCRE) |
| 329 | * 1 = Enable |
| 330 | * 0 = Disable (default) |
| 331 | * [05:05] Suspend Refresh Type (SRT) |
| 332 | * 1 = Self refresh mode |
| 333 | * 0 = CBR fresh mode |
| 334 | * [04:04] Normal Refresh Enable (NREF_EN) |
| 335 | * 1 = Enable |
| 336 | * 0 = Disable |
| 337 | * [03:03] Quick Start Mode (QSTART) |
| 338 | * 1 = Quick start mode for the processor is enabled |
| 339 | * [02:02] Gated Clock Enable (GCLKEN) |
| 340 | * 1 = Enable |
| 341 | * 0 = Disable |
| 342 | * [01:01] AGP Disable (AGP_DIS) |
| 343 | * 1 = Disable |
| 344 | * 0 = Enable |
| 345 | * [00:00] CPU reset without PCIRST enable (CRst_En) |
| 346 | * 1 = Enable |
| 347 | * 0 = Disable |
| 348 | */ |
| 349 | /* Enable normal refresh and the gated clock. */ |
| 350 | // TODO: Only do this later? |
| 351 | // PMCR, 0x00, 0x14, |
| 352 | // PMCR, 0x00, 0x10, |
| 353 | PMCR, 0x00, 0x00, |
Keith Hui | 59356ca | 2010-03-06 18:16:25 +0000 | [diff] [blame] | 354 | |
| 355 | /* Enable SCRR.SRRAEN and let BX choose the SRR. */ |
| 356 | SCRR + 1, 0x00, 0x10, |
Uwe Hermann | 1a9c892 | 2007-04-01 17:24:03 +0000 | [diff] [blame] | 357 | }; |
| 358 | |
| 359 | /*----------------------------------------------------------------------------- |
| 360 | SDRAM configuration functions. |
| 361 | -----------------------------------------------------------------------------*/ |
| 362 | |
| 363 | /** |
| 364 | * Send the specified RAM command to all DIMMs. |
| 365 | * |
Uwe Hermann | 8b643cea | 2008-12-09 16:36:12 +0000 | [diff] [blame] | 366 | * @param command The RAM command to send to the DIMM(s). |
Uwe Hermann | 1a9c892 | 2007-04-01 17:24:03 +0000 | [diff] [blame] | 367 | */ |
Uwe Hermann | 8b643cea | 2008-12-09 16:36:12 +0000 | [diff] [blame] | 368 | static void do_ram_command(u32 command) |
Uwe Hermann | 1a9c892 | 2007-04-01 17:24:03 +0000 | [diff] [blame] | 369 | { |
Uwe Hermann | 8b643cea | 2008-12-09 16:36:12 +0000 | [diff] [blame] | 370 | int i, caslatency; |
| 371 | u8 dimm_start, dimm_end; |
| 372 | u16 reg16; |
| 373 | u32 addr, addr_offset; |
Uwe Hermann | 1a9c892 | 2007-04-01 17:24:03 +0000 | [diff] [blame] | 374 | |
| 375 | /* Configure the RAM command. */ |
Uwe Hermann | 8b643cea | 2008-12-09 16:36:12 +0000 | [diff] [blame] | 376 | reg16 = pci_read_config16(NB, SDRAMC); |
| 377 | reg16 &= 0xff1f; /* Clear bits 7-5. */ |
| 378 | reg16 |= (u16) (command << 5); /* Write command into bits 7-5. */ |
| 379 | pci_write_config16(NB, SDRAMC, reg16); |
Uwe Hermann | 1a9c892 | 2007-04-01 17:24:03 +0000 | [diff] [blame] | 380 | |
Uwe Hermann | 8b643cea | 2008-12-09 16:36:12 +0000 | [diff] [blame] | 381 | /* |
| 382 | * RAM_COMMAND_NORMAL affects only the memory controller and |
| 383 | * doesn't need to be "sent" to the DIMMs. |
| 384 | */ |
| 385 | if (command == RAM_COMMAND_NORMAL) |
| 386 | return; |
Uwe Hermann | 1a9c892 | 2007-04-01 17:24:03 +0000 | [diff] [blame] | 387 | |
Uwe Hermann | 8b643cea | 2008-12-09 16:36:12 +0000 | [diff] [blame] | 388 | /* Send the RAM command to each row of memory. */ |
| 389 | dimm_start = 0; |
| 390 | for (i = 0; i < (DIMM_SOCKETS * 2); i++) { |
Keith Hui | 59356ca | 2010-03-06 18:16:25 +0000 | [diff] [blame] | 391 | addr_offset = 0; |
| 392 | caslatency = 3; /* TODO: Dynamically get CAS latency later. */ |
Uwe Hermann | 8b643cea | 2008-12-09 16:36:12 +0000 | [diff] [blame] | 393 | if (command == RAM_COMMAND_MRS) { |
| 394 | /* |
| 395 | * MAA[12:11,9:0] must be inverted when sent to DIMM |
| 396 | * 2 or 3 (no inversion if sent to DIMM 0 or 1). |
| 397 | */ |
| 398 | if ((i >= 0 && i <= 3) && caslatency == 3) |
| 399 | addr_offset = 0x1d0; |
| 400 | if ((i >= 4 && i <= 7) && caslatency == 3) |
| 401 | addr_offset = 0x1e28; |
| 402 | if ((i >= 0 && i <= 3) && caslatency == 2) |
| 403 | addr_offset = 0x150; |
| 404 | if ((i >= 4 && i <= 7) && caslatency == 2) |
| 405 | addr_offset = 0x1ea8; |
| 406 | } |
Uwe Hermann | 1a9c892 | 2007-04-01 17:24:03 +0000 | [diff] [blame] | 407 | |
Uwe Hermann | 8b643cea | 2008-12-09 16:36:12 +0000 | [diff] [blame] | 408 | dimm_end = pci_read_config8(NB, DRB + i); |
| 409 | |
| 410 | addr = (dimm_start * 8 * 1024 * 1024) + addr_offset; |
| 411 | if (dimm_end > dimm_start) { |
| 412 | #if 0 |
| 413 | PRINT_DEBUG(" Sending RAM command 0x"); |
| 414 | PRINT_DEBUG_HEX16(reg16); |
| 415 | PRINT_DEBUG(" to 0x"); |
| 416 | PRINT_DEBUG_HEX32(addr); |
| 417 | PRINT_DEBUG("\r\n"); |
| 418 | #endif |
| 419 | |
| 420 | read32(addr); |
| 421 | } |
| 422 | |
| 423 | /* Set the start of the next DIMM. */ |
| 424 | dimm_start = dimm_end; |
| 425 | } |
Richard Smith | cb8eab4 | 2006-07-24 04:25:47 +0000 | [diff] [blame] | 426 | } |
| 427 | |
Keith Hui | 59356ca | 2010-03-06 18:16:25 +0000 | [diff] [blame] | 428 | static void set_dram_buffer_strength(void) |
| 429 | { |
| 430 | /* TODO: This needs to be set according to the DRAM tech |
| 431 | * (x8, x16, or x32). Argh, Intel provides no docs on this! |
| 432 | * Currently, it needs to be pulled from the output of |
| 433 | * lspci -xxx Rx92 |
| 434 | * |
| 435 | * Relevant registers: MBSC, MBFS, BUFFC. |
| 436 | */ |
| 437 | |
| 438 | pci_write_config8(NB, MBSC, 0x03); |
| 439 | } |
| 440 | |
Uwe Hermann | 1a9c892 | 2007-04-01 17:24:03 +0000 | [diff] [blame] | 441 | /*----------------------------------------------------------------------------- |
| 442 | DIMM-independant configuration functions. |
| 443 | -----------------------------------------------------------------------------*/ |
Richard Smith | cb8eab4 | 2006-07-24 04:25:47 +0000 | [diff] [blame] | 444 | |
Uwe Hermann | 1683cef | 2008-11-27 00:47:07 +0000 | [diff] [blame] | 445 | static void spd_enable_refresh(void) |
Uwe Hermann | 1a9c892 | 2007-04-01 17:24:03 +0000 | [diff] [blame] | 446 | { |
| 447 | int i, value; |
| 448 | uint8_t reg; |
| 449 | |
Uwe Hermann | 1683cef | 2008-11-27 00:47:07 +0000 | [diff] [blame] | 450 | reg = pci_read_config8(NB, DRAMC); |
Uwe Hermann | 1a9c892 | 2007-04-01 17:24:03 +0000 | [diff] [blame] | 451 | |
| 452 | for (i = 0; i < DIMM_SOCKETS; i++) { |
Uwe Hermann | 1683cef | 2008-11-27 00:47:07 +0000 | [diff] [blame] | 453 | value = spd_read_byte(DIMM_SPD_BASE + i, SPD_REFRESH); |
Uwe Hermann | 1a9c892 | 2007-04-01 17:24:03 +0000 | [diff] [blame] | 454 | if (value < 0) |
| 455 | continue; |
| 456 | reg = (reg & 0xf8) | refresh_rate_map[(value & 0x7f)]; |
| 457 | |
| 458 | PRINT_DEBUG(" Enabling refresh (DRAMC = 0x"); |
| 459 | PRINT_DEBUG_HEX8(reg); |
| 460 | PRINT_DEBUG(") for DIMM "); |
| 461 | PRINT_DEBUG_HEX8(i); |
| 462 | PRINT_DEBUG("\r\n"); |
| 463 | } |
| 464 | |
Uwe Hermann | 1683cef | 2008-11-27 00:47:07 +0000 | [diff] [blame] | 465 | pci_write_config8(NB, DRAMC, reg); |
Richard Smith | cb8eab4 | 2006-07-24 04:25:47 +0000 | [diff] [blame] | 466 | } |
| 467 | |
Uwe Hermann | 1a9c892 | 2007-04-01 17:24:03 +0000 | [diff] [blame] | 468 | /*----------------------------------------------------------------------------- |
| 469 | Public interface. |
| 470 | -----------------------------------------------------------------------------*/ |
| 471 | |
Uwe Hermann | 1683cef | 2008-11-27 00:47:07 +0000 | [diff] [blame] | 472 | static void sdram_set_registers(void) |
Uwe Hermann | 1a9c892 | 2007-04-01 17:24:03 +0000 | [diff] [blame] | 473 | { |
| 474 | int i, max; |
Uwe Hermann | bc359473 | 2007-06-07 22:16:30 +0000 | [diff] [blame] | 475 | uint8_t reg; |
Uwe Hermann | 1a9c892 | 2007-04-01 17:24:03 +0000 | [diff] [blame] | 476 | |
| 477 | PRINT_DEBUG("Northbridge prior to SDRAM init:\r\n"); |
| 478 | DUMPNORTH(); |
| 479 | |
Carl-Daniel Hailfinger | 2ee6779 | 2008-10-01 12:52:52 +0000 | [diff] [blame] | 480 | max = ARRAY_SIZE(register_values); |
Uwe Hermann | 1a9c892 | 2007-04-01 17:24:03 +0000 | [diff] [blame] | 481 | |
Uwe Hermann | f5a6fd2 | 2007-05-27 23:31:31 +0000 | [diff] [blame] | 482 | /* Set registers as specified in the register_values[] array. */ |
Uwe Hermann | 1a9c892 | 2007-04-01 17:24:03 +0000 | [diff] [blame] | 483 | for (i = 0; i < max; i += 3) { |
Uwe Hermann | 1683cef | 2008-11-27 00:47:07 +0000 | [diff] [blame] | 484 | reg = pci_read_config8(NB, register_values[i]); |
Uwe Hermann | 1a9c892 | 2007-04-01 17:24:03 +0000 | [diff] [blame] | 485 | reg &= register_values[i + 1]; |
| 486 | reg |= register_values[i + 2] & ~(register_values[i + 1]); |
Uwe Hermann | 1683cef | 2008-11-27 00:47:07 +0000 | [diff] [blame] | 487 | pci_write_config8(NB, register_values[i], reg); |
Keith Hui | 59356ca | 2010-03-06 18:16:25 +0000 | [diff] [blame] | 488 | #if 0 |
Uwe Hermann | 1a9c892 | 2007-04-01 17:24:03 +0000 | [diff] [blame] | 489 | PRINT_DEBUG(" Set register 0x"); |
Uwe Hermann | bc359473 | 2007-06-07 22:16:30 +0000 | [diff] [blame] | 490 | PRINT_DEBUG_HEX8(register_values[i]); |
Uwe Hermann | 1a9c892 | 2007-04-01 17:24:03 +0000 | [diff] [blame] | 491 | PRINT_DEBUG(" to 0x"); |
Uwe Hermann | bc359473 | 2007-06-07 22:16:30 +0000 | [diff] [blame] | 492 | PRINT_DEBUG_HEX8(reg); |
Uwe Hermann | 1a9c892 | 2007-04-01 17:24:03 +0000 | [diff] [blame] | 493 | PRINT_DEBUG("\r\n"); |
Keith Hui | 59356ca | 2010-03-06 18:16:25 +0000 | [diff] [blame] | 494 | #endif |
Uwe Hermann | 1a9c892 | 2007-04-01 17:24:03 +0000 | [diff] [blame] | 495 | } |
| 496 | } |
| 497 | |
Keith Hui | 59356ca | 2010-03-06 18:16:25 +0000 | [diff] [blame] | 498 | struct dimm_size { |
| 499 | unsigned long side1; |
| 500 | unsigned long side2; |
| 501 | }; |
| 502 | |
| 503 | static struct dimm_size spd_get_dimm_size(unsigned int device) |
| 504 | { |
| 505 | struct dimm_size sz; |
| 506 | int i, module_density, dimm_banks; |
| 507 | sz.side1 = 0; |
| 508 | module_density = spd_read_byte(device, SPD_DENSITY_OF_EACH_ROW_ON_MODULE); |
| 509 | dimm_banks = spd_read_byte(device, SPD_NUM_DIMM_BANKS); |
| 510 | |
| 511 | /* Find the size of side1. */ |
| 512 | /* Find the larger value. The larger value is always side1. */ |
| 513 | for (i = 512; i >= 0; i >>= 1) { |
| 514 | if ((module_density & i) == i) { |
| 515 | sz.side1 = i; |
| 516 | break; |
| 517 | } |
| 518 | } |
| 519 | |
| 520 | /* Set to 0 in case it's single sided. */ |
| 521 | sz.side2 = 0; |
| 522 | |
| 523 | /* Test if it's a dual-sided DIMM. */ |
| 524 | if (dimm_banks > 1) { |
| 525 | /* Test if there's a second value. If so it's asymmetrical. */ |
| 526 | if (module_density != i) { |
| 527 | /* |
| 528 | * Find second value, picking up where we left off. |
| 529 | * i >>= 1 done initially to make sure we don't get |
| 530 | * the same value again. |
| 531 | */ |
| 532 | for (i >>= 1; i >= 0; i >>= 1) { |
| 533 | if (module_density == (sz.side1 | i)) { |
| 534 | sz.side2 = i; |
| 535 | break; |
| 536 | } |
| 537 | } |
| 538 | /* If not, it's symmetrical. */ |
| 539 | } else { |
| 540 | sz.side2 = sz.side1; |
| 541 | } |
| 542 | } |
| 543 | |
| 544 | /* |
| 545 | * SPD byte 31 is the memory size divided by 4 so we |
| 546 | * need to muliply by 4 to get the total size. |
| 547 | */ |
| 548 | sz.side1 *= 4; |
| 549 | sz.side2 *= 4; |
| 550 | |
| 551 | return sz; |
| 552 | } |
| 553 | /* |
| 554 | * Sets DRAM attributes one DIMM at a time, based on SPD data. |
| 555 | * Northbridge settings that are set: NBXCFG[31:24], DRB0-DRB7, RPS, DRAMC. |
| 556 | */ |
| 557 | static void set_dram_row_attributes(void) |
| 558 | { |
| 559 | int i, dra, drb, col, width, value, rps, edosd, ecc, nbxecc; |
| 560 | u8 bpr; /* Top 8 bits of PGPOL */ |
| 561 | |
| 562 | edosd = 0; |
| 563 | rps = 0; |
| 564 | drb = 0; |
| 565 | bpr = 0; |
| 566 | nbxecc = 0xff; |
| 567 | |
| 568 | for (i = 0; i < DIMM_SOCKETS; i++) { |
| 569 | unsigned int device; |
| 570 | device = DIMM_SPD_BASE + i; |
| 571 | bpr >>= 2; |
| 572 | |
| 573 | /* First check if a DIMM is actually present. */ |
| 574 | value = spd_read_byte(device, SPD_MEMORY_TYPE); |
| 575 | /* This is 440BX! We do EDO too! */ |
| 576 | if (value == SPD_MEMORY_TYPE_EDO |
| 577 | || value == SPD_MEMORY_TYPE_SDRAM) { |
| 578 | |
| 579 | PRINT_DEBUG("Found "); |
| 580 | if (value == SPD_MEMORY_TYPE_EDO) { |
| 581 | edosd |= 0x02; |
| 582 | } else if (value == SPD_MEMORY_TYPE_SDRAM) { |
| 583 | edosd |= 0x04; |
| 584 | } |
| 585 | PRINT_DEBUG("DIMM in slot "); |
| 586 | PRINT_DEBUG_HEX8(i); |
| 587 | PRINT_DEBUG("\r\n"); |
| 588 | |
| 589 | if (edosd == 0x06) { |
| 590 | print_err("Mixing EDO/SDRAM unsupported!\r\n"); |
| 591 | die("HALT\r\n"); |
| 592 | } |
| 593 | |
| 594 | /* "DRA" is our RPS for the two rows on this DIMM. */ |
| 595 | dra = 0; |
| 596 | |
| 597 | /* Columns */ |
| 598 | col = spd_read_byte(device, SPD_NUM_COLUMNS); |
| 599 | |
| 600 | /* |
| 601 | * Is this an ECC DIMM? Actually will be a 2 if so. |
| 602 | * TODO: Other register than NBXCFG also needs this |
| 603 | * ECC information. |
| 604 | */ |
| 605 | ecc = spd_read_byte(device, SPD_DIMM_CONFIG_TYPE); |
| 606 | |
| 607 | /* Data width */ |
| 608 | width = spd_read_byte(device, SPD_MODULE_DATA_WIDTH_LSB); |
| 609 | |
| 610 | /* Exclude error checking data width from page size calculations */ |
| 611 | if (ecc) { |
| 612 | value = spd_read_byte(device, |
| 613 | SPD_ERROR_CHECKING_SDRAM_WIDTH); |
| 614 | width -= value; |
| 615 | /* ### ECC */ |
| 616 | /* Clear top 2 bits to help set up NBXCFG. */ |
| 617 | ecc &= 0x3f; |
| 618 | } else { |
| 619 | /* Without ECC, top 2 bits should be 11. */ |
| 620 | ecc |= 0xc0; |
| 621 | } |
| 622 | |
| 623 | /* Calculate page size in bits. */ |
| 624 | value = ((1 << col) * width); |
| 625 | |
| 626 | /* Convert to KB. */ |
| 627 | dra = (value >> 13); |
| 628 | |
| 629 | /* Number of banks of DIMM (single or double sided). */ |
| 630 | value = spd_read_byte(device, SPD_NUM_DIMM_BANKS); |
| 631 | |
| 632 | /* Once we have dra, col is done and can be reused. |
| 633 | * So it's reused for number of banks. |
| 634 | */ |
| 635 | col = spd_read_byte(device, SPD_NUM_BANKS_PER_SDRAM); |
| 636 | |
| 637 | if (value == 1) { |
| 638 | /* |
| 639 | * Second bank of 1-bank DIMMs "doesn't have |
| 640 | * ECC" - or anything. |
| 641 | */ |
| 642 | ecc |= 0x80; |
| 643 | if (dra == 2) { |
| 644 | dra = 0x0; /* 2KB */ |
| 645 | } else if (dra == 4) { |
| 646 | dra = 0x1; /* 4KB */ |
| 647 | } else if (dra == 8) { |
| 648 | dra = 0x2; /* 8KB */ |
| 649 | } else { |
| 650 | dra = -1; |
| 651 | } |
| 652 | /* |
| 653 | * Sets a flag in PGPOL[BPR] if this DIMM has |
| 654 | * 4 banks per row. |
| 655 | */ |
| 656 | if (col == 4) |
| 657 | bpr |= 0x40; |
| 658 | } else if (value == 2) { |
| 659 | if (dra == 2) { |
| 660 | dra = 0x0; /* 2KB */ |
| 661 | } else if (dra == 4) { |
| 662 | dra = 0x05; /* 4KB */ |
| 663 | } else if (dra == 8) { |
| 664 | dra = 0x0a; /* 8KB */ |
| 665 | } else { |
| 666 | dra = -1; |
| 667 | } |
| 668 | /* Ditto */ |
| 669 | if (col == 4) |
| 670 | bpr |= 0xc0; |
| 671 | } else { |
| 672 | print_err("# of banks of DIMM unsupported!\r\n"); |
| 673 | die("HALT\r\n"); |
| 674 | } |
| 675 | if (dra == -1) { |
| 676 | print_err("Page size not supported\r\n"); |
| 677 | die("HALT\r\n"); |
| 678 | } |
| 679 | |
| 680 | /* |
| 681 | * 440BX supports asymmetrical dual-sided DIMMs, |
| 682 | * but can't handle DIMMs smaller than 8MB per |
| 683 | * side or larger than 128MB per side. |
| 684 | */ |
| 685 | struct dimm_size sz = spd_get_dimm_size(device); |
| 686 | if ((sz.side1 < 8)) { |
| 687 | print_err("DIMMs smaller than 8MB per side\r\n" |
| 688 | "are not supported on this NB.\r\n"); |
| 689 | die("HALT\r\n"); |
| 690 | } |
| 691 | if ((sz.side1 > 128)) { |
| 692 | print_err ("DIMMs > 128MB per side\r\n" |
| 693 | "are not supported on this NB\r\n"); |
| 694 | die("HALT\r\n"); |
| 695 | } |
| 696 | |
| 697 | /* Divide size by 8 to set up the DRB registers. */ |
| 698 | drb += (sz.side1 / 8); |
| 699 | |
| 700 | /* |
| 701 | * Build the DRB for the next row in MSB so it gets |
| 702 | * placed in DRB[n+1] where it belongs when written |
| 703 | * as a 16-bit word. |
| 704 | */ |
| 705 | drb &= 0xff; |
| 706 | drb |= (drb + (sz.side2 / 8)) << 8; |
| 707 | } else { |
| 708 | #if 0 |
| 709 | PRINT_DEBUG("No DIMM found in slot "); |
| 710 | PRINT_DEBUG_HEX8(i); |
| 711 | PRINT_DEBUG("\r\n"); |
| 712 | #endif |
| 713 | |
| 714 | /* If there's no DIMM in the slot, set dra to 0x00. */ |
| 715 | dra = 0x00; |
| 716 | ecc = 0xc0; |
| 717 | /* Still have to propagate DRB over. */ |
| 718 | drb &= 0xff; |
| 719 | drb |= (drb << 8); |
| 720 | } |
| 721 | |
| 722 | pci_write_config16(NB, DRB + (2 * i), drb); |
| 723 | #if 0 |
| 724 | PRINT_DEBUG("DRB has been set to 0x"); |
| 725 | PRINT_DEBUG_HEX16(drb); |
| 726 | PRINT_DEBUG("\r\n"); |
| 727 | #endif |
| 728 | |
| 729 | /* Brings the upper DRB back down to be base for |
| 730 | * DRB calculations for the next two rows. |
| 731 | */ |
| 732 | drb >>= 8; |
| 733 | |
| 734 | rps |= (dra & 0x0f) << (i * 4); |
| 735 | nbxecc = (nbxecc >> 2) | (ecc & 0xc0); |
| 736 | } |
| 737 | |
| 738 | /* Set paging policy register. */ |
| 739 | pci_write_config8(NB, PGPOL + 1, bpr); |
| 740 | PRINT_DEBUG("PGPOL[BPR] has been set to 0x"); |
| 741 | PRINT_DEBUG_HEX8(bpr); |
| 742 | PRINT_DEBUG("\r\n"); |
| 743 | |
| 744 | /* Set DRAM row page size register. */ |
| 745 | pci_write_config16(NB, RPS, rps); |
| 746 | PRINT_DEBUG("RPS has been set to 0x"); |
| 747 | PRINT_DEBUG_HEX16(rps); |
| 748 | PRINT_DEBUG("\r\n"); |
| 749 | |
| 750 | /* ### ECC */ |
| 751 | pci_write_config8(NB, NBXCFG + 3, nbxecc); |
| 752 | PRINT_DEBUG("NBXECC[31:24] has been set to 0x"); |
| 753 | PRINT_DEBUG_HEX8(nbxecc); |
| 754 | PRINT_DEBUG("\r\n"); |
| 755 | |
| 756 | /* Set DRAMC[4:3] to proper memory type (EDO/SDRAM). |
| 757 | * TODO: Registered SDRAM support. |
| 758 | */ |
| 759 | edosd &= 0x07; |
| 760 | if (edosd & 0x02) { |
| 761 | edosd |= 0x00; |
| 762 | } else if (edosd & 0x04) { |
| 763 | edosd |= 0x08; |
| 764 | } |
| 765 | edosd &= 0x18; |
| 766 | |
| 767 | /* edosd is now in the form needed for DRAMC[4:3]. */ |
| 768 | value = pci_read_config8(NB, DRAMC) & 0xe7; |
| 769 | value |= edosd; |
| 770 | pci_write_config8(NB, DRAMC, value); |
| 771 | PRINT_DEBUG("DRAMC has been set to 0x"); |
| 772 | PRINT_DEBUG_HEX8(value); |
| 773 | PRINT_DEBUG("\r\n"); |
| 774 | } |
| 775 | |
Uwe Hermann | 1683cef | 2008-11-27 00:47:07 +0000 | [diff] [blame] | 776 | static void sdram_set_spd_registers(void) |
Richard Smith | cb8eab4 | 2006-07-24 04:25:47 +0000 | [diff] [blame] | 777 | { |
Keith Hui | 59356ca | 2010-03-06 18:16:25 +0000 | [diff] [blame] | 778 | /* Setup DRAM row boundary registers and other attributes. */ |
| 779 | set_dram_row_attributes(); |
Uwe Hermann | 1a9c892 | 2007-04-01 17:24:03 +0000 | [diff] [blame] | 780 | |
| 781 | /* TODO: Set SDRAMC. */ |
Uwe Hermann | 8b643cea | 2008-12-09 16:36:12 +0000 | [diff] [blame] | 782 | pci_write_config16(NB, SDRAMC, 0x0010); /* SDRAMPWR=1: 4 DIMM config */ |
Uwe Hermann | 1a9c892 | 2007-04-01 17:24:03 +0000 | [diff] [blame] | 783 | |
Keith Hui | 59356ca | 2010-03-06 18:16:25 +0000 | [diff] [blame] | 784 | /* TODO */ |
| 785 | set_dram_buffer_strength(); |
Uwe Hermann | 1a9c892 | 2007-04-01 17:24:03 +0000 | [diff] [blame] | 786 | |
| 787 | /* TODO: Set PMCR? */ |
Uwe Hermann | 1683cef | 2008-11-27 00:47:07 +0000 | [diff] [blame] | 788 | // pci_write_config8(NB, PMCR, 0x14); |
| 789 | pci_write_config8(NB, PMCR, 0x10); |
Uwe Hermann | 1a9c892 | 2007-04-01 17:24:03 +0000 | [diff] [blame] | 790 | |
| 791 | /* TODO? */ |
Uwe Hermann | 1683cef | 2008-11-27 00:47:07 +0000 | [diff] [blame] | 792 | pci_write_config8(NB, DRAMT, 0x03); |
Richard Smith | cb8eab4 | 2006-07-24 04:25:47 +0000 | [diff] [blame] | 793 | } |
| 794 | |
Uwe Hermann | 1683cef | 2008-11-27 00:47:07 +0000 | [diff] [blame] | 795 | static void sdram_enable(void) |
Richard Smith | cb8eab4 | 2006-07-24 04:25:47 +0000 | [diff] [blame] | 796 | { |
Uwe Hermann | 1a9c892 | 2007-04-01 17:24:03 +0000 | [diff] [blame] | 797 | int i; |
Richard Smith | cb8eab4 | 2006-07-24 04:25:47 +0000 | [diff] [blame] | 798 | |
Uwe Hermann | 861f964 | 2007-05-28 14:37:06 +0000 | [diff] [blame] | 799 | /* 0. Wait until power/voltages and clocks are stable (200us). */ |
| 800 | udelay(200); |
Richard Smith | cb8eab4 | 2006-07-24 04:25:47 +0000 | [diff] [blame] | 801 | |
Uwe Hermann | 861f964 | 2007-05-28 14:37:06 +0000 | [diff] [blame] | 802 | /* 1. Apply NOP. Wait 200 clock cycles (200us should do). */ |
Uwe Hermann | 1a9c892 | 2007-04-01 17:24:03 +0000 | [diff] [blame] | 803 | PRINT_DEBUG("RAM Enable 1: Apply NOP\r\n"); |
Uwe Hermann | 8b643cea | 2008-12-09 16:36:12 +0000 | [diff] [blame] | 804 | do_ram_command(RAM_COMMAND_NOP); |
Uwe Hermann | 861f964 | 2007-05-28 14:37:06 +0000 | [diff] [blame] | 805 | udelay(200); |
Richard Smith | cb8eab4 | 2006-07-24 04:25:47 +0000 | [diff] [blame] | 806 | |
Uwe Hermann | 1a9c892 | 2007-04-01 17:24:03 +0000 | [diff] [blame] | 807 | /* 2. Precharge all. Wait tRP. */ |
| 808 | PRINT_DEBUG("RAM Enable 2: Precharge all\r\n"); |
Uwe Hermann | 8b643cea | 2008-12-09 16:36:12 +0000 | [diff] [blame] | 809 | do_ram_command(RAM_COMMAND_PRECHARGE); |
Uwe Hermann | 861f964 | 2007-05-28 14:37:06 +0000 | [diff] [blame] | 810 | udelay(1); |
Richard Smith | cb8eab4 | 2006-07-24 04:25:47 +0000 | [diff] [blame] | 811 | |
Uwe Hermann | 1a9c892 | 2007-04-01 17:24:03 +0000 | [diff] [blame] | 812 | /* 3. Perform 8 refresh cycles. Wait tRC each time. */ |
| 813 | PRINT_DEBUG("RAM Enable 3: CBR\r\n"); |
| 814 | for (i = 0; i < 8; i++) { |
Uwe Hermann | 8b643cea | 2008-12-09 16:36:12 +0000 | [diff] [blame] | 815 | do_ram_command(RAM_COMMAND_CBR); |
Uwe Hermann | 861f964 | 2007-05-28 14:37:06 +0000 | [diff] [blame] | 816 | udelay(1); |
Richard Smith | cb8eab4 | 2006-07-24 04:25:47 +0000 | [diff] [blame] | 817 | } |
Uwe Hermann | 1a9c892 | 2007-04-01 17:24:03 +0000 | [diff] [blame] | 818 | |
| 819 | /* 4. Mode register set. Wait two memory cycles. */ |
| 820 | PRINT_DEBUG("RAM Enable 4: Mode register set\r\n"); |
Uwe Hermann | 8b643cea | 2008-12-09 16:36:12 +0000 | [diff] [blame] | 821 | do_ram_command(RAM_COMMAND_MRS); |
Uwe Hermann | 861f964 | 2007-05-28 14:37:06 +0000 | [diff] [blame] | 822 | udelay(2); |
Uwe Hermann | 1a9c892 | 2007-04-01 17:24:03 +0000 | [diff] [blame] | 823 | |
| 824 | /* 5. Normal operation. */ |
| 825 | PRINT_DEBUG("RAM Enable 5: Normal operation\r\n"); |
Uwe Hermann | 8b643cea | 2008-12-09 16:36:12 +0000 | [diff] [blame] | 826 | do_ram_command(RAM_COMMAND_NORMAL); |
Uwe Hermann | 861f964 | 2007-05-28 14:37:06 +0000 | [diff] [blame] | 827 | udelay(1); |
Uwe Hermann | 1a9c892 | 2007-04-01 17:24:03 +0000 | [diff] [blame] | 828 | |
| 829 | /* 6. Finally enable refresh. */ |
| 830 | PRINT_DEBUG("RAM Enable 6: Enable refresh\r\n"); |
Uwe Hermann | 1683cef | 2008-11-27 00:47:07 +0000 | [diff] [blame] | 831 | // pci_write_config8(NB, PMCR, 0x10); |
| 832 | spd_enable_refresh(); |
Uwe Hermann | 861f964 | 2007-05-28 14:37:06 +0000 | [diff] [blame] | 833 | udelay(1); |
Uwe Hermann | 1a9c892 | 2007-04-01 17:24:03 +0000 | [diff] [blame] | 834 | |
| 835 | PRINT_DEBUG("Northbridge following SDRAM init:\r\n"); |
| 836 | DUMPNORTH(); |
Richard Smith | cb8eab4 | 2006-07-24 04:25:47 +0000 | [diff] [blame] | 837 | } |