Richard Smith | cb8eab4 | 2006-07-24 04:25:47 +0000 | [diff] [blame] | 1 | /* |
Uwe Hermann | 1a9c892 | 2007-04-01 17:24:03 +0000 | [diff] [blame] | 2 | * This file is part of the LinuxBIOS project. |
| 3 | * |
| 4 | * Copyright (C) 2007 Uwe Hermann <uwe@hermann-uwe.de> |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or modify |
| 7 | * it under the terms of the GNU General Public License as published by |
| 8 | * the Free Software Foundation; either version 2 of the License, or |
| 9 | * (at your option) any later version. |
| 10 | * |
| 11 | * This program is distributed in the hope that it will be useful, |
| 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 14 | * GNU General Public License for more details. |
| 15 | * |
| 16 | * You should have received a copy of the GNU General Public License |
| 17 | * along with this program; if not, write to the Free Software |
| 18 | * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA |
Richard Smith | cb8eab4 | 2006-07-24 04:25:47 +0000 | [diff] [blame] | 19 | */ |
| 20 | |
Uwe Hermann | 1a9c892 | 2007-04-01 17:24:03 +0000 | [diff] [blame] | 21 | #include <spd.h> |
| 22 | #include <sdram_mode.h> |
| 23 | #include <delay.h> |
| 24 | #include "i440bx.h" |
Richard Smith | cb8eab4 | 2006-07-24 04:25:47 +0000 | [diff] [blame] | 25 | |
Uwe Hermann | 1a9c892 | 2007-04-01 17:24:03 +0000 | [diff] [blame] | 26 | /*----------------------------------------------------------------------------- |
| 27 | Macros and definitions. |
| 28 | -----------------------------------------------------------------------------*/ |
Richard Smith | cb8eab4 | 2006-07-24 04:25:47 +0000 | [diff] [blame] | 29 | |
Uwe Hermann | 1a9c892 | 2007-04-01 17:24:03 +0000 | [diff] [blame] | 30 | /* Uncomment this to enable debugging output. */ |
| 31 | #define DEBUG_RAM_SETUP 1 |
Richard Smith | cb8eab4 | 2006-07-24 04:25:47 +0000 | [diff] [blame] | 32 | |
Uwe Hermann | 1a9c892 | 2007-04-01 17:24:03 +0000 | [diff] [blame] | 33 | /* Debugging macros. */ |
| 34 | #if defined(DEBUG_RAM_SETUP) |
| 35 | #define PRINT_DEBUG(x) print_debug(x) |
| 36 | #define PRINT_DEBUG_HEX8(x) print_debug_hex8(x) |
| 37 | #define PRINT_DEBUG_HEX16(x) print_debug_hex16(x) |
| 38 | #define PRINT_DEBUG_HEX32(x) print_debug_hex32(x) |
| 39 | #define DUMPNORTH() dump_pci_device(PCI_DEV(0, 0, 0)) |
Richard Smith | cb8eab4 | 2006-07-24 04:25:47 +0000 | [diff] [blame] | 40 | #else |
Uwe Hermann | 941a6f0 | 2007-04-30 23:27:27 +0000 | [diff] [blame^] | 41 | #define PRINT_DEBUG(x) |
Uwe Hermann | 1a9c892 | 2007-04-01 17:24:03 +0000 | [diff] [blame] | 42 | #define PRINT_DEBUG_HEX8(x) |
| 43 | #define PRINT_DEBUG_HEX16(x) |
| 44 | #define PRINT_DEBUG_HEX32(x) |
| 45 | #define DUMPNORTH() |
Richard Smith | cb8eab4 | 2006-07-24 04:25:47 +0000 | [diff] [blame] | 46 | #endif |
| 47 | |
Uwe Hermann | 1a9c892 | 2007-04-01 17:24:03 +0000 | [diff] [blame] | 48 | /* SDRAMC[7:5] - SDRAM Mode Select (SMS). */ |
| 49 | #define RAM_COMMAND_NORMAL 0x0 |
| 50 | #define RAM_COMMAND_NOP 0x1 |
| 51 | #define RAM_COMMAND_PRECHARGE 0x2 |
| 52 | #define RAM_COMMAND_MRS 0x3 |
| 53 | #define RAM_COMMAND_CBR 0x4 |
Richard Smith | cb8eab4 | 2006-07-24 04:25:47 +0000 | [diff] [blame] | 54 | |
Uwe Hermann | 1a9c892 | 2007-04-01 17:24:03 +0000 | [diff] [blame] | 55 | /* Map the JEDEC SPD refresh rates (array index) to 440BX refresh rates as |
| 56 | * defined in DRAMC[2:0]. |
| 57 | * |
| 58 | * [0] == Normal 15.625 us -> 15.6 us |
| 59 | * [1] == Reduced(.25X) 3.9 us -> 7.8 ns |
| 60 | * [2] == Reduced(.5X) 7.8 us -> 7.8 us |
| 61 | * [3] == Extended(2x) 31.3 us -> 31.2 us |
| 62 | * [4] == Extended(4x) 62.5 us -> 62.4 us |
| 63 | * [5] == Extended(8x) 125 us -> 124.8 us |
| 64 | */ |
| 65 | static const uint32_t refresh_rate_map[] = { |
| 66 | 1, 5, 5, 2, 3, 4 |
| 67 | }; |
Richard Smith | cb8eab4 | 2006-07-24 04:25:47 +0000 | [diff] [blame] | 68 | |
Uwe Hermann | 1a9c892 | 2007-04-01 17:24:03 +0000 | [diff] [blame] | 69 | /* Table format: register, bitmask, value. */ |
| 70 | static const long register_values[] = { |
| 71 | /* NBXCFG - NBX Configuration Register |
| 72 | * 0x50 |
| 73 | * |
| 74 | * [31:24] SDRAM Row Without ECC |
| 75 | * 0 = ECC components are populated in this row |
| 76 | * 1 = ECC components are not populated in this row |
| 77 | * [23:19] Reserved |
| 78 | * [18:18] Host Bus Fast Data Ready Enable (HBFDRE) |
| 79 | * Assertion of DRAM data on host bus occurs... |
| 80 | * 0 = ...one clock after sampling snoop results (default) |
| 81 | * 1 = ...on the same clock the snoop result is being sampled |
| 82 | * (this mode is faster by one clock cycle) |
| 83 | * [17:17] ECC - EDO static Drive mode |
| 84 | * 0 = Normal mode (default) |
| 85 | * 1 = ECC signals are always driven |
| 86 | * [16:16] IDSEL_REDIRECT |
| 87 | * 0 = IDSEL1 is allocated to this bridge (default) |
| 88 | * 1 = IDSEL7 is allocated to this bridge |
| 89 | * [15:15] WSC# Handshake Disable |
| 90 | * 1 = Uni-processor mode |
| 91 | * 0 = Dual-processor mode with external IOAPIC (default) |
| 92 | * [14:14] Intel Reserved |
| 93 | * [13:12] Host/DRAM Frequency |
| 94 | * 00 = 100 MHz |
| 95 | * 01 = Reserved |
| 96 | * 10 = 66 MHz |
| 97 | * 11 = Reserved |
| 98 | * [11:11] AGP to PCI Access Enable |
| 99 | * 1 = Enable |
| 100 | * 0 = Disable |
| 101 | * [10:10] PCI Agent to Aperture Access Disable |
| 102 | * 1 = Disable |
| 103 | * 0 = Enable (default) |
| 104 | * [09:09] Aperture Access Global Enable |
| 105 | * 1 = Enable |
| 106 | * 0 = Disable |
| 107 | * [08:07] DRAM Data Integrity Mode (DDIM) |
| 108 | * 00 = Non-ECC |
| 109 | * 01 = EC-only |
| 110 | * 10 = ECC Mode |
| 111 | * 11 = ECC Mode with hardware scrubbing enabled |
| 112 | * [06:06] ECC Diagnostic Mode Enable (EDME) |
| 113 | * 1 = Enable |
| 114 | * 0 = Normal operation mode (default) |
| 115 | * [05:05] MDA Present (MDAP) |
| 116 | * Works in conjunction with the VGA_EN bit. |
| 117 | * VGA_EN MDAP |
| 118 | * 0 x All VGA cycles are sent to PCI |
| 119 | * 1 0 All VGA cycles are sent to AGP |
| 120 | * 1 1 All VGA cycles are sent to AGP, except for |
| 121 | * cycles in the MDA range. |
| 122 | * [04:04] Reserved |
| 123 | * [03:03] USWC Write Post During I/O Bridge Access Enable (UWPIO) |
| 124 | * 1 = Enable |
| 125 | * 0 = Disable |
| 126 | * [02:02] In-Order Queue Depth (IOQD) |
| 127 | * 1 = In-order queue = maximum |
| 128 | * 0 = A7# is sampled asserted (i.e., 0) |
| 129 | * [01:00] Reserved |
Richard Smith | cb8eab4 | 2006-07-24 04:25:47 +0000 | [diff] [blame] | 130 | */ |
Uwe Hermann | 1a9c892 | 2007-04-01 17:24:03 +0000 | [diff] [blame] | 131 | // TODO |
| 132 | NBXCFG, 0x00000000, 0xff00a00c, |
| 133 | |
| 134 | /* DRAMC - DRAM Control Register |
| 135 | * 0x57 |
| 136 | * |
| 137 | * [7:6] Reserved |
| 138 | * [5:5] Module Mode Configuration (MMCONFIG) |
| 139 | * TODO |
| 140 | * [4:3] DRAM Type (DT) |
| 141 | * 00 = EDO |
| 142 | * 01 = SDRAM |
| 143 | * 10 = Registered SDRAM |
| 144 | * 11 = Reserved |
| 145 | * Note: EDO, SDRAM and Registered SDRAM cannot be mixed. |
| 146 | * [2:0] DRAM Refresh Rate (DRR) |
| 147 | * 000 = Refresh disabled |
| 148 | * 001 = 15.6 us |
| 149 | * 010 = 31.2 us |
| 150 | * 011 = 62.4 us |
| 151 | * 100 = 124.8 us |
| 152 | * 101 = 249.6 us |
| 153 | * 110 = Reserved |
| 154 | * 111 = Reserved |
Richard Smith | cb8eab4 | 2006-07-24 04:25:47 +0000 | [diff] [blame] | 155 | */ |
Uwe Hermann | 1a9c892 | 2007-04-01 17:24:03 +0000 | [diff] [blame] | 156 | /* Choose SDRAM (not registered), and disable refresh for now. */ |
| 157 | DRAMC, 0x00, 0x8, |
Richard Smith | cb8eab4 | 2006-07-24 04:25:47 +0000 | [diff] [blame] | 158 | |
Uwe Hermann | 1a9c892 | 2007-04-01 17:24:03 +0000 | [diff] [blame] | 159 | /* |
| 160 | * PAM[6:0] - Programmable Attribute Map Registers |
| 161 | * |
| 162 | * 0x59 [3:0] Reserved |
| 163 | * 0x59 [5:4] 0xF0000 - 0xFFFFF BIOS area |
| 164 | * 0x5a [1:0] 0xC0000 - 0xC3FFF ISA add-on BIOS |
| 165 | * 0x5a [5:4] 0xC4000 - 0xC7FFF ISA add-on BIOS |
| 166 | * 0x5b [1:0] 0xC8000 - 0xCBFFF ISA add-on BIOS |
| 167 | * 0x5b [5:4] 0xCC000 - 0xCFFFF ISA add-on BIOS |
| 168 | * 0x5c [1:0] 0xD0000 - 0xD3FFF ISA add-on BIOS |
| 169 | * 0x5c [5:4] 0xD4000 - 0xD7FFF ISA add-on BIOS |
| 170 | * 0x5d [1:0] 0xD8000 - 0xDBFFF ISA add-on BIOS |
| 171 | * 0x5d [5:4] 0xDC000 - 0xDFFFF ISA add-on BIOS |
| 172 | * 0x5e [1:0] 0xE0000 - 0xE3FFF BIOS entension |
| 173 | * 0x5e [5:4] 0xE4000 - 0xE7FFF BIOS entension |
| 174 | * 0x5f [1:0] 0xE8000 - 0xEBFFF BIOS entension |
| 175 | * 0x5f [5:4] 0xEC000 - 0xEFFFF BIOS entension |
| 176 | * |
| 177 | * Bit assignment: |
| 178 | * 00 = DRAM Disabled (all access goes to memory mapped I/O space) |
| 179 | * 01 = Read Only (Reads to DRAM, writes to memory mapped I/O space) |
| 180 | * 10 = Write Only (Writes to DRAM, reads to memory mapped I/O space) |
| 181 | * 11 = Read/Write (all access goes to DRAM) |
| 182 | */ |
| 183 | // TODO |
| 184 | PAM0, 0x00000000, 0x00, |
| 185 | PAM1, 0x00000000, 0x00, |
| 186 | PAM2, 0x00000000, 0x00, |
| 187 | PAM3, 0x00000000, 0x00, |
| 188 | PAM4, 0x00000000, 0x00, |
| 189 | PAM5, 0x00000000, 0x00, |
| 190 | PAM6, 0x00000000, 0x00, |
Richard Smith | cb8eab4 | 2006-07-24 04:25:47 +0000 | [diff] [blame] | 191 | |
Uwe Hermann | 1a9c892 | 2007-04-01 17:24:03 +0000 | [diff] [blame] | 192 | /* DRB[0:7] - DRAM Row Boundary Registers |
| 193 | * 0x60 - 0x67 |
| 194 | * |
| 195 | * An array of 8 byte registers, which hold the ending memory address |
| 196 | * assigned to each pair of DIMMs, in 8MB granularity. |
| 197 | * |
| 198 | * 0x60 DRB0 = Total memory in row0 (in 8 MB) |
| 199 | * 0x61 DRB1 = Total memory in row0+1 (in 8 MB) |
| 200 | * 0x62 DRB2 = Total memory in row0+1+2 (in 8 MB) |
| 201 | * 0x63 DRB3 = Total memory in row0+1+2+3 (in 8 MB) |
| 202 | * 0x64 DRB4 = Total memory in row0+1+2+3+4 (in 8 MB) |
| 203 | * 0x65 DRB5 = Total memory in row0+1+2+3+4+5 (in 8 MB) |
| 204 | * 0x66 DRB6 = Total memory in row0+1+2+3+4+5+6 (in 8 MB) |
| 205 | * 0x67 DRB7 = Total memory in row0+1+2+3+4+5+6+7 (in 8 MB) |
| 206 | */ |
| 207 | // TODO |
| 208 | DRB0, 0x00, 0x00, |
| 209 | DRB1, 0x00, 0x00, |
| 210 | DRB2, 0x00, 0x00, |
| 211 | DRB3, 0x00, 0x00, |
| 212 | DRB4, 0x00, 0x00, |
| 213 | DRB5, 0x00, 0x00, |
| 214 | DRB6, 0x00, 0x00, |
| 215 | DRB7, 0x00, 0x00, |
| 216 | |
| 217 | /* FDHC - Fixed DRAM Hole Control Register |
| 218 | * 0x68 |
| 219 | * |
| 220 | * Controls two fixed DRAM holes: 512 KB - 640 KB and 15 MB - 16 MB. |
| 221 | * |
| 222 | * [7:6] Hole Enable (HEN) |
| 223 | * 00 = None |
| 224 | * 01 = 512 KB - 640 KB (128 KB) |
| 225 | * 10 = 15 MB - 16 MB (1 MB) |
| 226 | * 11 = Reserved |
| 227 | * [5:0] Reserved |
| 228 | */ |
| 229 | /* No memory holes. */ |
| 230 | FDHC, 0x00, 0x00, |
| 231 | |
| 232 | /* RPS - SDRAM Row Page Size Register |
| 233 | * 0x74 - 0x75 |
| 234 | * |
| 235 | * Sets the row page size for SDRAM. For EDO memory, the page |
| 236 | * size is fixed at 2 KB. |
| 237 | * |
| 238 | * [15:0] Page Size (PS) |
| 239 | * TODO |
| 240 | */ |
| 241 | // TODO |
| 242 | RPS, 0x0000, 0x0000, |
| 243 | |
| 244 | /* SDRAMC - SDRAM Control Register |
| 245 | * 0x76-0x77 |
| 246 | * |
| 247 | * [15:10] Reserved |
| 248 | * [09:08] Idle/Pipeline DRAM Leadoff Timing (IPDLT) |
| 249 | * 00 = Illegal |
| 250 | * 01 = Add a clock delay to the lead-off clock count |
| 251 | * 10 = Illegal |
| 252 | * 11 = Illegal |
| 253 | * [07:05] SDRAM Mode Select (SMS) |
| 254 | * 000 = Normal SDRAM Operation (default) |
| 255 | * 001 = NOP Command Enable |
| 256 | * 010 = All Banks Precharge Enable |
| 257 | * 011 = Mode Register Set Enable |
| 258 | * 100 = CBR Enable |
| 259 | * 101 = Reserved |
| 260 | * 110 = Reserved |
| 261 | * 111 = Reserved |
| 262 | * [04:04] SDRAMPWR |
| 263 | * 0 = 3 DIMM configuration |
| 264 | * 1 = 4 DIMM configuration |
| 265 | * [03:03] Leadoff Command Timing (LCT) |
| 266 | * 0 = 4 CS# Clock |
| 267 | * 1 = 3 CS# Clock |
| 268 | * [02:02] CAS# Latency (CL) |
| 269 | * 0 = 3 DCLK CAS# latency |
| 270 | * 1 = 2 DCLK CAS# latency |
| 271 | * [01:01] SDRAM RAS# to CAS# Delay (SRCD) |
| 272 | * 0 = 3 clocks between a row activate and a read or write cmd. |
| 273 | * 1 = 2 clocks between a row activate and a read or write cmd. |
| 274 | * [00:00] SDRAM RAS# Precharge (SRP) |
| 275 | * 0 = 3 clocks of RAS# precharge |
| 276 | * 1 = 2 clocks of RAS# precharge |
| 277 | */ |
| 278 | SDRAMC, 0x0000, 0x0000, |
| 279 | |
| 280 | /* PGPOL - Paging Policy Register |
| 281 | * 0x78 - 0x79 |
| 282 | * |
| 283 | * [15:08] Banks per Row (BPR) |
| 284 | * TODO |
| 285 | * 0 = 2 banks |
| 286 | * 1 = 4 banks |
| 287 | * [07:05] Reserved |
| 288 | * [04:04] Intel Reserved |
| 289 | * [03:00] DRAM Idle Timer (DIT) |
| 290 | * 0000 = 0 clocks |
| 291 | * 0001 = 2 clocks |
| 292 | * 0010 = 4 clocks |
| 293 | * 0011 = 8 clocks |
| 294 | * 0100 = 10 clocks |
| 295 | * 0101 = 12 clocks |
| 296 | * 0110 = 16 clocks |
| 297 | * 0111 = 32 clocks |
| 298 | * 1xxx = Infinite (pages are not closed for idle condition) |
| 299 | */ |
| 300 | // TODO |
| 301 | PGPOL, 0x0000, 0xff00, |
| 302 | |
| 303 | /* PMCR - Power Management Control Register |
| 304 | * 0x7a |
| 305 | * |
| 306 | * [07:07] Power Down SDRAM Enable (PDSE) |
| 307 | * 1 = Enable |
| 308 | * 0 = Disable |
| 309 | * [06:06] ACPI Control Register Enable (SCRE) |
| 310 | * 1 = Enable |
| 311 | * 0 = Disable (default) |
| 312 | * [05:05] Suspend Refresh Type (SRT) |
| 313 | * 1 = Self refresh mode |
| 314 | * 0 = CBR fresh mode |
| 315 | * [04:04] Normal Refresh Enable (NREF_EN) |
| 316 | * 1 = Enable |
| 317 | * 0 = Disable |
| 318 | * [03:03] Quick Start Mode (QSTART) |
| 319 | * 1 = Quick start mode for the processor is enabled |
| 320 | * [02:02] Gated Clock Enable (GCLKEN) |
| 321 | * 1 = Enable |
| 322 | * 0 = Disable |
| 323 | * [01:01] AGP Disable (AGP_DIS) |
| 324 | * 1 = Disable |
| 325 | * 0 = Enable |
| 326 | * [00:00] CPU reset without PCIRST enable (CRst_En) |
| 327 | * 1 = Enable |
| 328 | * 0 = Disable |
| 329 | */ |
| 330 | /* Enable normal refresh and the gated clock. */ |
| 331 | // TODO: Only do this later? |
| 332 | // PMCR, 0x00, 0x14, |
| 333 | // PMCR, 0x00, 0x10, |
| 334 | PMCR, 0x00, 0x00, |
| 335 | }; |
| 336 | |
| 337 | /*----------------------------------------------------------------------------- |
| 338 | SDRAM configuration functions. |
| 339 | -----------------------------------------------------------------------------*/ |
| 340 | |
| 341 | /** |
| 342 | * Send the specified RAM command to all DIMMs. |
| 343 | * |
| 344 | * @param Memory controller |
| 345 | * @param TODO |
| 346 | * @param TODO |
| 347 | */ |
| 348 | static void do_ram_command(const struct mem_controller *ctrl, |
| 349 | uint32_t command, uint32_t addr_offset) |
| 350 | { |
| 351 | int i; |
| 352 | uint16_t reg; |
| 353 | |
| 354 | /* TODO: Support for multiple DIMMs. */ |
| 355 | |
| 356 | /* Configure the RAM command. */ |
| 357 | reg = pci_read_config16(ctrl->d0, SDRAMC); |
| 358 | reg &= 0xff1f; /* Clear bits 7-5. */ |
| 359 | reg |= (uint16_t) (command << 5); |
| 360 | pci_write_config16(ctrl->d0, SDRAMC, reg); |
| 361 | |
| 362 | /* RAM_COMMAND_NORMAL affects only the memory controller and |
| 363 | doesn't need to be "sent" to the DIMMs. */ |
| 364 | /* if (command == RAM_COMMAND_NORMAL) return; */ |
| 365 | |
| 366 | PRINT_DEBUG(" Sending RAM command 0x"); |
| 367 | PRINT_DEBUG_HEX16(reg); |
| 368 | PRINT_DEBUG(" to 0x"); |
| 369 | PRINT_DEBUG_HEX32(0 + addr_offset); // FIXME |
| 370 | PRINT_DEBUG("\r\n"); |
| 371 | |
| 372 | /* Read from (DIMM start address + addr_offset). */ |
| 373 | read32(0 + addr_offset); // FIXME |
Richard Smith | cb8eab4 | 2006-07-24 04:25:47 +0000 | [diff] [blame] | 374 | } |
| 375 | |
Uwe Hermann | 1a9c892 | 2007-04-01 17:24:03 +0000 | [diff] [blame] | 376 | /*----------------------------------------------------------------------------- |
| 377 | DIMM-independant configuration functions. |
| 378 | -----------------------------------------------------------------------------*/ |
Richard Smith | cb8eab4 | 2006-07-24 04:25:47 +0000 | [diff] [blame] | 379 | |
Uwe Hermann | 1a9c892 | 2007-04-01 17:24:03 +0000 | [diff] [blame] | 380 | /** |
| 381 | * TODO. |
| 382 | * |
| 383 | * @param Memory controller |
| 384 | */ |
| 385 | static void spd_enable_refresh(const struct mem_controller *ctrl) |
| 386 | { |
| 387 | int i, value; |
| 388 | uint8_t reg; |
| 389 | |
| 390 | reg = pci_read_config8(ctrl->d0, DRAMC); |
| 391 | |
| 392 | for (i = 0; i < DIMM_SOCKETS; i++) { |
| 393 | value = spd_read_byte(ctrl->channel0[i], SPD_REFRESH); |
| 394 | if (value < 0) |
| 395 | continue; |
| 396 | reg = (reg & 0xf8) | refresh_rate_map[(value & 0x7f)]; |
| 397 | |
| 398 | PRINT_DEBUG(" Enabling refresh (DRAMC = 0x"); |
| 399 | PRINT_DEBUG_HEX8(reg); |
| 400 | PRINT_DEBUG(") for DIMM "); |
| 401 | PRINT_DEBUG_HEX8(i); |
| 402 | PRINT_DEBUG("\r\n"); |
| 403 | } |
| 404 | |
| 405 | pci_write_config8(ctrl->d0, DRAMC, reg); |
Richard Smith | cb8eab4 | 2006-07-24 04:25:47 +0000 | [diff] [blame] | 406 | } |
| 407 | |
Uwe Hermann | 1a9c892 | 2007-04-01 17:24:03 +0000 | [diff] [blame] | 408 | /*----------------------------------------------------------------------------- |
| 409 | Public interface. |
| 410 | -----------------------------------------------------------------------------*/ |
| 411 | |
| 412 | /** |
| 413 | * TODO. |
| 414 | * |
| 415 | * @param Memory controller |
| 416 | */ |
| 417 | static void sdram_set_registers(const struct mem_controller *ctrl) |
| 418 | { |
| 419 | int i, max; |
| 420 | uint32_t reg; |
| 421 | |
| 422 | PRINT_DEBUG("Northbridge prior to SDRAM init:\r\n"); |
| 423 | DUMPNORTH(); |
| 424 | |
| 425 | max = sizeof(register_values) / sizeof(register_values[0]); |
| 426 | |
| 427 | /* Set registers as specified in the register_values array. */ |
| 428 | for (i = 0; i < max; i += 3) { |
| 429 | reg = pci_read_config32(ctrl->d0, register_values[i]); |
| 430 | reg &= register_values[i + 1]; |
| 431 | reg |= register_values[i + 2] & ~(register_values[i + 1]); |
| 432 | pci_write_config32(ctrl->d0, register_values[i], reg); |
| 433 | |
| 434 | PRINT_DEBUG(" Set register 0x"); |
| 435 | PRINT_DEBUG_HEX32(register_values[i]); |
| 436 | PRINT_DEBUG(" to 0x"); |
| 437 | PRINT_DEBUG_HEX32(reg); |
| 438 | PRINT_DEBUG("\r\n"); |
| 439 | } |
| 440 | } |
| 441 | |
| 442 | /** |
| 443 | * TODO. |
| 444 | * |
| 445 | * @param Memory controller |
| 446 | */ |
Richard Smith | cb8eab4 | 2006-07-24 04:25:47 +0000 | [diff] [blame] | 447 | static void sdram_set_spd_registers(const struct mem_controller *ctrl) |
| 448 | { |
Uwe Hermann | 1a9c892 | 2007-04-01 17:24:03 +0000 | [diff] [blame] | 449 | /* TODO: Don't hardcode the values here, get info via SPD. */ |
| 450 | |
| 451 | /* TODO: Set DRB0-DRB7. */ |
| 452 | pci_write_config8(ctrl->d0, DRB0, 0x08); |
| 453 | pci_write_config8(ctrl->d0, DRB1, 0x08); |
| 454 | pci_write_config8(ctrl->d0, DRB2, 0x08); |
| 455 | pci_write_config8(ctrl->d0, DRB3, 0x08); |
| 456 | pci_write_config8(ctrl->d0, DRB4, 0x08); |
| 457 | pci_write_config8(ctrl->d0, DRB5, 0x08); |
| 458 | pci_write_config8(ctrl->d0, DRB6, 0x08); |
| 459 | pci_write_config8(ctrl->d0, DRB7, 0x08); |
| 460 | |
| 461 | /* TODO: Set DRAMC. Don't enable refresh for now. */ |
| 462 | pci_write_config8(ctrl->d0, DRAMC, 0x08); |
| 463 | |
| 464 | /* TODO: Set RPS. */ |
| 465 | pci_write_config16(ctrl->d0, RPS, 0x0001); |
| 466 | |
| 467 | /* TODO: Set SDRAMC. */ |
| 468 | // pci_write_config16(ctrl->d0, SDRAMC, 0x0000); |
| 469 | |
| 470 | /* TODO: Set PGPOL. */ |
| 471 | pci_write_config16(ctrl->d0, PGPOL, 0x0107); |
| 472 | |
| 473 | /* TODO: Set NBXCFG. */ |
| 474 | // pci_write_config32(ctrl->d0, NBXCFG, 0x0100220c); |
| 475 | |
| 476 | /* TODO: Set PMCR? */ |
| 477 | // pci_write_config8(ctrl->d0, PMCR, 0x14); |
| 478 | // pci_write_config8(ctrl->d0, PMCR, 0x10); |
| 479 | |
| 480 | /* TODO? */ |
| 481 | // pci_write_config8(ctrl->d0, MLT, 0x40); |
| 482 | // pci_write_config8(ctrl->d0, DRAMT, 0x03); |
| 483 | // pci_write_config8(ctrl->d0, MBSC, 0x03); |
| 484 | // pci_write_config8(ctrl->d0, SCRR, 0x38); |
Richard Smith | cb8eab4 | 2006-07-24 04:25:47 +0000 | [diff] [blame] | 485 | } |
| 486 | |
Uwe Hermann | 1a9c892 | 2007-04-01 17:24:03 +0000 | [diff] [blame] | 487 | /** |
| 488 | * Enable SDRAM. |
| 489 | * |
| 490 | * @param Number of controllers |
| 491 | * @param Memory controller |
| 492 | */ |
| 493 | static void sdram_enable(int controllers, const struct mem_controller *ctrl) |
Richard Smith | cb8eab4 | 2006-07-24 04:25:47 +0000 | [diff] [blame] | 494 | { |
Uwe Hermann | 1a9c892 | 2007-04-01 17:24:03 +0000 | [diff] [blame] | 495 | int i; |
Richard Smith | cb8eab4 | 2006-07-24 04:25:47 +0000 | [diff] [blame] | 496 | |
Uwe Hermann | 1a9c892 | 2007-04-01 17:24:03 +0000 | [diff] [blame] | 497 | /* TODO: Use a delay here? Needed? */ |
| 498 | mdelay(200); |
Richard Smith | cb8eab4 | 2006-07-24 04:25:47 +0000 | [diff] [blame] | 499 | |
Uwe Hermann | 1a9c892 | 2007-04-01 17:24:03 +0000 | [diff] [blame] | 500 | /* TODO: How long should the delays be? Fix later. */ |
Richard Smith | cb8eab4 | 2006-07-24 04:25:47 +0000 | [diff] [blame] | 501 | |
Uwe Hermann | 1a9c892 | 2007-04-01 17:24:03 +0000 | [diff] [blame] | 502 | /* 1. Apply NOP. */ |
| 503 | PRINT_DEBUG("RAM Enable 1: Apply NOP\r\n"); |
| 504 | do_ram_command(ctrl, RAM_COMMAND_NOP, 0); |
| 505 | mdelay(10); |
Richard Smith | cb8eab4 | 2006-07-24 04:25:47 +0000 | [diff] [blame] | 506 | |
Uwe Hermann | 1a9c892 | 2007-04-01 17:24:03 +0000 | [diff] [blame] | 507 | /* 2. Precharge all. Wait tRP. */ |
| 508 | PRINT_DEBUG("RAM Enable 2: Precharge all\r\n"); |
| 509 | do_ram_command(ctrl, RAM_COMMAND_PRECHARGE, 0); |
| 510 | mdelay(10); |
Richard Smith | cb8eab4 | 2006-07-24 04:25:47 +0000 | [diff] [blame] | 511 | |
Uwe Hermann | 1a9c892 | 2007-04-01 17:24:03 +0000 | [diff] [blame] | 512 | /* 3. Perform 8 refresh cycles. Wait tRC each time. */ |
| 513 | PRINT_DEBUG("RAM Enable 3: CBR\r\n"); |
| 514 | for (i = 0; i < 8; i++) { |
| 515 | do_ram_command(ctrl, RAM_COMMAND_CBR, 0); |
| 516 | mdelay(10); |
Richard Smith | cb8eab4 | 2006-07-24 04:25:47 +0000 | [diff] [blame] | 517 | } |
Uwe Hermann | 1a9c892 | 2007-04-01 17:24:03 +0000 | [diff] [blame] | 518 | |
| 519 | /* 4. Mode register set. Wait two memory cycles. */ |
| 520 | PRINT_DEBUG("RAM Enable 4: Mode register set\r\n"); |
| 521 | do_ram_command(ctrl, RAM_COMMAND_MRS, 0x1d0); |
| 522 | // TODO: Is 0x1d0 correct? |
| 523 | // do_ram_command(ctrl, RAM_COMMAND_MRS, 0x1d0000); |
| 524 | mdelay(10); |
| 525 | mdelay(10); |
| 526 | |
| 527 | /* 5. Normal operation. */ |
| 528 | PRINT_DEBUG("RAM Enable 5: Normal operation\r\n"); |
| 529 | do_ram_command(ctrl, RAM_COMMAND_NORMAL, 0); |
| 530 | mdelay(10); |
| 531 | |
| 532 | /* 6. Finally enable refresh. */ |
| 533 | PRINT_DEBUG("RAM Enable 6: Enable refresh\r\n"); |
| 534 | // pci_write_config8(ctrl->d0, PMCR, 0x10); |
| 535 | spd_enable_refresh(ctrl); |
| 536 | mdelay(10); |
| 537 | |
| 538 | PRINT_DEBUG("Northbridge following SDRAM init:\r\n"); |
| 539 | DUMPNORTH(); |
Richard Smith | cb8eab4 | 2006-07-24 04:25:47 +0000 | [diff] [blame] | 540 | } |