Vladimir Serbinenko | 9bf05de | 2013-11-14 19:11:19 +0100 | [diff] [blame^] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2007-2009 coresystems GmbH |
| 5 | * Copyright (C) 2011 Sven Schnelle <svens@stackframe.org> |
| 6 | * Copyright (C) 2013 Vladimir Serbinenko <phcoder@gmail.com> |
| 7 | * |
| 8 | * This program is free software; you can redistribute it and/or |
| 9 | * modify it under the terms of the GNU General Public License as |
| 10 | * published by the Free Software Foundation; version 2 of |
| 11 | * the License. |
| 12 | * |
| 13 | * This program is distributed in the hope that it will be useful, |
| 14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 16 | * GNU General Public License for more details. |
| 17 | * |
| 18 | * You should have received a copy of the GNU General Public License |
| 19 | * along with this program; if not, write to the Free Software |
| 20 | * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, |
| 21 | * MA 02110-1301 USA |
| 22 | */ |
| 23 | |
| 24 | /* __PRE_RAM__ means: use "unsigned" for device, not a struct. */ |
| 25 | |
| 26 | #include <stdint.h> |
| 27 | #include <string.h> |
| 28 | #include <arch/io.h> |
| 29 | #include <device/pci_def.h> |
| 30 | #include <device/pnp_def.h> |
| 31 | #include <cpu/x86/lapic.h> |
| 32 | #include <lib.h> |
| 33 | #include <pc80/mc146818rtc.h> |
| 34 | #include <console/console.h> |
| 35 | #include <cpu/x86/bist.h> |
| 36 | #include <ec/acpi/ec.h> |
| 37 | #include <delay.h> |
| 38 | #include <timestamp.h> |
| 39 | #include <cbmem.h> |
| 40 | |
| 41 | #include "gpio.h" |
| 42 | #include "dock.h" |
| 43 | #include "arch/early_variables.h" |
| 44 | #include "southbridge/intel/ibexpeak/pch.h" |
| 45 | #include "northbridge/intel/nehalem/nehalem.h" |
| 46 | |
| 47 | #include "northbridge/intel/nehalem/raminit.h" |
| 48 | #include "southbridge/intel/ibexpeak/me.h" |
| 49 | |
| 50 | static void pch_enable_lpc(void) |
| 51 | { |
| 52 | /* X201 EC Decode Range Port60/64, Port62/66 */ |
| 53 | /* Enable EC, PS/2 Keyboard/Mouse */ |
| 54 | pci_write_config16(PCH_LPC_DEV, LPC_EN, |
| 55 | CNF2_LPC_EN | CNF1_LPC_EN | MC_LPC_EN | KBC_LPC_EN | |
| 56 | COMA_LPC_EN); |
| 57 | |
| 58 | pci_write_config32(PCH_LPC_DEV, LPC_GEN1_DEC, 0x7c1601); |
| 59 | pci_write_config32(PCH_LPC_DEV, LPC_GEN2_DEC, 0xc15e1); |
| 60 | pci_write_config32(PCH_LPC_DEV, LPC_GEN3_DEC, 0x1c1681); |
| 61 | pci_write_config32(PCH_LPC_DEV, LPC_GEN4_DEC, (0x68 & ~3) | 0x00040001); |
| 62 | |
| 63 | pci_write_config16(PCH_LPC_DEV, LPC_IO_DEC, 0x10); |
| 64 | |
| 65 | pci_write_config32(PCH_LPC_DEV, 0xd0, 0x0); |
| 66 | pci_write_config32(PCH_LPC_DEV, 0xdc, 0x0); |
| 67 | |
| 68 | pci_write_config8(PCH_LPC_DEV, GEN_PMCON_3, |
| 69 | (pci_read_config8(PCH_LPC_DEV, GEN_PMCON_3) & ~2) | 1); |
| 70 | |
| 71 | pci_write_config32(PCH_LPC_DEV, ETR3, |
| 72 | pci_read_config32(PCH_LPC_DEV, ETR3) & ~ETR3_CF9GR); |
| 73 | } |
| 74 | |
| 75 | static void rcba_config(void) |
| 76 | { |
| 77 | static const u32 rcba_dump3[] = { |
| 78 | /* 30fc */ 0x00000000, |
| 79 | /* 3100 */ 0x04341200, 0x00000000, 0x40043214, 0x00014321, |
| 80 | /* 3110 */ 0x00000002, 0x30003214, 0x00000001, 0x00000002, |
| 81 | /* 3120 */ 0x00000000, 0x00002321, 0x00000000, 0x00000000, |
| 82 | /* 3130 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, |
| 83 | /* 3140 */ 0x00003107, 0x76543210, 0x00000010, 0x00007654, |
| 84 | /* 3150 */ 0x00000004, 0x00000000, 0x00000000, 0x00003210, |
| 85 | /* 3160 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, |
| 86 | /* 3170 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, |
| 87 | /* 3180 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, |
| 88 | /* 3190 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, |
| 89 | /* 31a0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, |
| 90 | /* 31b0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, |
| 91 | /* 31c0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, |
| 92 | /* 31d0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, |
| 93 | /* 31e0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, |
| 94 | /* 31f0 */ 0x00000000, 0x00000000, 0x00000000, 0x03000000, |
| 95 | /* 3200 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, |
| 96 | /* 3210 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, |
| 97 | /* 3220 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, |
| 98 | /* 3230 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, |
| 99 | /* 3240 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, |
| 100 | /* 3250 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, |
| 101 | /* 3260 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, |
| 102 | /* 3270 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, |
| 103 | /* 3280 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, |
| 104 | /* 3290 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, |
| 105 | /* 32a0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, |
| 106 | /* 32b0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, |
| 107 | /* 32c0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, |
| 108 | /* 32d0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, |
| 109 | /* 32e0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, |
| 110 | /* 32f0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, |
| 111 | /* 3300 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, |
| 112 | /* 3310 */ 0x02060100, 0x0000000f, 0x01020000, 0x80000000, |
| 113 | /* 3320 */ 0x00000000, 0x04000000, 0x00000000, 0x00000000, |
| 114 | /* 3330 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, |
| 115 | /* 3340 */ 0x000fffff, 0x00000000, 0x00000000, 0x00000000, |
| 116 | /* 3350 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, |
| 117 | /* 3360 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, |
| 118 | /* 3370 */ 0x00000000, 0x00000000, 0x7f8fdfff, 0x00000000, |
| 119 | /* 3380 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, |
| 120 | /* 3390 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, |
| 121 | /* 33a0 */ 0x00003900, 0x00000000, 0x00000000, 0x00000000, |
| 122 | /* 33b0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, |
| 123 | /* 33c0 */ 0x00010000, 0x00000000, 0x00000000, 0x0001004b, |
| 124 | /* 33d0 */ 0x06000008, 0x00010000, 0x00000000, 0x00000000, |
| 125 | /* 33e0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, |
| 126 | /* 33f0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, |
| 127 | /* 3400 */ 0x0000001c, 0x00000080, 0x00000000, 0x00000000, |
| 128 | /* 3410 */ 0x00000c61, 0x00000000, 0x16e61fe1, 0xbf4f001f, |
| 129 | /* 3420 */ 0x00000000, 0x00060010, 0x0000001d, 0x00000000, |
| 130 | /* 3430 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, |
| 131 | /* 3440 */ 0xdeaddeed, 0x00000000, 0x00000000, 0x00000000, |
| 132 | /* 3450 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, |
| 133 | /* 3460 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, |
| 134 | /* 3470 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, |
| 135 | /* 3480 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, |
| 136 | /* 3490 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, |
| 137 | /* 34a0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, |
| 138 | /* 34b0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, |
| 139 | /* 34c0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, |
| 140 | /* 34d0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, |
| 141 | /* 34e0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, |
| 142 | /* 34f0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, |
| 143 | /* 3500 */ 0x20000557, 0x2000055f, 0x2000074b, 0x2000074b, |
| 144 | /* 3510 */ 0x20000557, 0x2000014b, 0x2000074b, 0x2000074b, |
| 145 | /* 3520 */ 0x2000074b, 0x2000074b, 0x2000055f, 0x2000055f, |
| 146 | /* 3530 */ 0x20000557, 0x2000055f, 0x00000000, 0x00000000, |
| 147 | /* 3540 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, |
| 148 | /* 3550 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, |
| 149 | /* 3560 */ 0x00000001, 0x000026a3, 0x00040002, 0x01000052, |
| 150 | /* 3570 */ 0x02000772, 0x16000f8f, 0x1800ff4f, 0x0001d630, |
| 151 | /* 3580 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, |
| 152 | /* 3590 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, |
| 153 | /* 35a0 */ 0xfc000201, 0x3c000201, 0x00000000, 0x00000000, |
| 154 | /* 35b0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, |
| 155 | /* 35c0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, |
| 156 | /* 35d0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, |
| 157 | /* 35e0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, |
| 158 | /* 35f0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, |
| 159 | /* 3600 */ 0x0a001f00, 0x00000000, 0x00000000, 0x00000001, |
| 160 | /* 3610 */ 0x00010000, 0x00000000, 0x00000000, 0x00000000, |
| 161 | /* 3600 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, |
| 162 | /* 3610 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, |
| 163 | /* 3620 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, |
| 164 | /* 3630 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, |
| 165 | /* 3640 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, |
| 166 | /* 3650 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, |
| 167 | /* 3660 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, |
| 168 | /* 3670 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, |
| 169 | /* 3680 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, |
| 170 | /* 3690 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, |
| 171 | /* 36a0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, |
| 172 | /* 36b0 */ 0x00000000, 0x089c0018, 0x00000000, 0x00000000, |
| 173 | /* 36c0 */ 0x11111111, 0x00000000, 0x00000000, 0x00000000, |
| 174 | /* 36d0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, |
| 175 | /* 36e0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, |
| 176 | /* 36f0 */ 0x00000000, 0x00000000, 0x00000000, 0x00000000, |
| 177 | /* 3710 */ 0x00000000, 0x4e564d49, 0x00000000, 0x00000000, |
| 178 | }; |
| 179 | unsigned i; |
| 180 | for (i = 0; i < sizeof(rcba_dump3) / 4; i++) { |
| 181 | RCBA32(4 * i + 0x30fc) = rcba_dump3[i]; |
| 182 | (void)RCBA32(4 * i + 0x30fc); |
| 183 | } |
| 184 | } |
| 185 | |
| 186 | static void setup_smbus_5c(void) |
| 187 | { |
| 188 | u16 t3; |
| 189 | |
| 190 | /* We have a muxed bus, hence all the GPIO accesses. */ |
| 191 | if (MCHBAR8(0x2ca8) == 0) { |
| 192 | t3 = inw(DEFAULT_GPIOBASE | 0x38); |
| 193 | outw(t3 & ~0x400, DEFAULT_GPIOBASE | 0x38); |
| 194 | smbus_read_byte(0x5c, 0x06); |
| 195 | smbus_write_byte(0x5c, 0x06, 0x8f); |
| 196 | |
| 197 | smbus_read_byte(0x5c, 0x07); |
| 198 | smbus_write_byte(0x5c, 0x07, 0x8f); |
| 199 | |
| 200 | outw(t3 | 0x400, DEFAULT_GPIOBASE | 0x38); |
| 201 | } |
| 202 | |
| 203 | t3 = inw(DEFAULT_GPIOBASE | 0x38); |
| 204 | outw(t3 & ~0x400, DEFAULT_GPIOBASE | 0x38); |
| 205 | |
| 206 | smbus_read_byte(0x57, 0x55); |
| 207 | outw(t3 | 0x400, DEFAULT_GPIOBASE | 0x38); |
| 208 | } |
| 209 | |
| 210 | static inline void write_acpi32(u32 addr, u32 val) |
| 211 | { |
| 212 | outl(val, DEFAULT_PMBASE | addr); |
| 213 | } |
| 214 | |
| 215 | static inline void write_acpi16(u32 addr, u16 val) |
| 216 | { |
| 217 | outw(val, DEFAULT_PMBASE | addr); |
| 218 | } |
| 219 | |
| 220 | static inline u32 read_acpi32(u32 addr) |
| 221 | { |
| 222 | return inl(DEFAULT_PMBASE | addr); |
| 223 | } |
| 224 | |
| 225 | static inline u16 read_acpi16(u32 addr) |
| 226 | { |
| 227 | return inw(DEFAULT_PMBASE | addr); |
| 228 | } |
| 229 | |
| 230 | void main(unsigned long bist) |
| 231 | { |
| 232 | u32 reg32; |
| 233 | int s3resume = 0; |
| 234 | |
| 235 | timestamp_init(rdtsc ()); |
| 236 | |
| 237 | timestamp_add_now(TS_START_ROMSTAGE); |
| 238 | |
| 239 | if (bist == 0) |
| 240 | enable_lapic(); |
| 241 | |
| 242 | /* Force PCIRST# */ |
| 243 | pci_write_config16(PCI_DEV(0, 0x1e, 0), BCTRL, SBR); |
| 244 | pci_write_config16(PCI_DEV(0, 0, 0), BCTRL, SBR); |
| 245 | udelay(200 * 1000); |
| 246 | pci_write_config16(PCI_DEV(0, 0x1e, 0), BCTRL, 0); |
| 247 | pci_write_config16(PCI_DEV(0, 0, 0), BCTRL, 0); |
| 248 | |
| 249 | /* Enable USB Power. We need to do it early for usbdebug to work. */ |
| 250 | ec_set_bit(0x3b, 4); |
| 251 | |
| 252 | pch_enable_lpc(); |
| 253 | |
| 254 | /* Enable GPIOs */ |
| 255 | pci_write_config32(PCH_LPC_DEV, GPIO_BASE, DEFAULT_GPIOBASE | 1); |
| 256 | pci_write_config8(PCH_LPC_DEV, GPIO_CNTL, 0x10); |
| 257 | |
| 258 | setup_pch_gpios(&x201_gpio_map); |
| 259 | |
| 260 | nehalem_early_initialization(NEHALEM_MOBILE); |
| 261 | |
| 262 | /* This should probably go away. Until now it is required |
| 263 | * and mainboard specific |
| 264 | */ |
| 265 | rcba_config(); |
| 266 | |
| 267 | console_init(); |
| 268 | |
| 269 | /* Halt if there was a built in self test failure */ |
| 270 | report_bist_failure(bist); |
| 271 | |
| 272 | /* Read PM1_CNT */ |
| 273 | reg32 = inl(DEFAULT_PMBASE + 0x04); |
| 274 | printk(BIOS_DEBUG, "PM1_CNT: %08x\n", reg32); |
| 275 | if (((reg32 >> 10) & 7) == 5) { |
| 276 | u8 reg8; |
| 277 | reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xa2); |
| 278 | printk(BIOS_DEBUG, "a2: %02x\n", reg8); |
| 279 | if (!(reg8 & 0x20)) { |
| 280 | outl(reg32 & ~(7 << 10), DEFAULT_PMBASE + 0x04); |
| 281 | printk(BIOS_DEBUG, "Bad resume from S3 detected.\n"); |
| 282 | } else { |
| 283 | #if CONFIG_HAVE_ACPI_RESUME |
| 284 | printk(BIOS_DEBUG, "Resume from S3 detected.\n"); |
| 285 | s3resume = 1; |
| 286 | #else |
| 287 | printk(BIOS_DEBUG, |
| 288 | "Resume from S3 detected, but disabled.\n"); |
| 289 | #endif |
| 290 | } |
| 291 | } |
| 292 | |
| 293 | /* Enable SMBUS. */ |
| 294 | enable_smbus(); |
| 295 | |
| 296 | setup_smbus_5c(); |
| 297 | |
| 298 | outb((inb(DEFAULT_GPIOBASE | 0x3a) & ~0x2) | 0x20, |
| 299 | DEFAULT_GPIOBASE | 0x3a); |
| 300 | outb(0x50, 0x15ec); |
| 301 | outb(inb(0x15ee) & 0x70, 0x15ee); |
| 302 | |
| 303 | write_acpi16(0x2, 0x0); |
| 304 | write_acpi32(0x28, 0x0); |
| 305 | write_acpi32(0x2c, 0x0); |
| 306 | if (!s3resume) { |
| 307 | read_acpi32(0x4); |
| 308 | read_acpi32(0x20); |
| 309 | read_acpi32(0x34); |
| 310 | write_acpi16(0x0, 0x900); |
| 311 | write_acpi32(0x20, 0xffff7ffe); |
| 312 | write_acpi32(0x34, 0x56974); |
| 313 | pci_write_config8(PCH_LPC_DEV, GEN_PMCON_3, |
| 314 | pci_read_config8(PCH_LPC_DEV, GEN_PMCON_3) | 2); |
| 315 | } |
| 316 | |
| 317 | timestamp_add_now(TS_BEFORE_INITRAM); |
| 318 | |
| 319 | raminit(s3resume); |
| 320 | |
| 321 | timestamp_add_now(TS_AFTER_INITRAM); |
| 322 | |
| 323 | intel_early_me_status(); |
| 324 | |
| 325 | if (s3resume) { |
| 326 | /* Clear SLP_TYPE. This will break stage2 but |
| 327 | * we care for that when we get there. |
| 328 | */ |
| 329 | reg32 = inl(DEFAULT_PMBASE + 0x04); |
| 330 | outl(reg32 & ~(7 << 10), DEFAULT_PMBASE + 0x04); |
| 331 | } |
| 332 | #if CONFIG_HAVE_ACPI_RESUME |
| 333 | /* If there is no high memory area, we didn't boot before, so |
| 334 | * this is not a resume. In that case we just create the cbmem toc. |
| 335 | */ |
| 336 | if (s3resume && cbmem_reinit()) { |
| 337 | void *resume_backup_memory = cbmem_find(CBMEM_ID_RESUME); |
| 338 | |
| 339 | /* copy 1MB - 64K to high tables ram_base to prevent memory corruption |
| 340 | * through stage 2. We could keep stuff like stack and heap in high tables |
| 341 | * memory completely, but that's a wonderful clean up task for another |
| 342 | * day. |
| 343 | */ |
| 344 | if (resume_backup_memory) |
| 345 | memcpy(resume_backup_memory, (void *)CONFIG_RAMBASE, |
| 346 | HIGH_MEMORY_SAVE); |
| 347 | |
| 348 | /* Magic for S3 resume */ |
| 349 | pci_write_config32(PCI_DEV(0, 0x00, 0), SKPAD, 0xcafed00d); |
| 350 | } else if (s3resume) { |
| 351 | printk(BIOS_ERR, "Failed S3 resume.\n"); |
| 352 | ram_check(0x100000, 0x200000); |
| 353 | |
| 354 | /* Failed S3 resume, reset to come up cleanly */ |
| 355 | outb(0xe, 0xcf9); |
| 356 | hlt(); |
| 357 | } else { |
| 358 | pci_write_config32(PCI_DEV(0, 0x00, 0), SKPAD, 0xcafebabe); |
| 359 | quick_ram_check(); |
| 360 | } |
| 361 | #endif |
| 362 | |
| 363 | timestamp_add_now(TS_END_ROMSTAGE); |
| 364 | } |