Damien Zammit | f7060f1 | 2015-11-14 00:59:21 +1100 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2015 Damien Zammit <damien@zamaudio.com> |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or |
| 7 | * modify it under the terms of the GNU General Public License as |
| 8 | * published by the Free Software Foundation; either version 2 of |
| 9 | * the License, or (at your option) any later version. |
| 10 | * |
| 11 | * This program is distributed in the hope that it will be useful, |
| 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 14 | * GNU General Public License for more details. |
| 15 | */ |
| 16 | |
| 17 | #include <stdint.h> |
| 18 | #include <stdlib.h> |
| 19 | #include <console/console.h> |
| 20 | #include <arch/io.h> |
| 21 | #include <device/pci_def.h> |
Damien Zammit | 51fdb92 | 2016-01-18 18:34:52 +1100 | [diff] [blame] | 22 | #include <device/pci.h> |
Damien Zammit | f7060f1 | 2015-11-14 00:59:21 +1100 | [diff] [blame] | 23 | #include <cbmem.h> |
| 24 | #include <halt.h> |
| 25 | #include <string.h> |
| 26 | #include <northbridge/intel/pineview/pineview.h> |
Damien Zammit | 51fdb92 | 2016-01-18 18:34:52 +1100 | [diff] [blame] | 27 | #include <northbridge/intel/pineview/chip.h> |
Damien Zammit | f7060f1 | 2015-11-14 00:59:21 +1100 | [diff] [blame] | 28 | |
| 29 | #define LPC PCI_DEV(0, 0x1f, 0) |
| 30 | #define D0F0 PCI_DEV(0, 0, 0) |
| 31 | |
Damien Zammit | 51fdb92 | 2016-01-18 18:34:52 +1100 | [diff] [blame] | 32 | #define PCI_GCFC 0xf0 |
| 33 | #define MCH_GCFGC 0xc8c |
| 34 | #define CRCLK_PINEVIEW 0x02 |
| 35 | #define CDCLK_PINEVIEW 0x10 |
| 36 | #define MCH_HPLLVCO 0xc38 |
| 37 | |
| 38 | static void early_graphics_setup(void) |
Damien Zammit | f7060f1 | 2015-11-14 00:59:21 +1100 | [diff] [blame] | 39 | { |
| 40 | u8 reg8; |
| 41 | u16 reg16; |
| 42 | u32 reg32; |
| 43 | |
Damien Zammit | 51fdb92 | 2016-01-18 18:34:52 +1100 | [diff] [blame] | 44 | const struct device *d0f0 = dev_find_slot(0, PCI_DEVFN(0,0)); |
| 45 | const struct northbridge_intel_pineview_config *config = d0f0->chip_info; |
Damien Zammit | f7060f1 | 2015-11-14 00:59:21 +1100 | [diff] [blame] | 46 | |
Damien Zammit | 51fdb92 | 2016-01-18 18:34:52 +1100 | [diff] [blame] | 47 | pci_write_config8(D0F0, DEVEN, BOARD_DEVEN); |
| 48 | pci_write_config16(D0F0, GGC, 0x130); /* 1MB GTT 8MB UMA */ |
Damien Zammit | f7060f1 | 2015-11-14 00:59:21 +1100 | [diff] [blame] | 49 | |
Damien Zammit | 51fdb92 | 2016-01-18 18:34:52 +1100 | [diff] [blame] | 50 | printk(BIOS_SPEW, "Set GFX clocks..."); |
| 51 | reg16 = MCHBAR16(MCH_GCFGC); |
| 52 | MCHBAR16(MCH_GCFGC) = reg16 | (1 << 9); |
| 53 | reg16 &= ~0x7f; |
| 54 | reg16 |= CDCLK_PINEVIEW | CRCLK_PINEVIEW; |
| 55 | reg16 &= ~(1 << 9); |
| 56 | MCHBAR16(MCH_GCFGC) = reg16; |
Damien Zammit | f7060f1 | 2015-11-14 00:59:21 +1100 | [diff] [blame] | 57 | |
Damien Zammit | 51fdb92 | 2016-01-18 18:34:52 +1100 | [diff] [blame] | 58 | /* Graphics core */ |
| 59 | reg8 = MCHBAR8(MCH_HPLLVCO); |
| 60 | reg8 &= 0x7; |
Damien Zammit | f7060f1 | 2015-11-14 00:59:21 +1100 | [diff] [blame] | 61 | |
Damien Zammit | 51fdb92 | 2016-01-18 18:34:52 +1100 | [diff] [blame] | 62 | reg16 = pci_read_config16(PCI_DEV(0,2,0), 0xcc) & ~0x1ff; |
Damien Zammit | f7060f1 | 2015-11-14 00:59:21 +1100 | [diff] [blame] | 63 | |
Damien Zammit | 51fdb92 | 2016-01-18 18:34:52 +1100 | [diff] [blame] | 64 | if (reg8 == 0x4) { |
| 65 | /* 2666MHz */ |
| 66 | reg16 |= 0xad; |
| 67 | } else if (reg8 == 0) { |
| 68 | /* 3200MHz */ |
| 69 | reg16 |= 0xa0; |
| 70 | } else if (reg8 == 1) { |
| 71 | /* 4000MHz */ |
| 72 | reg16 |= 0xad; |
| 73 | } |
Damien Zammit | f7060f1 | 2015-11-14 00:59:21 +1100 | [diff] [blame] | 74 | |
Damien Zammit | 51fdb92 | 2016-01-18 18:34:52 +1100 | [diff] [blame] | 75 | pci_write_config16(PCI_DEV(0,2,0), 0xcc, reg16); |
| 76 | |
| 77 | pci_write_config8(PCI_DEV(0,2,0), 0x62, |
| 78 | pci_read_config8(PCI_DEV(0,2,0), 0x62) & ~0x3); |
| 79 | pci_write_config8(PCI_DEV(0,2,0), 0x62, |
| 80 | pci_read_config8(PCI_DEV(0,2,0), 0x62) | 2); |
| 81 | |
| 82 | if (config->use_crt) { |
| 83 | /* Enable VGA */ |
| 84 | MCHBAR32(0xb08) = MCHBAR32(0xb08) | (1 << 15); |
| 85 | } else { |
| 86 | /* Disable VGA */ |
| 87 | MCHBAR32(0xb08) = MCHBAR32(0xb08) & ~(1 << 15); |
| 88 | } |
| 89 | |
| 90 | if (config->use_lvds) { |
| 91 | /* Enable LVDS */ |
| 92 | reg32 = MCHBAR32(0x3004); |
| 93 | reg32 &= ~0xf1000000; |
| 94 | reg32 |= 0x90000000; |
| 95 | MCHBAR32(0x3004) = reg32; |
| 96 | MCHBAR32(0x3008) = MCHBAR32(0x3008) | (1 << 9); |
| 97 | } else { |
| 98 | /* Disable LVDS */ |
| 99 | MCHBAR32(0xb08) = MCHBAR32(0xb08) | (3 << 25); |
| 100 | } |
| 101 | |
| 102 | MCHBAR32(0xff4) = 0x0c6db8b5f; |
| 103 | MCHBAR16(0xff8) = 0x24f; |
| 104 | |
| 105 | MCHBAR32(0xb08) = MCHBAR32(0xb08) & 0xffffff00; |
| 106 | MCHBAR32(0xb08) = MCHBAR32(0xb08) | (1 << 5); |
| 107 | |
| 108 | /* Legacy backlight control */ |
| 109 | pci_write_config8(PCI_DEV(0, 2, 0), 0xf4, 0x4c); |
| 110 | } |
| 111 | |
| 112 | static void early_misc_setup(void) |
| 113 | { |
| 114 | u32 reg32; |
Damien Zammit | f7060f1 | 2015-11-14 00:59:21 +1100 | [diff] [blame] | 115 | |
| 116 | reg32 = MCHBAR32(0x30); |
| 117 | MCHBAR32(0x30) = 0x21800; |
| 118 | DMIBAR32(0x2c) = 0x86000040; |
Damien Zammit | f7060f1 | 2015-11-14 00:59:21 +1100 | [diff] [blame] | 119 | pci_write_config32(PCI_DEV(0, 0x1e, 0), 0x18, 0x00020200); |
| 120 | pci_write_config32(PCI_DEV(0, 0x1e, 0), 0x18, 0x00000000); |
Damien Zammit | f7060f1 | 2015-11-14 00:59:21 +1100 | [diff] [blame] | 121 | |
Damien Zammit | 51fdb92 | 2016-01-18 18:34:52 +1100 | [diff] [blame] | 122 | early_graphics_setup(); |
Damien Zammit | f7060f1 | 2015-11-14 00:59:21 +1100 | [diff] [blame] | 123 | |
Damien Zammit | f7060f1 | 2015-11-14 00:59:21 +1100 | [diff] [blame] | 124 | reg32 = MCHBAR32(0x40); |
| 125 | MCHBAR32(0x40) = 0x0; |
| 126 | reg32 = MCHBAR32(0x40); |
| 127 | MCHBAR32(0x40) = 0x8; |
| 128 | |
| 129 | pci_write_config8(LPC, 0x8, 0x1d); |
| 130 | pci_write_config8(LPC, 0x8, 0x0); |
| 131 | RCBA32(0x3410) = 0x00020465; |
| 132 | RCBA32(0x88) = 0x0011d000; |
| 133 | RCBA32(0x1fc) = 0x60f; |
| 134 | RCBA32(0x1f4) = 0x86000040; |
| 135 | RCBA32(0x214) = 0x10030509; |
| 136 | RCBA32(0x218) = 0x00020504; |
| 137 | RCBA32(0x220) = 0xc5; |
| 138 | RCBA32(0x3430) = 0x1; |
| 139 | RCBA32(0x2027) = 0x38f6a70d; |
| 140 | RCBA16(0x3e08) = 0x0080; |
| 141 | RCBA16(0x3e48) = 0x0080; |
| 142 | RCBA32(0x3e0e) = 0x00000080; |
| 143 | RCBA32(0x3e4e) = 0x00000080; |
| 144 | RCBA32(0x2034) = 0xb24577cc; |
| 145 | RCBA32(0x1c) = 0x03128010; |
| 146 | RCBA32(0x2010) = 0x400; |
| 147 | RCBA32(0x3400) = 0x4; |
| 148 | RCBA32(0x2080) = 0x18006007; |
| 149 | RCBA32(0x20a0) = 0x18006007; |
| 150 | RCBA32(0x20c0) = 0x18006007; |
| 151 | RCBA32(0x20e0) = 0x18006007; |
| 152 | |
| 153 | pci_write_config32(PCI_DEV(0, 0x1d, 0), 0xca, 0x1); |
| 154 | pci_write_config32(PCI_DEV(0, 0x1d, 1), 0xca, 0x1); |
| 155 | pci_write_config32(PCI_DEV(0, 0x1d, 2), 0xca, 0x1); |
| 156 | pci_write_config32(PCI_DEV(0, 0x1d, 3), 0xca, 0x1); |
| 157 | |
| 158 | RCBA32(0x3100) = 0x42210; |
| 159 | RCBA32(0x3108) = 0x10004321; |
| 160 | RCBA32(0x310c) = 0x00214321; |
| 161 | RCBA32(0x3110) = 0x1; |
| 162 | RCBA32(0x3140) = 0x01460132; |
| 163 | RCBA32(0x3142) = 0x02370146; |
| 164 | RCBA32(0x3144) = 0x32010237; |
| 165 | RCBA32(0x3146) = 0x01463201; |
| 166 | RCBA32(0x3148) = 0x146; |
Damien Zammit | 51fdb92 | 2016-01-18 18:34:52 +1100 | [diff] [blame] | 167 | } |
| 168 | |
| 169 | static void pineview_setup_bars(void) |
| 170 | { |
| 171 | /* Setting up Southbridge. In the northbridge code. */ |
| 172 | printk(BIOS_DEBUG, "Setting up static southbridge registers..."); |
| 173 | pci_write_config32(LPC, RCBA, (uintptr_t)DEFAULT_RCBA | 1); |
| 174 | pci_write_config32(LPC, PMBASE, DEFAULT_PMBASE | 1); |
| 175 | pci_write_config8(LPC, 0x44 /* ACPI_CNTL */ , 0x80); /* Enable ACPI */ |
| 176 | pci_write_config32(LPC, GPIOBASE, DEFAULT_GPIOBASE | 1); |
| 177 | pci_write_config8(LPC, 0x4c /* GC */ , 0x10); /* Enable GPIOs */ |
| 178 | pci_write_config32(LPC, 0x88, 0x007c0291); |
| 179 | |
| 180 | pci_write_config32(PCI_DEV(0, 0x1e, 0), 0x1b, 0x20); |
| 181 | printk(BIOS_DEBUG, " done.\n"); |
| 182 | |
| 183 | printk(BIOS_DEBUG, "Disabling Watchdog reboot..."); |
| 184 | RCBA32(GCS) = RCBA32(GCS) | (1 << 5); /* No reset */ |
| 185 | outw((1 << 11), DEFAULT_PMBASE | 0x60 | 0x08); /* halt timer */ |
| 186 | printk(BIOS_DEBUG, " done.\n"); |
| 187 | |
| 188 | /* Enable upper 128bytes of CMOS */ |
| 189 | RCBA32(0x3400) = (1 << 2); |
| 190 | |
| 191 | printk(BIOS_DEBUG, "Setting up static northbridge registers..."); |
| 192 | pci_write_config8(D0F0, 0x8, 0x69); |
| 193 | |
| 194 | /* Set up all hardcoded northbridge BARs */ |
| 195 | pci_write_config32(D0F0, EPBAR, DEFAULT_EPBAR | 1); |
| 196 | pci_write_config32(D0F0, MCHBAR, (uintptr_t)DEFAULT_MCHBAR | 1); |
| 197 | pci_write_config32(D0F0, DMIBAR, (uintptr_t)DEFAULT_DMIBAR | 1); |
| 198 | pci_write_config32(D0F0, PMIOBAR, (uintptr_t)0x400 | 1); |
Damien Zammit | f7060f1 | 2015-11-14 00:59:21 +1100 | [diff] [blame] | 199 | |
| 200 | /* Set C0000-FFFFF to access RAM on both reads and writes */ |
| 201 | pci_write_config8(D0F0, PAM0, 0x30); |
| 202 | pci_write_config8(D0F0, PAM1, 0x33); |
| 203 | pci_write_config8(D0F0, PAM2, 0x33); |
| 204 | pci_write_config8(D0F0, PAM3, 0x33); |
| 205 | pci_write_config8(D0F0, PAM4, 0x33); |
| 206 | pci_write_config8(D0F0, PAM5, 0x33); |
| 207 | pci_write_config8(D0F0, PAM6, 0x33); |
| 208 | |
Damien Zammit | f7060f1 | 2015-11-14 00:59:21 +1100 | [diff] [blame] | 209 | printk(BIOS_DEBUG, " done.\n"); |
| 210 | } |
| 211 | |
| 212 | void pineview_early_initialization(void) |
| 213 | { |
| 214 | /* Print some chipset specific information */ |
| 215 | printk(BIOS_DEBUG, "Intel Pineview northbridge\n"); |
| 216 | |
| 217 | /* Setup all BARs required for early PCIe and raminit */ |
| 218 | pineview_setup_bars(); |
| 219 | |
Damien Zammit | 51fdb92 | 2016-01-18 18:34:52 +1100 | [diff] [blame] | 220 | /* Miscellaneous set up */ |
| 221 | early_misc_setup(); |
| 222 | |
Damien Zammit | f7060f1 | 2015-11-14 00:59:21 +1100 | [diff] [blame] | 223 | /* Change port80 to LPC */ |
| 224 | RCBA32(GCS) &= (~0x04); |
| 225 | RCBA32(0x2010) |= (1 << 10); |
| 226 | } |