blob: f9fe0e220526ef300083e544f90e74c8d32a08c7 [file] [log] [blame]
Raul E Rangeld53c2812020-06-11 14:06:11 -06001/* SPDX-License-Identifier: GPL-2.0-only */
2
3#include <stdint.h>
4#include <amdblocks/acpimmio.h>
5#include <soc/southbridge.h>
6#include <delay.h>
7
8#define FCH_AOAC_UART_FOR_CONSOLE \
9 (CONFIG_UART_FOR_CONSOLE == 0 ? FCH_AOAC_DEV_UART0 \
10 : CONFIG_UART_FOR_CONSOLE == 1 ? FCH_AOAC_DEV_UART1 \
11 : CONFIG_UART_FOR_CONSOLE == 2 ? FCH_AOAC_DEV_UART2 \
12 : CONFIG_UART_FOR_CONSOLE == 3 ? FCH_AOAC_DEV_UART3 \
13 : -1)
14#if FCH_AOAC_UART_FOR_CONSOLE == -1
15# error Unsupported UART_FOR_CONSOLE chosen
16#endif
17
18/*
19 * Table of devices that need their AOAC registers enabled and waited
20 * upon (usually about .55 milliseconds). Instead of individual delays
21 * waiting for each device to become available, a single delay will be
22 * executed. The console UART is handled separately from this table.
23 */
24const static int aoac_devs[] = {
25 FCH_AOAC_DEV_AMBA,
26 FCH_AOAC_DEV_I2C2,
27 FCH_AOAC_DEV_I2C3,
28 FCH_AOAC_DEV_I2C4,
29 FCH_AOAC_DEV_ESPI,
30};
31
Felix Held6c61b4b2020-09-12 01:01:43 +020032void power_on_aoac_device(unsigned int dev)
Raul E Rangeld53c2812020-06-11 14:06:11 -060033{
34 uint8_t byte;
35
36 /* Power on the UART and AMBA devices */
37 byte = aoac_read8(AOAC_DEV_D3_CTL(dev));
38 byte |= FCH_AOAC_PWR_ON_DEV;
Raul E Rangelc64755b2020-06-11 14:08:17 -060039 byte &= ~FCH_AOAC_TARGET_DEVICE_STATE;
40 byte |= FCH_AOAC_D0_INITIALIZED;
Raul E Rangeld53c2812020-06-11 14:06:11 -060041 aoac_write8(AOAC_DEV_D3_CTL(dev), byte);
42}
43
Felix Held6c61b4b2020-09-12 01:01:43 +020044void power_off_aoac_device(unsigned int dev)
Raul E Rangeld53c2812020-06-11 14:06:11 -060045{
46 uint8_t byte;
47
Felix Held9bc16ed2020-11-30 18:06:35 +010048 /* Power off the UART and AMBA devices */
Raul E Rangeld53c2812020-06-11 14:06:11 -060049 byte = aoac_read8(AOAC_DEV_D3_CTL(dev));
50 byte &= ~FCH_AOAC_PWR_ON_DEV;
51 aoac_write8(AOAC_DEV_D3_CTL(dev), byte);
52}
53
Felix Held6c61b4b2020-09-12 01:01:43 +020054bool is_aoac_device_enabled(unsigned int dev)
Raul E Rangeld53c2812020-06-11 14:06:11 -060055{
56 uint8_t byte;
57
58 byte = aoac_read8(AOAC_DEV_D3_STATE(dev));
59 byte &= (FCH_AOAC_PWR_RST_STATE | FCH_AOAC_RST_CLK_OK_STATE);
60 if (byte == (FCH_AOAC_PWR_RST_STATE | FCH_AOAC_RST_CLK_OK_STATE))
61 return true;
62 else
63 return false;
64}
65
Felix Held6c61b4b2020-09-12 01:01:43 +020066void wait_for_aoac_enabled(unsigned int dev)
Raul E Rangeld53c2812020-06-11 14:06:11 -060067{
Raul E Rangel5591b912020-06-11 16:53:57 -060068 while (!is_aoac_device_enabled(dev))
69 udelay(100);
Raul E Rangeld53c2812020-06-11 14:06:11 -060070}
71
72void enable_aoac_devices(void)
73{
Felix Held6c61b4b2020-09-12 01:01:43 +020074 unsigned int i;
Raul E Rangeld53c2812020-06-11 14:06:11 -060075
76 for (i = 0; i < ARRAY_SIZE(aoac_devs); i++)
77 power_on_aoac_device(aoac_devs[i]);
Raul E Rangel5591b912020-06-11 16:53:57 -060078
Felix Held097e4492020-06-16 15:35:20 +020079 if (CONFIG(PICASSO_CONSOLE_UART))
Raul E Rangel5591b912020-06-11 16:53:57 -060080 power_on_aoac_device(FCH_AOAC_UART_FOR_CONSOLE);
Raul E Rangeld53c2812020-06-11 14:06:11 -060081
82 /* Wait for AOAC devices to indicate power and clock OK */
Raul E Rangel5591b912020-06-11 16:53:57 -060083 for (i = 0; i < ARRAY_SIZE(aoac_devs); i++)
84 wait_for_aoac_enabled(aoac_devs[i]);
85
Felix Held097e4492020-06-16 15:35:20 +020086 if (CONFIG(PICASSO_CONSOLE_UART))
Raul E Rangel5591b912020-06-11 16:53:57 -060087 wait_for_aoac_enabled(FCH_AOAC_UART_FOR_CONSOLE);
Raul E Rangeld53c2812020-06-11 14:06:11 -060088}