Mono | 9b90824 | 2014-03-02 18:40:36 +0100 | [diff] [blame^] | 1 | ## |
| 2 | ## This file is part of the coreboot project. |
| 3 | ## |
| 4 | ## Copyright (C) 2007-2009 coresystems GmbH |
| 5 | ## Copyright (C) 2011 Sven Schnelle <svens@stackframe.org> |
| 6 | ## |
| 7 | ## This program is free software; you can redistribute it and/or |
| 8 | ## modify it under the terms of the GNU General Public License as |
| 9 | ## published by the Free Software Foundation; version 2 of |
| 10 | ## the License. |
| 11 | ## |
| 12 | ## This program is distributed in the hope that it will be useful, |
| 13 | ## but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 14 | ## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 15 | ## GNU General Public License for more details. |
| 16 | ## |
| 17 | ## You should have received a copy of the GNU General Public License |
| 18 | ## along with this program; if not, write to the Free Software |
| 19 | ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, |
| 20 | ## MA 02110-1301 USA |
| 21 | ## |
| 22 | |
| 23 | chip northbridge/intel/i945 |
| 24 | |
| 25 | register "gpu_hotplug" = "0x00000220" |
| 26 | register "gpu_lvds_use_spread_spectrum_clock" = "1" |
| 27 | register "gpu_lvds_is_dual_channel" = "0" |
| 28 | register "gpu_backlight" = "0x1280128" |
| 29 | |
| 30 | device cpu_cluster 0 on |
| 31 | chip cpu/intel/socket_mFCPGA478 |
| 32 | device lapic 0 on end |
| 33 | end |
| 34 | end |
| 35 | |
| 36 | device domain 0 on |
| 37 | device pci 00.0 on # Host bridge |
| 38 | subsystemid 0x8086 0x7270 |
| 39 | end |
| 40 | device pci 02.0 on # VGA controller |
| 41 | subsystemid 0x8086 0x7270 |
| 42 | end |
| 43 | device pci 02.1 on # display controller |
| 44 | subsystemid 0x17aa 0x201a |
| 45 | end |
| 46 | chip southbridge/intel/i82801gx |
| 47 | register "pirqa_routing" = "0x0b" |
| 48 | register "pirqb_routing" = "0x0b" |
| 49 | register "pirqc_routing" = "0x0b" |
| 50 | register "pirqd_routing" = "0x0b" |
| 51 | register "pirqe_routing" = "0x0b" |
| 52 | register "pirqf_routing" = "0x0b" |
| 53 | register "pirqg_routing" = "0x0b" |
| 54 | register "pirqh_routing" = "0x0b" |
| 55 | |
| 56 | # GPI routing |
| 57 | # 0 No effect (default) |
| 58 | # 1 SMI# (if corresponding ALT_GPI_SMI_EN bit is also set) |
| 59 | # 2 SCI (if corresponding GPIO_EN bit is also set) |
| 60 | register "gpi13_routing" = "2" |
| 61 | register "gpi12_routing" = "1" |
| 62 | register "gpi8_routing" = "2" |
| 63 | |
| 64 | register "sata_ahci" = "0x1" |
| 65 | register "sata_ports_implemented" = "0x04" |
| 66 | |
| 67 | register "gpe0_en" = "0x11000006" |
| 68 | register "alt_gp_smi_en" = "0x1000" |
| 69 | |
| 70 | register "ide_enable_primary" = "1" |
| 71 | register "ide_enable_secondary" = "1" |
| 72 | |
| 73 | register "c4onc3_enable" = "1" |
| 74 | device pci 1b.0 on # Audio Controller |
| 75 | subsystemid 0x17aa 0x2010 |
| 76 | end |
| 77 | device pci 1c.0 on end # Ethernet |
| 78 | device pci 1c.1 on end # Atheros WLAN |
| 79 | device pci 1d.0 on # USB UHCI |
| 80 | subsystemid 0x8086 0x7270 |
| 81 | end |
| 82 | device pci 1d.1 on # USB UHCI |
| 83 | subsystemid 0x8086 0x7270 |
| 84 | end |
| 85 | device pci 1d.2 on # USB UHCI |
| 86 | subsystemid 0x8086 0x7270 |
| 87 | end |
| 88 | device pci 1d.3 on # USB UHCI |
| 89 | subsystemid 0x8086 0x7270 |
| 90 | end |
| 91 | device pci 1d.7 on # USB2 EHCI |
| 92 | subsystemid 0x8086 0x7270 |
| 93 | end |
| 94 | device pci 1f.0 on # PCI-LPC bridge |
| 95 | subsystemid 0x8086 0x7270 |
| 96 | end |
| 97 | device pci 1f.1 on # IDE |
| 98 | subsystemid 0x8086 0x7270 |
| 99 | end |
| 100 | device pci 1f.2 on # SATA |
| 101 | subsystemid 0x8086 0x7270 |
| 102 | end |
| 103 | device pci 1f.3 on # SMBUS |
| 104 | subsystemid 0x8086 0x7270 |
| 105 | end |
| 106 | end |
| 107 | end |
| 108 | end |